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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 1998-10-01 18:50:43 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 1998-10-01 18:50:43 +0000 |
| commit | 086836e10e022ccb1da931a975a307c7f326b14a (patch) | |
| tree | 92b5d3d2d8f0705762166654b10d6fa71669fdd6 /c/src/exec/score/cpu/powerpc/cpu.h | |
| parent | Regenerated. (diff) | |
| download | rtems-086836e10e022ccb1da931a975a307c7f326b14a.tar.bz2 | |
Patch from Thomas Doerfler <td@imd.m.isar.de> to improve 403 support.
- c/src/exec/score/cpu/powerpc/ppc.h: some small changes
(added ppc403 characteristics like a exception vector prefix
register, some special register definitions). I am quite sure, they
are compatible with the existing sources, although I did not check
- c/src/exec/score/cpu/powerpc/cpu.c: There is one severe
limitation in the exception entries: Due to the current code
arrangement, the "branch absolute" to the ISR handler may only
jump to the first 128MByte or the last 128MByte of the 4GByte
address range. When the ppc403 is running out of ROM, the ROM
functions are located in the last 128MByte (0xFFF00000 and up).
These addresses were not handled correctly (sign reduced) in
"install_raw_handler". The change I added should work on existing
ppc BSPs aswell...
Diffstat (limited to 'c/src/exec/score/cpu/powerpc/cpu.h')
| -rw-r--r-- | c/src/exec/score/cpu/powerpc/cpu.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/c/src/exec/score/cpu/powerpc/cpu.h b/c/src/exec/score/cpu/powerpc/cpu.h index 6288b3e20a..1240f68451 100644 --- a/c/src/exec/score/cpu/powerpc/cpu.h +++ b/c/src/exec/score/cpu/powerpc/cpu.h @@ -481,7 +481,8 @@ typedef struct { boolean serial_cts_rts; unsigned32 serial_rate; unsigned32 timer_average_overhead; /* Average overhead of timer in ticks */ - unsigned32 timer_least_valid; /* Least valid number from timer */ + unsigned32 timer_least_valid; /* Least valid number from timer */ + boolean timer_internal_clock; /* TRUE, when timer runs with CPU clk */ #endif } rtems_cpu_table; |