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author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2002-03-01 16:21:12 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2002-03-01 16:21:12 +0000 |
commit | bd1ecb00d955204b7c01daffe7e6e7cb8c8a765a (patch) | |
tree | 0a3497019e1d4840c978d664a05107d00ddc69b5 /c/src/exec/score/cpu/mips/iregdef.h | |
parent | 2001-03-01 Joel Sherrill <joel@OARcorp.com> (diff) | |
download | rtems-bd1ecb00d955204b7c01daffe7e6e7cb8c8a765a.tar.bz2 |
2002-02-27 Greg Menke <gregory.menke@gsfc.nasa.gov>
* cpu_asm.S: Fixed exception return address, modified FP context
switch so FPU is properly enabled and also doesn't screw up the
exception FP handling.
* idtcpu.h: Added C0_TAR, the MIPS target address register used for
returning from exceptions.
* iregdef.h: Added R_TAR to the stack frame so the target address
can be saved on a per-exception basis. The new entry is past the
end of the frame gdb cares about, so doesn't affect gdb or cpu.h
stuff.
* rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
to obtain FPU defines without systax errors generated by the C
defintions.
* cpu.c: Improved interrupt level saves & restores.
Diffstat (limited to 'c/src/exec/score/cpu/mips/iregdef.h')
-rw-r--r-- | c/src/exec/score/cpu/mips/iregdef.h | 39 |
1 files changed, 21 insertions, 18 deletions
diff --git a/c/src/exec/score/cpu/mips/iregdef.h b/c/src/exec/score/cpu/mips/iregdef.h index 2c8e01b6d1..3584325e07 100644 --- a/c/src/exec/score/cpu/mips/iregdef.h +++ b/c/src/exec/score/cpu/mips/iregdef.h @@ -225,39 +225,42 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define R_FCSR 70 #define R_FEIR 71 #define R_TLBHI 72 + #if __mips == 1 #define R_TLBLO 73 #endif #if __mips == 3 -#define R_TLBLO0 74 +#define R_TLBLO0 73 #endif + #define R_INX 74 #define R_RAND 75 #define R_CTXT 76 #define R_EXCTYPE 77 #define R_MODE 78 #define R_PRID 79 +#define R_TAR 80 #if __mips == 1 -#define NREGS 80 +#define NREGS 81 #endif #if __mips == 3 -#define R_TLBLO1 80 -#define R_PAGEMASK 81 -#define R_WIRED 82 -#define R_COUNT 83 -#define R_COMPARE 84 -#define R_CONFIG 85 -#define R_LLADDR 86 -#define R_WATCHLO 87 -#define R_WATCHHI 88 -#define R_ECC 89 -#define R_CACHEERR 90 -#define R_TAGLO 91 -#define R_TAGHI 92 -#define R_ERRPC 93 -#define R_XCTXT 94 /* Ketan added from SIM64bit */ +#define R_TLBLO1 81 +#define R_PAGEMASK 82 +#define R_WIRED 83 +#define R_COUNT 84 +#define R_COMPARE 85 +#define R_CONFIG 86 +#define R_LLADDR 87 +#define R_WATCHLO 88 +#define R_WATCHHI 89 +#define R_ECC 90 +#define R_CACHEERR 91 +#define R_TAGLO 92 +#define R_TAGHI 93 +#define R_ERRPC 94 +#define R_XCTXT 95 /* Ketan added from SIM64bit */ -#define NREGS 95 +#define NREGS 96 #endif /* |