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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 1996-12-02 19:43:22 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 1996-12-02 19:43:22 +0000 |
| commit | f4b7e2971038a736c72cdca78e32906dea516fca (patch) | |
| tree | fc5098365b5e6e5f7d2a3493018317c228a03914 /c/src/exec/score/cpu/m68k/cpu.h | |
| parent | Added asserts for unhandled conditions which need to result in error (diff) | |
| download | rtems-f4b7e2971038a736c72cdca78e32906dea516fca.tar.bz2 | |
Update from Chris Johns <cjohns@awa.com.au> to add better support for
68000 class CPUs.
Diffstat (limited to 'c/src/exec/score/cpu/m68k/cpu.h')
| -rw-r--r-- | c/src/exec/score/cpu/m68k/cpu.h | 33 |
1 files changed, 30 insertions, 3 deletions
diff --git a/c/src/exec/score/cpu/m68k/cpu.h b/c/src/exec/score/cpu/m68k/cpu.h index 59f8d3d4b7..48caa7a0d7 100644 --- a/c/src/exec/score/cpu/m68k/cpu.h +++ b/c/src/exec/score/cpu/m68k/cpu.h @@ -139,10 +139,37 @@ typedef struct { /* variables */ -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; +SCORE_EXTERN void *_CPU_Interrupt_stack_low; +SCORE_EXTERN void *_CPU_Interrupt_stack_high; + +extern char _VBR[]; + +#if ( M68K_HAS_VBR == 0 ) + +/* + * Table of ISR handler entries that resides in RAM. The FORMAT/ID is + * pushed onto the stack. This is not is the same order as VBR processors. + * The ISR handler takes the format and uses it for dispatching the user + * handler. + * + * FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS + * + */ + +typedef struct { + unsigned16 move_a7; /* move #FORMAT_ID,%a7@- */ + unsigned16 format_id; + unsigned16 jmp; /* jmp _ISR_Handlers */ + unsigned32 isr_handler; +} _CPU_ISR_handler_entry; + +#define M68K_MOVE_A7 0x3F3C +#define M68K_JMP 0x4EF9 + /* points to jsr-exception-table in targets wo/ VBR register */ -extern char _VBR[]; +SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256]; + +#endif /* M68K_HAS_VBR */ /* constants */ |