diff options
| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 1999-10-27 17:25:53 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 1999-10-27 17:25:53 +0000 |
| commit | ae7325bdc85e1dd39f039b66ba20ca681712dcc3 (patch) | |
| tree | b90f303df4b2cefcd3155f164e16d177bcfb18f9 /c/src/exec/score/cpu/i960/i960RP.h | |
| parent | Added CVS Ids and a basic header. More header cleanup needed. (diff) | |
| download | rtems-ae7325bdc85e1dd39f039b66ba20ca681712dcc3.tar.bz2 | |
rxgen960 now compiles -- may not link.
Diffstat (limited to 'c/src/exec/score/cpu/i960/i960RP.h')
| -rw-r--r-- | c/src/exec/score/cpu/i960/i960RP.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/c/src/exec/score/cpu/i960/i960RP.h b/c/src/exec/score/cpu/i960/i960RP.h index 4cda73eff0..25ed29037a 100644 --- a/c/src/exec/score/cpu/i960/i960RP.h +++ b/c/src/exec/score/cpu/i960/i960RP.h @@ -270,13 +270,13 @@ /* Byte order bit for region configuration */ /* Set to Little Endian for the 80960RP*/ -#define BYTE_ORDER BIG_ENDIAN(0) -#define BUS_WIDTH(bw) ((bw==16)?(1<<22):(0)) | ((bw==32)?(2<<22):(0)) -#define BIG_ENDIAN(on) ((on)?(0x1<<31):0) -#define BYTE_N(n,data) (((unsigned)(data) >> (n*8)) & 0xFF) -#define BUS_WIDTH_8 0 -#define BUS_WIDTH_16 (1<<22) -#define BUS_WIDTH_32 (1<<23) +#define I960RP_BYTE_ORDER I960RP_BIG_ENDIAN(0) +#define I960RP_BUS_WIDTH(bw) ((bw==16)?(1<<22):(0)) | ((bw==32)?(2<<22):(0)) +#define I960RP_BIG_ENDIAN(on) ((on)?(0x1<<31):0) +#define I960RP_BYTE_N(n,data) (((unsigned)(data) >> (n*8)) & 0xFF) +#define I960RP_BUS_WIDTH_8 0 +#define I960RP_BUS_WIDTH_16 (1<<22) +#define I960RP_BUS_WIDTH_32 (1<<23) /* ATU Register Definitions */ |