bsp/stm32h7: bring all required changes into system_stm32h7xx for STM32H7B3I-DK BSP variant

The changes provided here are a result of a merge from various examples
system_stm32h7xx.c files provided by STMicroelectronics for the STM32H7B3I-DK
board with the original RTEMS file provided for the STM32H743I-EVAL2 board.

1 files changed, 44 insertions, 7 deletions

diff --git a/bsps/arm/stm32h7/start/system_stm32h7xx.c b/bsps/arm/stm32h7/start/system_stm32h7xx.c
index 092d853720..1f0fd04dab 100644
--- a/bsps/arm/stm32h7/start/system_stm32h7xx.c
+++ b/bsps/arm/stm32h7/start/system_stm32h7xx.c
@@ -51,7 +51,11 @@
 #include <bsp/linker-symbols.h>

 #endif /* __rtems__ */

 #if !defined  (HSE_VALUE)

+#ifdef STM32H7B3xxQ

+#define HSE_VALUE    ((uint32_t)24000000) /*!< Value of the External oscillator in Hz */

+#else

 #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */

+#endif

 #endif /* HSE_VALUE */

 

 #if !defined  (CSI_VALUE)

@@ -147,9 +151,9 @@
   */

 void SystemInit (void)

 {

-#if defined (DATA_IN_D2_SRAM)

+#if defined (DATA_IN_D2_SRAM) || defined (DATA_IN_CD_AHB_SRAM)

  __IO uint32_t tmpreg;

-#endif /* DATA_IN_D2_SRAM */

+#endif /* DATA_IN_D2_SRAM || DATA_IN_CD_AHB_SRAM */

 

   /* FPU settings ------------------------------------------------------------*/

   #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)

@@ -184,6 +188,26 @@ void SystemInit (void)
   /* Reset SRDCFGR register */

   RCC->SRDCFGR = 0x00000000;

 #endif

+#ifdef STM32H7B3xxQ

+  /* Reset PLLCKSELR register */

+  RCC->PLLCKSELR = 0x02020200;

+

+  /* Reset PLLCFGR register */

+  RCC->PLLCFGR = 0x01FF0000;

+  /* Reset PLL1DIVR register */

+  RCC->PLL1DIVR = 0x01010280;

+  /* Reset PLL1FRACR register */

+  RCC->PLL1FRACR = 0x00000000;

+

+  /* Reset PLL2DIVR register */

+  RCC->PLL2DIVR = 0x01010280;

+

+  /* Reset PLL2FRACR register */

+

+  RCC->PLL2FRACR = 0x00000000;

+  /* Reset PLL3DIVR register */

+  RCC->PLL3DIVR = 0x01010280;

+#else

   /* Reset PLLCKSELR register */

   RCC->PLLCKSELR = 0x00000000;

 

@@ -202,7 +226,7 @@ void SystemInit (void)
   RCC->PLL2FRACR = 0x00000000;

   /* Reset PLL3DIVR register */

   RCC->PLL3DIVR = 0x00000000;

-

+#endif

   /* Reset PLL3FRACR register */

   RCC->PLL3FRACR = 0x00000000;

 

@@ -222,25 +246,34 @@ void SystemInit (void)
   }

 #endif

 

-#ifndef __rtems__

 #if defined (DATA_IN_D2_SRAM)

   /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */

 #if defined(RCC_AHB2ENR_D2SRAM3EN)

   RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);

 #elif defined(RCC_AHB2ENR_D2SRAM2EN)

   RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);

+#elif DATA_IN_CD_AHB_SRAM

+  /* in case of initialized data in CD AHB SRAM, enable the CD AHB SRAM clock */

+  RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);

 #else

   RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);

 #endif /* RCC_AHB2ENR_D2SRAM3EN */

-

+#endif /* DATA_IN_D2_SRAM */

+#ifndef __rtems__

   tmpreg = RCC->AHB2ENR;

   (void) tmpreg;

-#endif /* DATA_IN_D2_SRAM */

 #else /* __rtems__ */

-  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);

   RCC->AHB2ENR;

 #endif /* __rtems__ */

 

+#ifdef STM32H7B3xxQ

+/*

+   * Disable the FMC bank1 (enabled after reset).

+   * This, prevents CPU speculation access on this bank which blocks the use of FMC during

+   * 24us. During this time the others FMC master (such as LTDC) cannot use it!

+   */

+  FMC_Bank1_R->BTCR[0] = 0x000030D2;

+#endif

 #ifndef __rtems__

 #if defined(DUAL_CORE) && defined(CORE_CM4)

   /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/

@@ -254,7 +287,11 @@ void SystemInit (void)
 

   /* Configure the Vector Table location add offset address for cortex-M7 ------------------*/

 #ifdef VECT_TAB_SRAM

+#ifdef STM32H7B3xxQ

+  SCB->VTOR = CD_AXISRAM1_BASE  | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal CD AXI-RAM */

+#else

   SCB->VTOR = D1_AXISRAM_BASE  | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */

+#endif

 #else

   SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */

 #endif