bsp/tms570: Add tms570_pbist_run_and_check()

Update #4982.

3 files changed, 33 insertions, 54 deletions

diff --git a/bsps/arm/tms570/include/bsp/tms570_selftest.h b/bsps/arm/tms570/include/bsp/tms570_selftest.h
index c46e3247a8..fdad4de64c 100644
--- a/bsps/arm/tms570/include/bsp/tms570_selftest.h
+++ b/bsps/arm/tms570/include/bsp/tms570_selftest.h
@@ -198,6 +198,8 @@ void tms570_pbist_fail( void );
 
 void tms570_pbist_stop( void );
 
+void tms570_pbist_run_and_check( uint32_t raminfoL, uint32_t algomask );
+
 void tms570_enable_parity( void );
 
 void tms570_disable_parity( void );
diff --git a/bsps/arm/tms570/start/bspstarthooks-hwinit.c b/bsps/arm/tms570/start/bspstarthooks-hwinit.c
index 593c7a9ec3..31ff4aa359 100644
--- a/bsps/arm/tms570/start/bspstarthooks-hwinit.c
+++ b/bsps/arm/tms570/start/bspstarthooks-hwinit.c
@@ -155,47 +155,13 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void )
   tms570_pbist_self_check();
 
   /* Run PBIST on STC ROM */
-  tms570_pbist_run( (uint32_t) STC_ROM_PBIST_RAM_GROUP,
+  tms570_pbist_run_and_check( (uint32_t) STC_ROM_PBIST_RAM_GROUP,
     ( (uint32_t) PBIST_TripleReadSlow | (uint32_t) PBIST_TripleReadFast ) );
 
-  /* Wait for PBIST for STC ROM to be completed */
-  /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
-  while ( tms570_pbist_is_test_completed() != TRUE ) {
-  }                                                  /* Wait */
-
-  /* Check if PBIST on STC ROM passed the self-test */
-  if ( tms570_pbist_is_test_passed() != TRUE ) {
-    /* PBIST and STC ROM failed the self-test.
-     * Need custom handler to check the memory failure
-     * and to take the appropriate next step.
-     */
-    tms570_pbist_fail();
-  }
-
-  /* Disable PBIST clocks and disable memory self-test mode */
-  tms570_pbist_stop();
-
   /* Run PBIST on PBIST ROM */
-  tms570_pbist_run( (uint32_t) PBIST_ROM_PBIST_RAM_GROUP,
+  tms570_pbist_run_and_check( (uint32_t) PBIST_ROM_PBIST_RAM_GROUP,
     ( (uint32_t) PBIST_TripleReadSlow | (uint32_t) PBIST_TripleReadFast ) );
 
-  /* Wait for PBIST for PBIST ROM to be completed */
-  /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
-  while ( tms570_pbist_is_test_completed() != TRUE ) {
-  }                                                  /* Wait */
-
-  /* Check if PBIST ROM passed the self-test */
-  if ( tms570_pbist_is_test_passed() != TRUE ) {
-    /* PBIST and STC ROM failed the self-test.
-     * Need custom handler to check the memory failure
-     * and to take the appropriate next step.
-     */
-    tms570_pbist_fail();
-  }
-
-  /* Disable PBIST clocks and disable memory self-test mode */
-  tms570_pbist_stop();
-
   if ( !tms570_running_from_tcram() ) {
     /*
      * The next sequence tests TCRAM, main TMS570 system operation RAM area.
@@ -223,26 +189,9 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void )
      * The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the
      * device datasheet.
      */
-    tms570_pbist_run( 0x08300020U,   /* ESRAM Single Port PBIST */
+    tms570_pbist_run_and_check( 0x08300020U,   /* ESRAM Single Port PBIST */
       (uint32_t) PBIST_March13N_SP );
 
-    /* Wait for PBIST for CPU RAM to be completed */
-    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
-    while ( tms570_pbist_is_test_completed() != TRUE ) {
-    }                                                  /* Wait */
-
-    /* Check if CPU RAM passed the self-test */
-    if ( tms570_pbist_is_test_passed() != TRUE ) {
-      /* CPU RAM failed the self-test.
-       * Need custom handler to check the memory failure
-       * and to take the appropriate next step.
-       */
-      tms570_pbist_fail();
-    }
-
-    /* Disable PBIST clocks and disable memory self-test mode */
-    tms570_pbist_stop();
-
     /*
      * Initialize CPU RAM.
      * This function uses the system module's hardware for auto-initialization of memories and their
diff --git a/bsps/arm/tms570/start/tms570_selftest.c b/bsps/arm/tms570/start/tms570_selftest.c
index 7fad351aee..20d0f0d352 100644
--- a/bsps/arm/tms570/start/tms570_selftest.c
+++ b/bsps/arm/tms570/start/tms570_selftest.c
@@ -9,6 +9,7 @@
  */
 
 /*
+ * Copyright (C) 2022 Airbus U.S. Space & Defense, Inc
  * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com
  *
  *
@@ -440,6 +441,33 @@ bool tms570_pbist_is_test_passed( void )
 }
 
 /**
+ * Helper method that will run a pbist test and blocks until it finishes
+ * Reduces code duplication in start system start hooks
+ */
+void tms570_pbist_run_and_check(uint32_t raminfoL, uint32_t algomask)
+{
+  /* Run PBIST on region */
+  tms570_pbist_run(raminfoL, algomask);
+
+  /* Wait for PBIST for region to be completed */
+  /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+  while (!tms570_pbist_is_test_completed()) {
+  }                                                  /* Wait */
+
+  /* Check if PBIST on region passed the self-test */
+  if (!tms570_pbist_is_test_passed()) {
+    /* PBIST and region failed the self-test.
+     * Need custom handler to check the memory failure
+     * and to take the appropriate next step.
+     */
+    tms570_pbist_fail();
+  }
+
+  /* Disable PBIST clocks and disable memory self-test mode */
+  tms570_pbist_stop();
+}
+
+/**
  * @brief Checks to see if the PBIST Port test is completed successfully (HCG:pbistPortTestStatus)
  * @param[in] port   - Select the port to get the status.
  * @return 1 if PBIST Port test completed successfully, otherwise 0.