diff options
| author | Kinsey Moore <kinsey.moore@oarcorp.com> | 2021-01-14 07:58:15 -0600 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2021-01-14 13:32:06 -0600 |
| commit | 7c30dca2b5385c0e8ffab8331ab2f214e9741d0b (patch) | |
| tree | 7221354f80ca1cebe320071cbd1a95f77e18f021 /bsps | |
| parent | cpukit: Merge FreeBSD values for the priorities (diff) | |
| download | rtems-7c30dca2b5385c0e8ffab8331ab2f214e9741d0b.tar.bz2 | |
bsps/aarch64: Swap primary ZynqMP UART
Both Qemu and actual hardware treat the second UART in memory map as the
primary UART. This adjusts the ZynqMP BSPs to match.
Diffstat (limited to 'bsps')
| -rw-r--r-- | bsps/aarch64/xilinx-zynqmp/console/console.c | 4 | ||||
| -rw-r--r-- | bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/bsps/aarch64/xilinx-zynqmp/console/console.c b/bsps/aarch64/xilinx-zynqmp/console/console.c index a22a194782..84e158d3f6 100644 --- a/bsps/aarch64/xilinx-zynqmp/console/console.c +++ b/bsps/aarch64/xilinx-zynqmp/console/console.c @@ -46,11 +46,11 @@ static zynq_uart_context zynqmp_uart_instances[2] = { { .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ), - .regs = (volatile struct zynq_uart *) 0xff000000, + .regs = (volatile struct zynq_uart *) 0xff010000, .irq = ZYNQMP_IRQ_UART_0 }, { .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 1" ), - .regs = (volatile struct zynq_uart *) 0xff010000, + .regs = (volatile struct zynq_uart *) 0xff000000, .irq = ZYNQMP_IRQ_UART_1 } }; diff --git a/bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h b/bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h index 6546d637cf..13ce55d5b9 100644 --- a/bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h +++ b/bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h @@ -54,8 +54,8 @@ extern "C" { /* Interrupts vectors */ #define BSP_TIMER_VIRT_PPI 27 #define BSP_TIMER_PHYS_NS_PPI 30 -#define ZYNQMP_IRQ_UART_0 53 -#define ZYNQMP_IRQ_UART_1 54 +#define ZYNQMP_IRQ_UART_0 54 +#define ZYNQMP_IRQ_UART_1 53 #define ZYNQMP_IRQ_ETHERNET_0 89 #define ZYNQMP_IRQ_ETHERNET_1 91 #define ZYNQMP_IRQ_ETHERNET_2 93 |