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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-04-25 14:51:49 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-04-26 07:17:57 +0200 |
| commit | 3460c5228637b784edf68011d0e15d3f65517d61 (patch) | |
| tree | 5b9eb832672c754d315b8d01323ac50d3bad0df8 /bsps | |
| parent | bsp/psim: Move align_h.S to bsps (diff) | |
| download | rtems-3460c5228637b784edf68011d0e15d3f65517d61.tar.bz2 | |
bsps/powerpc: Move bsp-start-zero.S to bsps
This patch is a part of the BSP source reorganization.
Update #3285.
Diffstat (limited to 'bsps')
| -rw-r--r-- | bsps/powerpc/shared/start/bsp-start-zero.S | 115 |
1 files changed, 115 insertions, 0 deletions
diff --git a/bsps/powerpc/shared/start/bsp-start-zero.S b/bsps/powerpc/shared/start/bsp-start-zero.S new file mode 100644 index 0000000000..e87efff8c3 --- /dev/null +++ b/bsps/powerpc/shared/start/bsp-start-zero.S @@ -0,0 +1,115 @@ +/** + * @file + * + * @ingroup bsp_start + * + * @brief bsp_start_zero() implementation. + */ + +/* + * Copyright (c) 2010-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include <rtems/asm.h> +#include <rtems/powerpc/powerpc.h> +#include <bspopts.h> + + .globl bsp_start_zero + .globl bsp_start_zero_begin + .globl bsp_start_zero_end + .globl bsp_start_zero_size + + .section ".bsp_start_text", "ax" + .type bsp_start_zero, @function +bsp_start_zero: +bsp_start_zero_begin: + li r0, 0 + subi r11, r3, 1 + clrrwi r11, r11, PPC_CACHE_ALIGN_POWER + addi r10, r11, PPC_CACHE_ALIGNMENT + subf r11, r3, r10 + cmplw cr7, r11, r4 + add r9, r3, r4 + ble- cr7, head_end_done + mr r10, r9 +head_end_done: + subf r11, r3, r10 + addi r11, r11, 1 + mtctr r11 + + /* Head loop */ + b head_loop_update +head_loop_begin: + stb r0, 0(r3) + addi r3, r3, 1 +head_loop_update: + bdnz+ head_loop_begin + + subf r11, r3, r9 + srwi r11, r11, PPC_CACHE_ALIGN_POWER + addi r11, r11, 1 + mtctr r11 + + /* Main loop */ + b main_loop_update +main_loop_begin: +#if BSP_DATA_CACHE_ENABLED + dcbz r0, r3 + dcbf r0, r3 +#else + #if PPC_CACHE_ALIGNMENT == 32 || PPC_CACHE_ALIGNMENT == 64 + stw r0, 0(r3) + stw r0, 4(r3) + stw r0, 8(r3) + stw r0, 12(r3) + stw r0, 16(r3) + stw r0, 20(r3) + stw r0, 24(r3) + stw r0, 28(r3) + #if PPC_CACHE_ALIGNMENT == 64 + stw r0, 32(r3) + stw r0, 36(r3) + stw r0, 40(r3) + stw r0, 44(r3) + stw r0, 48(r3) + stw r0, 52(r3) + stw r0, 56(r3) + stw r0, 60(r3) + #endif + #else + #error "unsupported cache alignment" + #endif +#endif + addi r3, r3, PPC_CACHE_ALIGNMENT +main_loop_update: + bdnz+ main_loop_begin + + subf r9, r3, r9 + addi r9, r9, 1 + mtctr r9 + + /* Tail loop */ + b tail_loop_update +tail_loop_begin: + stb r0, 0(r3) + addi r3, r3, 1 +tail_loop_update: + bdnz+ tail_loop_begin + + /* Return */ + sync + isync + blr + +bsp_start_zero_end: + .set bsp_start_zero_size, bsp_start_zero_end - bsp_start_zero_begin |