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authorSebastian Huber <sebastian.huber@embedded-brains.de>2018-04-20 10:35:35 +0200
committerSebastian Huber <sebastian.huber@embedded-brains.de>2018-04-20 13:52:14 +0200
commit99648958668d3a33ee57974479b36201fe303f34 (patch)
tree6f27ea790e2823c6156e71219a4f54680263fac6 /bsps/sparc64
parentbsps: Move start files to bsps (diff)
downloadrtems-99648958668d3a33ee57974479b36201fe303f34.tar.bz2
bsps: Move startup files to bsps
Adjust build support files to new directory layout. This patch is a part of the BSP source reorganization. Update #3285.
Diffstat (limited to 'bsps/sparc64')
-rw-r--r--bsps/sparc64/niagara/start/bsp_specs9
-rw-r--r--bsps/sparc64/niagara/start/bspclean.c22
-rw-r--r--bsps/sparc64/niagara/start/m5op.h90
-rw-r--r--bsps/sparc64/niagara/start/m5op_sparc.S153
-rw-r--r--bsps/sparc64/niagara/start/m5ops.h83
-rw-r--r--bsps/sparc64/shared/start/linkcmds218
-rw-r--r--bsps/sparc64/shared/start/setvec.c57
-rw-r--r--bsps/sparc64/usiii/start/bsp_specs9
8 files changed, 641 insertions, 0 deletions
diff --git a/bsps/sparc64/niagara/start/bsp_specs b/bsps/sparc64/niagara/start/bsp_specs
new file mode 100644
index 0000000000..0b4b0db932
--- /dev/null
+++ b/bsps/sparc64/niagara/start/bsp_specs
@@ -0,0 +1,9 @@
+%rename endfile old_endfile
+%rename startfile old_startfile
+
+*startfile:
+%{!qrtems: %(old_startfile)} \
+%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}}
+
+*endfile:
+%{!qrtems: %(old_endfile)} %{!nostdlib: %{qrtems: crtend.o%s crtn.o%s}}
diff --git a/bsps/sparc64/niagara/start/bspclean.c b/bsps/sparc64/niagara/start/bspclean.c
new file mode 100644
index 0000000000..eacc264e5b
--- /dev/null
+++ b/bsps/sparc64/niagara/start/bspclean.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2014 Gedare Bloom.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp.h>
+#include <bsp/bootcard.h>
+#include <rtems/bspIo.h>
+
+#include "m5op.h"
+
+void bsp_fatal_extension(
+ rtems_fatal_source source,
+ bool always_set_to_false,
+ rtems_fatal_code code
+)
+{
+ m5_exit(0);
+}
diff --git a/bsps/sparc64/niagara/start/m5op.h b/bsps/sparc64/niagara/start/m5op.h
new file mode 100644
index 0000000000..d349e4d6bc
--- /dev/null
+++ b/bsps/sparc64/niagara/start/m5op.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ * Ali Saidi
+ */
+
+#ifndef __M5OP_H__
+#define __M5OP_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+void arm(uint64_t address);
+void quiesce(void);
+void quiesceNs(uint64_t ns);
+void quiesceCycle(uint64_t cycles);
+uint64_t quiesceTime(void);
+uint64_t rpns(void);
+void wakeCPU(uint64_t cpuid);
+
+void m5_exit(uint64_t ns_delay);
+void m5_fail(uint64_t ns_delay, uint64_t code);
+uint64_t m5_initparam(void);
+void m5_checkpoint(uint64_t ns_delay, uint64_t ns_period);
+void m5_reset_stats(uint64_t ns_delay, uint64_t ns_period);
+void m5_dump_stats(uint64_t ns_delay, uint64_t ns_period);
+void m5_dumpreset_stats(uint64_t ns_delay, uint64_t ns_period);
+uint64_t m5_readfile(void *buffer, uint64_t len, uint64_t offset);
+uint64_t m5_writefile(void *buffer, uint64_t len, uint64_t offset, const char *filename);
+void m5_debugbreak(void);
+void m5_switchcpu(void);
+void m5_addsymbol(uint64_t addr, char *symbol);
+void m5_panic(void);
+void m5_work_begin(uint64_t workid, uint64_t threadid);
+void m5_work_end(uint64_t workid, uint64_t threadid);
+
+// These operations are for critical path annotation
+void m5a_bsm(char *sm, const void *id, int flags);
+void m5a_esm(char *sm);
+void m5a_begin(int flags, char *st);
+void m5a_end(void);
+void m5a_q(const void *id, char *q, int count);
+void m5a_dq(const void *id, char *q, int count);
+void m5a_wf(const void *id, char *q, char *sm, int count);
+void m5a_we(const void *id, char *q, char *sm, int count);
+void m5a_ws(const void *id, char *q, char *sm);
+void m5a_sq(const void *id, char *q, int count, int flags);
+void m5a_aq(const void *id, char *q, int count);
+void m5a_pq(const void *id, char *q, int count);
+void m5a_l(char *lsm, const void *id, char *sm);
+void m5a_identify(uint64_t id);
+uint64_t m5a_getid(void);
+
+#define M5_AN_FL_NONE 0x0
+#define M5_AN_FL_BAD 0x2
+#define M5_AN_FL_LINK 0x10
+#define M5_AN_FL_RESET 0x20
+
+#ifdef __cplusplus
+}
+#endif
+#endif // __M5OP_H__
diff --git a/bsps/sparc64/niagara/start/m5op_sparc.S b/bsps/sparc64/niagara/start/m5op_sparc.S
new file mode 100644
index 0000000000..40248ff8bf
--- /dev/null
+++ b/bsps/sparc64/niagara/start/m5op_sparc.S
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ * Ali Saidi
+ */
+
+#define m5_op 0x2
+#define m5_op3 0x37
+
+#include "m5ops.h"
+
+#define INST(func, rs1, rs2, rd) \
+ .long (m5_op) << 30 | (rd) << 25 | (m5_op3) << 19 | (func) << 7 | \
+ (rs1) << 14 | (rs2) << 0;
+
+
+#define LEAF(func) \
+ .section ".text"; \
+ .align 4; \
+ .global func; \
+ .type func, #function; \
+func:
+
+#define END(func) \
+ .size func, (.-func)
+
+#define DEBUGBREAK INST(debugbreak_func, 0, 0, 0)
+#define M5EXIT INST(exit_func, 0, 0, 0)
+#define PANIC INST(panic_func, 0, 0, 0)
+#define READFILE INST(readfile_func, 0, 0, 0)
+
+LEAF(m5_exit)
+ retl
+ M5EXIT
+END(m5_exit)
+
+LEAF(m5_panic)
+ retl
+ PANIC
+END(m5_panic)
+
+LEAF(m5_readfile)
+ retl
+ READFILE
+END(m5_readfile)
+
+LEAF(m5_debugbreak)
+ retl
+ DEBUGBREAK
+END(m5_debugbreak)
+
+/* !!!!!! All code below here just panics !!!!!! */
+LEAF(arm)
+ retl
+ PANIC
+END(arm)
+
+LEAF(quiesce)
+ retl
+ PANIC
+END(quiesce)
+
+LEAF(quiesceNs)
+ retl
+ PANIC
+END(quiesceNs)
+
+LEAF(quiesceCycle)
+ retl
+ PANIC
+END(quiesceCycle)
+
+LEAF(quiesceTime)
+ retl
+ PANIC
+END(quiesceTime)
+
+LEAF(m5_initparam)
+ retl
+ PANIC
+END(m5_initparam)
+
+LEAF(m5_loadsymbol)
+ retl
+ PANIC
+END(m5_loadsymbol)
+
+LEAF(m5_reset_stats)
+ retl
+ PANIC
+END(m5_reset_stats)
+
+LEAF(m5_dump_stats)
+ retl
+ PANIC
+END(m5_dump_stats)
+
+LEAF(m5_dumpreset_stats)
+ retl
+ PANIC
+END(m5_dumpreset_stats)
+
+LEAF(m5_checkpoint)
+ retl
+ PANIC
+END(m5_checkpoint)
+
+LEAF(m5_switchcpu)
+ retl
+ PANIC
+END(m5_switchcpu)
+
+LEAF(m5_addsymbol)
+ retl
+ PANIC
+END(m5_addsymbol)
+
+LEAF(m5_anbegin)
+ retl
+ PANIC
+END(m5_anbegin)
+
+LEAF(m5_anwait)
+ retl
+ PANIC
+END(m5_anwait)
+
+
diff --git a/bsps/sparc64/niagara/start/m5ops.h b/bsps/sparc64/niagara/start/m5ops.h
new file mode 100644
index 0000000000..8ff1ac42f1
--- /dev/null
+++ b/bsps/sparc64/niagara/start/m5ops.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ * Ali Saidi
+ */
+
+#define arm_func 0x00
+#define quiesce_func 0x01
+#define quiescens_func 0x02
+#define quiescecycle_func 0x03
+#define quiescetime_func 0x04
+#define rpns_func 0x07
+#define wakecpu_func 0x09
+#define deprecated1_func 0x10 // obsolete ivlb
+#define deprecated2_func 0x11 // obsolete ivle
+#define deprecated3_func 0x20 // deprecated exit function
+#define exit_func 0x21
+#define fail_func 0x22
+#define initparam_func 0x30
+#define loadsymbol_func 0x31
+#define resetstats_func 0x40
+#define dumpstats_func 0x41
+#define dumprststats_func 0x42
+#define ckpt_func 0x43
+#define writefile_func 0x4F
+#define readfile_func 0x50
+#define debugbreak_func 0x51
+#define switchcpu_func 0x52
+#define addsymbol_func 0x53
+#define panic_func 0x54
+
+#define reserved2_func 0x56 // Reserved for user
+#define reserved3_func 0x57 // Reserved for user
+#define reserved4_func 0x58 // Reserved for user
+#define reserved5_func 0x59 // Reserved for user
+
+#define work_begin_func 0x5a
+#define work_end_func 0x5b
+
+// These operations are for critical path annotation
+#define annotate_func 0x55
+#define an_bsm 0x1
+#define an_esm 0x2
+#define an_begin 0x3
+#define an_end 0x4
+#define an_q 0x6
+#define an_dq 0x7
+#define an_wf 0x8
+#define an_we 0x9
+#define an_rq 0xA
+#define an_ws 0xB
+#define an_sq 0xC
+#define an_aq 0xD
+#define an_pq 0xE
+#define an_l 0xF
+#define an_identify 0x10
+#define an_getid 0x11
+
diff --git a/bsps/sparc64/shared/start/linkcmds b/bsps/sparc64/shared/start/linkcmds
new file mode 100644
index 0000000000..2f9db3a087
--- /dev/null
+++ b/bsps/sparc64/shared/start/linkcmds
@@ -0,0 +1,218 @@
+/* linkcmds
+ */
+
+/*
+ * For alignment, SPARC v9 specifies that instructions are 4-byte aligned,
+ * and the worst-case alignment requirements for data are for quad-word
+ * accesses, which must be 16-byte aligned.
+ */
+
+/*
+ * Declare some sizes.
+ */
+RamBase = DEFINED(RamBase) ? RamBase : 0x0;
+RamSize = DEFINED(RamSize) ? RamSize : 4M;
+HeapSize = DEFINED(HeapSize) ? HeapSize : 1M;
+
+RAM_END = RamBase + RamSize;
+
+/* Default linker script, for normal executables */
+OUTPUT_FORMAT("elf64-sparc")
+ENTRY(_start)
+STARTUP(start.o)
+
+MEMORY
+{
+ ram : ORIGIN = 0x0, LENGTH = 12M
+}
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .gnu.version : { *(.gnu.version) }
+ .gnu.version_d : { *(.gnu.version_d) }
+ .gnu.version_r : { *(.gnu.version_r) }
+ .rel.init : { *(.rel.init) }
+ .rela.init : { *(.rela.init) }
+ .rel.text :
+ {
+ *(.rel.text)
+ *(.rel.text.*)
+ *(.rel.gnu.linkonce.t*)
+ }
+ .rela.text :
+ {
+ *(.rela.text)
+ *(.rela.text.*)
+ *(.rela.gnu.linkonce.t*)
+ }
+ .rel.fini : { *(.rel.fini) }
+ .rela.fini : { *(.rela.fini) }
+ .rel.rodata :
+ {
+ *(.rel.rodata)
+ *(.rel.rodata.*)
+ *(.rel.gnu.linkonce.r*)
+ }
+ .rela.rodata :
+ {
+ *(.rela.rodata)
+ *(.rela.rodata.*)
+ *(.rela.gnu.linkonce.r*)
+ }
+ .rel.data :
+ {
+ *(.rel.data)
+ *(.rel.data.*)
+ *(.rel.gnu.linkonce.d*)
+ }
+ .rela.data :
+ {
+ *(.rela.data)
+ *(.rela.data.*)
+ *(.rela.gnu.linkonce.d*)
+ }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ /* Internal text space or external memory */
+ .text 0x4000 : AT (0x4000)
+ {
+ *(BOOTSTRAP);
+ *(.text*)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ /*
+ * Special FreeBSD sysctl sections.
+ */
+ . = ALIGN (16);
+ __start_set_sysctl_set = .;
+ *(set_sysctl_*);
+ __stop_set_sysctl_set = ABSOLUTE(.);
+ *(set_domain_*);
+ *(set_pseudo_*);
+
+ *(.eh_frame)
+ . = ALIGN (16);
+
+ *(.gnu.linkonce.t*)
+ *(.gcc_except_table*)
+
+ /*
+ * C++ constructors
+ */
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+
+ _rodata_start = . ;
+ *(.rodata*)
+ KEEP (*(SORT(.rtemsroset.*)))
+ *(.gnu.linkonce.r*)
+ _erodata = ALIGN( 0x10 ) ;
+
+ *(.lit)
+ *(.shdata)
+
+ . = ALIGN (16);
+ _endtext = . ;
+ _etext = . ;
+ } > ram
+
+ .tdata : AT (ADDR (.text) + SIZEOF (.text)) {
+ _TLS_Data_begin = .;
+ *(.tdata .tdata.* .gnu.linkonce.td.*)
+ _TLS_Data_end = .;
+ } > ram
+ .tbss : AT (ADDR (.tdata) + SIZEOF (.tdata)) {
+ _TLS_BSS_begin = .;
+ *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+ _TLS_BSS_end = .;
+ } > ram
+ _TLS_Data_size = _TLS_Data_end - _TLS_Data_begin;
+ _TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin;
+ _TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin;
+ _TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin;
+ _TLS_Size = _TLS_BSS_end - _TLS_Data_begin;
+ _TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
+
+ .data : AT (ADDR (.tbss) + SIZEOF (.tbss))
+ {
+ PROVIDE (__data_start = .) ;
+ data_start = . ;
+ _data_start = . ;
+ *(.data)
+ *(.data*)
+ KEEP (*(SORT(.rtemsrwset.*)))
+ *(.rodata) /* We need to include .rodata here if gcc is used */
+ *(.rodata*) /* with -fdata-sections. */
+ *(.gnu.linkonce.d*)
+ . = ALIGN(2);
+ edata = . ;
+ _edata = . ;
+ PROVIDE (__data_end = .) ;
+ } > ram
+
+ /* XXX
+ __data_load_start = LOADADDR(.data);
+ __data_load_end = __data_load_start + SIZEOF(.data);
+ */
+ . = ALIGN (16);
+ .dynamic : { *(.dynamic) } >ram
+ .jcr : { *(.jcr) } > ram
+ .shbss : { *(.shbss) } > ram
+ .bss :
+ {
+ FILL(0x00000000);
+ . = ALIGN(16);
+ __bss_start = ALIGN(0x8);
+ bss_start = .;
+ bss_start = .;
+ *(.bss .bss* .gnu.linkonce.b*)
+ *(COMMON)
+ . = ALIGN (16);
+ end = .;
+ _end = .;
+ __end = .;
+
+ . = ALIGN (16); /* arbitrary alignment */
+ PROVIDE (WorkAreaBase = .);
+ . += HeapSize;
+ PROVIDE (HeapBase = .);
+ . += HeapSize;
+ } > ram
+}
+
+
diff --git a/bsps/sparc64/shared/start/setvec.c b/bsps/sparc64/shared/start/setvec.c
new file mode 100644
index 0000000000..12c7713285
--- /dev/null
+++ b/bsps/sparc64/shared/start/setvec.c
@@ -0,0 +1,57 @@
+/* set_vector
+ *
+ * This routine installs an interrupt vector on the sun4v niagara
+ *
+ * INPUT PARAMETERS:
+ * handler - interrupt handler entry point
+ * vector - vector number
+ * type - 0 indicates raw hardware connect
+ * 1 indicates RTEMS interrupt connect
+ *
+ * OUTPUT PARAMETERS: NONE
+ *
+ * RETURNS:
+ * address of previous interrupt handler
+ *
+ * COPYRIGHT (c) 1989-1998. On-Line Applications Research Corporation (OAR).
+ * COPYRIGHT (c) 2010. Gedare Bloom.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp.h>
+
+rtems_isr_entry set_vector( /* returns old vector */
+ rtems_isr_entry handler, /* isr routine */
+ rtems_vector_number vector, /* vector number */
+ int type /* RTEMS or RAW intr */
+)
+{
+ rtems_isr_entry previous_isr;
+ uint32_t real_trap;
+ uint32_t source;
+ int bit_mask;
+
+ if ( type )
+ rtems_interrupt_catch( handler, vector, &previous_isr );
+ else
+ _CPU_ISR_install_raw_handler( vector, handler, (void *)&previous_isr );
+
+ real_trap = SPARC_REAL_TRAP_NUMBER( vector );
+
+ /* check if this is an interrupt, if so, clear and unmask interrupts for
+ * this level
+ */
+ /* Interrupts have real_trap numbers between 0x41 and 0x4F (levels 1 - 15) */
+ if (real_trap >= 0x41 && real_trap <= 0x4F) {
+ source = real_trap - 0x40;
+ bit_mask = 1<<source;
+
+ sparc64_clear_interrupt_bits(bit_mask);
+ }
+
+
+ return previous_isr;
+}
diff --git a/bsps/sparc64/usiii/start/bsp_specs b/bsps/sparc64/usiii/start/bsp_specs
new file mode 100644
index 0000000000..0b4b0db932
--- /dev/null
+++ b/bsps/sparc64/usiii/start/bsp_specs
@@ -0,0 +1,9 @@
+%rename endfile old_endfile
+%rename startfile old_startfile
+
+*startfile:
+%{!qrtems: %(old_startfile)} \
+%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}}
+
+*endfile:
+%{!qrtems: %(old_endfile)} %{!nostdlib: %{qrtems: crtend.o%s crtn.o%s}}