diff options
| author | Kinsey Moore <kinsey.moore@oarcorp.com> | 2023-09-27 11:43:50 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2023-10-24 09:52:27 -0500 |
| commit | 8a2c3af9cfaa6863c21c8ce215759e7a528b9e59 (patch) | |
| tree | 9106964f6338eab53056cb57372f3685763d22ef /bsps/shared | |
| parent | bsps/xil: Import Xilinx Cortex-R5 support (diff) | |
| download | rtems-8a2c3af9cfaa6863c21c8ce215759e7a528b9e59.tar.bz2 | |
bsps/xil: Adjust Xilinx support code for Cortex-R5
This fixes some issues in the Xilinx support code that are critical to
support the Cortex-R5F cores present in my Xilinx SoCs. The imported
Cortex-R5 xil_cache.c matches the existing information in
bsps/shared/xil/VERSION.
Diffstat (limited to 'bsps/shared')
| -rw-r--r-- | bsps/shared/xil/arm/ARMv8/xil_cache.c (renamed from bsps/shared/xil/xil_cache.c) | 0 | ||||
| -rw-r--r-- | bsps/shared/xil/arm/cortexr5/xil_mpu.c | 4 |
2 files changed, 4 insertions, 0 deletions
diff --git a/bsps/shared/xil/xil_cache.c b/bsps/shared/xil/arm/ARMv8/xil_cache.c index aef64b310a..aef64b310a 100644 --- a/bsps/shared/xil/xil_cache.c +++ b/bsps/shared/xil/arm/ARMv8/xil_cache.c diff --git a/bsps/shared/xil/arm/cortexr5/xil_mpu.c b/bsps/shared/xil/arm/cortexr5/xil_mpu.c index f8f8fd1cc9..85f8f7f8da 100644 --- a/bsps/shared/xil/arm/cortexr5/xil_mpu.c +++ b/bsps/shared/xil/arm/cortexr5/xil_mpu.c @@ -115,12 +115,16 @@ static const struct { { 0x100000000, REGION_4G }, }; +#ifndef __rtems__ #if defined (__GNUC__) XMpu_Config Mpu_Config __attribute__((section(".bootdata"))); #elif defined (__ICCARM__) #pragma default_function_attributes = @ ".bootdata" XMpu_Config Mpu_Config; #endif +#else +XMpu_Config Mpu_Config __attribute__((section(".bsp_start_data"))); +#endif /************************** Function Prototypes ******************************/ void Xil_InitializeExistingMPURegConfig(void); |