diff options
author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-10-17 09:43:55 +0200 |
---|---|---|
committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-10-17 09:58:14 +0200 |
commit | 143c8d0d948b31f7c4b40e3d7eb7ebe0b80b4915 (patch) | |
tree | e08534fcf84f9c116a88ed37fa4855e9cf177135 /bsps/shared/dev | |
parent | bsp/imx7: Add getchark() support (diff) | |
download | rtems-143c8d0d948b31f7c4b40e3d7eb7ebe0b80b4915.tar.bz2 |
serial/ns16550: Fix precision clock synthesizer
The precision clock synthesizer support broke the driver on the QorIQ
P1020. On this device the Alternate Function Register is accessed with
DLAB == 1 instead of the FIFO Control Register (FCR). Restructure the
code to account for this.
Diffstat (limited to 'bsps/shared/dev')
-rw-r--r-- | bsps/shared/dev/serial/ns16550-context.c | 31 |
1 files changed, 16 insertions, 15 deletions
diff --git a/bsps/shared/dev/serial/ns16550-context.c b/bsps/shared/dev/serial/ns16550-context.c index a783edc2e6..ce55b8309c 100644 --- a/bsps/shared/dev/serial/ns16550-context.c +++ b/bsps/shared/dev/serial/ns16550-context.c @@ -191,28 +191,22 @@ bool ns16550_probe(rtems_termios_device_context *base) (uint8_t)(( ulBaudDivisor >> 8 ) & 0xffU ) ); - /* Enable and reset transmit and receive FIFOs. TJA */ - ucDataByte = SP_FIFO_ENABLE; - (*setReg)(pNS16550, NS16550_FIFO_CONTROL, ucDataByte); - - ucDataByte = SP_FIFO_ENABLE | SP_FIFO_RXRST | SP_FIFO_TXRST; + /* Clear the divisor latch and set the character size to eight bits */ + /* with one stop bit and no parity checking. */ + ucDataByte = EIGHT_BITS; + ctx->line_control = ucDataByte; if (ctx->has_precision_clock_synthesizer) { + uint8_t fcr; + /* * Enable precision clock synthesizer. This must be done with DLAB == 1 in * the line control register. */ - ucDataByte |= 0x10; - } - - (*setReg)(pNS16550, NS16550_FIFO_CONTROL, ucDataByte); + fcr = (*getReg)(pNS16550, NS16550_FIFO_CONTROL ); + fcr |= 0x10; + (*setReg)(pNS16550, NS16550_FIFO_CONTROL, fcr); - /* Clear the divisor latch and set the character size to eight bits */ - /* with one stop bit and no parity checking. */ - ucDataByte = EIGHT_BITS; - ctx->line_control = ucDataByte; - - if (ctx->has_precision_clock_synthesizer) { (*setReg)(pNS16550, NS16550_SCRATCH_PAD, (uint8_t)(ulBaudDivisor >> 24)); (*setReg)(pNS16550, NS16550_LINE_CONTROL, ucDataByte ); (*setReg)(pNS16550, NS16550_SCRATCH_PAD, (uint8_t)(ulBaudDivisor >> 16)); @@ -220,6 +214,13 @@ bool ns16550_probe(rtems_termios_device_context *base) (*setReg)(pNS16550, NS16550_LINE_CONTROL, ucDataByte); } + /* Enable and reset transmit and receive FIFOs. TJA */ + ucDataByte = SP_FIFO_ENABLE; + (*setReg)(pNS16550, NS16550_FIFO_CONTROL, ucDataByte); + + ucDataByte = SP_FIFO_ENABLE | SP_FIFO_RXRST | SP_FIFO_TXRST; + (*setReg)(pNS16550, NS16550_FIFO_CONTROL, ucDataByte); + ns16550_enable_interrupts(ctx, NS16550_DISABLE_ALL_INTR); /* Set data terminal ready. */ |