diff options
author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2024-04-16 10:20:48 +0200 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2024-04-16 10:27:15 +0200 |
commit | 5ce7ed1feac7f1943cf7faef006e488fd104f4b3 (patch) | |
tree | 534fc6fda6cbe987e4a61875892277e5ced86723 /bsps/shared/dev/irq/arm-gicv3.c | |
parent | arm/xen: Fix BSP_INTERRUPT_VECTOR_COUNT (diff) | |
download | rtems-5ce7ed1feac7f1943cf7faef006e488fd104f4b3.tar.bz2 |
bsps/arm: Improve GICv3 support
In addtion to 1023, the GICC_IAR register may return 1022 as a special value.
Simply check for a valid interrupt vector for the dispatching.
Check the GICC_IAR again after the dispatch to quickly process a next interrupt
without having to go through the interrupt prologue and epiloge.
Diffstat (limited to 'bsps/shared/dev/irq/arm-gicv3.c')
-rw-r--r-- | bsps/shared/dev/irq/arm-gicv3.c | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c index fd7abd6a13..958b1061bd 100644 --- a/bsps/shared/dev/irq/arm-gicv3.c +++ b/bsps/shared/dev/irq/arm-gicv3.c @@ -42,12 +42,18 @@ void bsp_interrupt_dispatch(void) { - uint32_t icciar = READ_SR(ICC_IAR1); - rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar); - rtems_vector_number spurious = 1023; + while (true) { + uint32_t icciar = READ_SR(ICC_IAR1); + rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar); + uint32_t status; - if (vector != spurious) { - arm_interrupt_handler_dispatch(vector); + if (!bsp_interrupt_is_valid_vector(vector)) { + break; + } + + status = arm_interrupt_enable_interrupts(); + bsp_interrupt_handler_dispatch_unchecked(vector); + arm_interrupt_restore_interrupts(status); WRITE_SR(ICC_EOIR1, icciar); } |