Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step.  It
copied header files from arbitrary locations into the build tree.  The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

* The make preinstall step itself needs time and disk space.

* Errors in header files show up in the build tree copy.  This makes it
  hard for editors to open the right file to fix the error.

* There is no clear relationship between source and build tree header
  files.  This makes an audit of the build process difficult.

* The visibility of all header files in the build tree makes it
  difficult to enforce API barriers.  For example it is discouraged to
  use BSP-specifics in the cpukit.

* An introduction of a new build system is difficult.

* Include paths specified by the -B option are system headers.  This
  may suppress warnings.

* The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step.   All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc.  Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

* cpukit/include

* cpukit/score/cpu/@RTEMS_CPU@/include

* cpukit/libnetworking

The new BSP include directories are:

* bsps/include

* bsps/@RTEMS_CPU@/include

* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed.  The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

1 files changed, 88 insertions, 0 deletions

diff --git a/bsps/sh/gensh2/include/sh/sh7_sci.h b/bsps/sh/gensh2/include/sh/sh7_sci.h
new file mode 100644
index 0000000000..7218313704
--- /dev/null
+++ b/bsps/sh/gensh2/include/sh/sh7_sci.h
@@ -0,0 +1,88 @@
+/*
+ * Bit values for the serial control registers of the Hitachi SH704X
+ *
+ * From Hitachi tutorials
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _sh7_sci_h
+#define _sh7_sci_h
+
+#include <rtems/score/iosh7045.h>
+
+/*
+ * Serial mode register bits
+ */
+
+#define SCI_SYNC_MODE               0x80
+#define SCI_SEVEN_BIT_DATA          0x40
+#define SCI_PARITY_ON               0x20
+#define SCI_ODD_PARITY              0x10
+#define SCI_STOP_BITS_2             0x08
+#define SCI_ENABLE_MULTIP           0x04
+#define SCI_PHI_64                  0x03
+#define SCI_PHI_16                  0x02
+#define SCI_PHI_4                   0x01
+#define SCI_PHI_0                   0x00
+
+/*
+ * Serial register offsets, relative to SCI0_SMR or SCI1_SMR
+ */
+
+#define SCI_SMR			0x00
+#define SCI_BRR			0x01
+#define SCI_SCR			0x02
+#define SCI_TDR			0x03
+#define SCI_SSR			0x04
+#define SCI_RDR			0x05
+
+/*
+ * Serial control register bits
+ */
+#define SCI_TIE                 0x80    /* Transmit interrupt enable */
+#define SCI_RIE                 0x40    /* Receive interrupt enable */
+#define SCI_TE                  0x20    /* Transmit enable */
+#define SCI_RE                  0x10    /* Receive enable */
+#define SCI_MPIE                0x08    /* Multiprocessor interrupt enable */
+#define SCI_TEIE                0x04    /* Transmit end interrupt enable */
+#define SCI_CKE1                0x02    /* Clock enable 1 */
+#define SCI_CKE0                0x01    /* Clock enable 0 */
+
+/*
+ * Serial status register bits
+ */
+#define SCI_TDRE                0x80    /* Transmit data register empty */
+#define SCI_RDRF                0x40    /* Receive data register full */
+#define SCI_ORER                0x20    /* Overrun error */
+#define SCI_FER                 0x10    /* Framing error */
+#define SCI_PER                 0x08    /* Parity error */
+#define SCI_TEND                0x04    /* Transmit end */
+#define SCI_MPB                 0x02    /* Multiprocessor bit */
+#define SCI_MPBT                0x01    /* Multiprocessor bit transfer */
+
+/*
+ * INTC Priority Settings
+ */
+
+#define SCI0_IPMSK	0x00F0
+#define SCI0_LOWIP	0x0010
+#define SCI1_IPMSK	0x000F
+#define SCI1_LOWIP	0x0001
+
+#endif /* _sh7_sci_h */