diff options
| author | Padmarao Begari <padmarao.begari@microchip.com> | 2022-09-19 18:30:26 +0530 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2022-09-20 12:00:51 -0500 |
| commit | 6b0d3c987349d188b65e9fc8229daeba247928c5 (patch) | |
| tree | 4f6f37aaab9be619b82612eb4f000a42549488ca /bsps/riscv/riscv/start/bspsmp.c | |
| parent | spec/build/bsps: Add dtb support (diff) | |
| download | rtems-6b0d3c987349d188b65e9fc8229daeba247928c5.tar.bz2 | |
bsps/riscv: Add Microchip PolarFire SoC BSP variant
The Microchip PolarFire SoC support is implemented as a
riscv BSP variant to boot with any individual hart(cpu core)
or SMP based on the boot HARTID configurable and support
components are 4 CPU Cores (U54), Interrupt controller (PLIC),
Timer (CLINT), UART.
Diffstat (limited to 'bsps/riscv/riscv/start/bspsmp.c')
| -rw-r--r-- | bsps/riscv/riscv/start/bspsmp.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/bsps/riscv/riscv/start/bspsmp.c b/bsps/riscv/riscv/start/bspsmp.c index 4f1b3c93cc..91f4f7b96a 100644 --- a/bsps/riscv/riscv/start/bspsmp.c +++ b/bsps/riscv/riscv/start/bspsmp.c @@ -49,7 +49,7 @@ void bsp_start_on_secondary_processor(Per_CPU_Control *cpu_self) uint32_t _CPU_SMP_Initialize(void) { - return riscv_hart_count; + return riscv_hart_count - RISCV_BOOT_HARTID; } bool _CPU_SMP_Start_processor(uint32_t cpu_index) |