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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-11-09 08:19:12 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-11-10 08:55:38 +0100 |
| commit | e19d490fbe8d4f6f0cc3a5e7f97b7623d02684b5 (patch) | |
| tree | 9415619c3b9baa8372248c95a81d760aa15c7f18 /bsps/riscv/riscv/irq/irq.c | |
| parent | bsps/riscv: bsp_interrupt_vector_is_enabled() (diff) | |
| download | rtems-e19d490fbe8d4f6f0cc3a5e7f97b7623d02684b5.tar.bz2 | |
bsps/riscv: Improve bsp_interrupt_vector_enable()
Add support for hart-specific software and timer interrupts.
Diffstat (limited to '')
| -rw-r--r-- | bsps/riscv/riscv/irq/irq.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c index 8de9e47cbc..3bce33ae13 100644 --- a/bsps/riscv/riscv/irq/irq.c +++ b/bsps/riscv/riscv/irq/irq.c @@ -437,8 +437,16 @@ rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector) } rtems_interrupt_lock_release(&riscv_plic_lock, &lock_context); + return RTEMS_SUCCESSFUL; + } + + if (vector == RISCV_INTERRUPT_VECTOR_TIMER) { + set_csr(mie, MIP_MTIP); + return RTEMS_SUCCESSFUL; } + _Assert(vector == RISCV_INTERRUPT_VECTOR_SOFTWARE); + set_csr(mie, MIP_MSIP); return RTEMS_SUCCESSFUL; } |