bsp/riscv: Fix inter-processor interrupts

The previous version worked only on a patched Qemu.  Writes to mip are
illegal according to the The RISC-V Instruction Set Manual, Volume II:
Privileged Architecture, Privileged Architecture Version 1.10.

Update #3433.

1 files changed, 7 insertions, 1 deletions

diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c
index 64cb68b474..0142efbe9b 100644
--- a/bsps/riscv/riscv/irq/irq.c
+++ b/bsps/riscv/riscv/irq/irq.c
@@ -90,7 +90,13 @@ void _RISCV_Interrupt_dispatch(uintptr_t mcause, Per_CPU_Control *cpu_self)
     }
   } else if (mcause == (RISCV_INTERRUPT_SOFTWARE_MACHINE << 1)) {
 #ifdef RTEMS_SMP
-    clear_csr(mip, MIP_MSIP);
+    /*
+     * Clear the software interrupt on this processor.  Synchronization of
+     * inter-processor interrupts is done via Per_CPU_Control::message in
+     * _SMP_Inter_processor_interrupt_handler().
+     */
+    *cpu_self->cpu_per_cpu.clint_msip = 0;
+
     _SMP_Inter_processor_interrupt_handler(cpu_self);
 #else
     bsp_interrupt_handler_dispatch(RISCV_INTERRUPT_VECTOR_SOFTWARE);