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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-08-01 10:06:37 +0200 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-08-02 09:28:23 +0200 |
commit | 3d11c1e2afee49470deec48c0cdd773ed0ac5191 (patch) | |
tree | f0c7770aa8dbea2d3ef0526abb4b878bc15999ff /bsps/riscv/riscv/irq/irq.c | |
parent | bsp/riscv: Remove unused variable (diff) | |
download | rtems-3d11c1e2afee49470deec48c0cdd773ed0ac5191.tar.bz2 |
bsp/riscv: Fix a synchronization issue for PLIC
Update #3433.
Diffstat (limited to 'bsps/riscv/riscv/irq/irq.c')
-rw-r--r-- | bsps/riscv/riscv/irq/irq.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c index a369a81e62..ea33a3239c 100644 --- a/bsps/riscv/riscv/irq/irq.c +++ b/bsps/riscv/riscv/irq/irq.c @@ -84,7 +84,15 @@ void _RISCV_Interrupt_dispatch(uintptr_t mcause, Per_CPU_Control *cpu_self) bsp_interrupt_handler_dispatch( RISCV_INTERRUPT_VECTOR_EXTERNAL(interrupt_index) ); + plic_hart_regs->claim_complete = interrupt_index; + + /* + * FIXME: It is not clear which fence is necessary here or if a fence is + * necessary at all. The goal is that the complete signal is somehow + * recognized by the PLIC before the next claim is issued. + */ + __asm__ volatile ("fence o, i" : : : "memory"); } } else if (mcause == (RISCV_INTERRUPT_SOFTWARE_MACHINE << 1)) { #ifdef RTEMS_SMP |