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| author | Padmarao Begari <padmarao.begari@microchip.com> | 2022-09-19 18:30:26 +0530 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2022-09-20 12:00:51 -0500 |
| commit | 6b0d3c987349d188b65e9fc8229daeba247928c5 (patch) | |
| tree | 4f6f37aaab9be619b82612eb4f000a42549488ca /bsps/riscv/riscv/include/bsp/riscv.h | |
| parent | spec/build/bsps: Add dtb support (diff) | |
| download | rtems-6b0d3c987349d188b65e9fc8229daeba247928c5.tar.bz2 | |
bsps/riscv: Add Microchip PolarFire SoC BSP variant
The Microchip PolarFire SoC support is implemented as a
riscv BSP variant to boot with any individual hart(cpu core)
or SMP based on the boot HARTID configurable and support
components are 4 CPU Cores (U54), Interrupt controller (PLIC),
Timer (CLINT), UART.
Diffstat (limited to 'bsps/riscv/riscv/include/bsp/riscv.h')
| -rw-r--r-- | bsps/riscv/riscv/include/bsp/riscv.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/bsps/riscv/riscv/include/bsp/riscv.h b/bsps/riscv/riscv/include/bsp/riscv.h index a469155865..2ef2f8d83d 100644 --- a/bsps/riscv/riscv/include/bsp/riscv.h +++ b/bsps/riscv/riscv/include/bsp/riscv.h @@ -34,17 +34,31 @@ extern "C" { #endif +static inline uint32_t _RISCV_Map_hardid_to_cpu_index(uint32_t hardid) +{ + return (hardid - RISCV_BOOT_HARTID); +} + +static inline uint32_t _RISCV_Map_cpu_index_to_hardid(uint32_t cpu_index) +{ + return (cpu_index + RISCV_BOOT_HARTID); +} + extern volatile RISCV_CLINT_regs *riscv_clint; void *riscv_fdt_get_address(const void *fdt, int node); uint32_t riscv_get_core_frequency(void); +#if RISCV_ENABLE_MPFS_SUPPORT != 0 +extern uint32_t riscv_hart_count; +#else #ifdef RTEMS_SMP extern uint32_t riscv_hart_count; #else #define riscv_hart_count 1 #endif +#endif uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle); |