diff options
| author | Pragnesh Patel <pragnesh.patel@sifive.com> | 2019-10-22 10:20:05 +0000 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2019-10-23 08:11:50 +0200 |
| commit | a7f5e42cc5234f239a01b8f69847ebb018710948 (patch) | |
| tree | 75d1abe5128bc54b678580c7d2d03b6823568e70 /bsps/riscv/riscv/config/frdme310arty.cfg | |
| parent | libdebugger/arm: Clean up the building on arm variants. (diff) | |
| download | rtems-a7f5e42cc5234f239a01b8f69847ebb018710948.tar.bz2 | |
riscv: add freedom E310 Arty A7 bsp
Added support for Sifive Freedom FE310 soc on Arty A7 FPGA board.
Update #3785.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Diffstat (limited to 'bsps/riscv/riscv/config/frdme310arty.cfg')
| -rw-r--r-- | bsps/riscv/riscv/config/frdme310arty.cfg | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/bsps/riscv/riscv/config/frdme310arty.cfg b/bsps/riscv/riscv/config/frdme310arty.cfg new file mode 100644 index 0000000000..e19e431b53 --- /dev/null +++ b/bsps/riscv/riscv/config/frdme310arty.cfg @@ -0,0 +1,9 @@ +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = riscv + +CPU_CFLAGS = -march=rv32imac -mabi=ilp32 + +LDFLAGS = -Wl,--gc-sections + +CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections |