bsps: Move startup files to bsps

Adjust build support files to new directory layout.

This patch is a part of the BSP source reorganization.

Update #3285.

13 files changed, 1136 insertions, 0 deletions

diff --git a/bsps/powerpc/gen5200/start/bestcomm.c b/bsps/powerpc/gen5200/start/bestcomm.c
new file mode 100644
index 0000000000..ef59adcfd8
--- /dev/null
+++ b/bsps/powerpc/gen5200/start/bestcomm.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2010-2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#define NDEBUG
+
+#include <bsp/bestcomm.h>
+
+#include <string.h>
+
+#include <bsp/mpc5200.h>
+
+static void bestcomm_irq_handler(void *arg)
+{
+  bestcomm_irq *self = arg;
+
+  bestcomm_irq_clear(self);
+  bestcomm_irq_wakeup_event_task(self);
+}
+
+void bestcomm_irq_create(bestcomm_irq *self, int task_index)
+{
+  assert(task_index >= 0 && task_index <= 15);
+
+  self->task_index = task_index;
+  self->event_task_id = rtems_task_self();
+  bestcomm_glue_irq_install(task_index, bestcomm_irq_handler, self);
+}
+
+void bestcomm_irq_destroy(const bestcomm_irq *self)
+{
+  bestcomm_glue_irq_install(self->task_index, NULL, NULL);
+}
+
+void bestcomm_task_create(bestcomm_task *self, TaskId task_index)
+{
+  self->task_control_register = &mpc5200.sdma.tcr[task_index];
+  self->variable_table = BESTCOMM_TASK_ENTRY_TABLE[task_index].var_table;
+  self->task_index = task_index;
+  self->tdt_begin = NULL;
+  self->tdt_opcode_count = 0;
+  bestcomm_task_stop(self);
+  bestcomm_irq_create(&self->irq, task_index);
+}
+
+void bestcomm_task_create_and_load(
+  bestcomm_task *self,
+  TaskId task_index,
+  const uint32_t *tdt_source_begin,
+  size_t tdt_size
+)
+{
+  bestcomm_task_create(self, task_index);
+  bestcomm_task_load(self, tdt_source_begin, tdt_size);
+}
+
+void bestcomm_task_destroy(bestcomm_task *self)
+{
+  bestcomm_task_stop(self);
+  bestcomm_task_free_tdt(self);
+}
+
+void bestcomm_task_load(bestcomm_task *self, const uint32_t *tdt_source_begin, size_t tdt_size)
+{
+  assert(tdt_size % 4 == 0);
+
+  bestcomm_task_irq_disable(self);
+  bestcomm_task_stop(self);
+  bestcomm_task_irq_clear(self);
+  bestcomm_task_irq_enable(self);
+  bestcomm_task_free_tdt(self);
+  bestcomm_task_clear_variables(self);
+
+  self->tdt_opcode_count = tdt_size / 4;
+
+  self->tdt_begin = bestcomm_malloc(tdt_size);
+  assert(self->tdt_begin != NULL);
+  uint32_t *tdt_last = self->tdt_begin + self->tdt_opcode_count - 1;
+
+  memcpy(self->tdt_begin, tdt_source_begin, tdt_size);
+
+  volatile bestcomm_task_entry *entry = bestcomm_task_get_task_entry(self);
+  entry->tdt_begin = self->tdt_begin;
+  entry->tdt_last = tdt_last;
+
+  bestcomm_task_clear_pragmas(self);
+  bestcomm_task_set_priority(self, 0);
+}
+
+void bestcomm_task_clear_variables(const bestcomm_task *self)
+{
+  int i;
+
+  for (i = 0; i < 32; ++i) {
+    (*self->variable_table)[i] = 0;
+  }
+}
diff --git a/bsps/powerpc/gen5200/start/bsp_specs b/bsps/powerpc/gen5200/start/bsp_specs
new file mode 100644
index 0000000000..2625609327
--- /dev/null
+++ b/bsps/powerpc/gen5200/start/bsp_specs
@@ -0,0 +1,9 @@
+%rename endfile old_endfile
+%rename startfile old_startfile
+
+*startfile:
+%{!qrtems: %(old_startfile)} \
+%{!nostdlib: %{qrtems: ecrti%O%s rtems_crti%O%s crtbegin.o%s}}
+
+*endfile:
+%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s ecrtn.o%s}
diff --git a/bsps/powerpc/gen5200/start/bspreset.c b/bsps/powerpc/gen5200/start/bspreset.c
new file mode 100644
index 0000000000..232ebfeac0
--- /dev/null
+++ b/bsps/powerpc/gen5200/start/bspreset.c
@@ -0,0 +1,30 @@
+/*
+ *  COPYRIGHT (c) 1989-2008.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <bsp.h>
+#include <bsp/mpc5200.h>
+#include <bsp/bootcard.h>
+
+void bsp_reset( void )
+{
+  #if (BENCHMARK_IRQ_PROCESSING == 1)
+  {
+    BSP_IRQ_Benchmarking_Report();
+  }
+  #endif
+
+  /*
+   * Now reset the CPU
+   */
+  mpc5200.gpt[0].count_in = 0xf;
+  mpc5200.gpt[0].emsel = 0x9004;
+
+  while(1) ;
+}
diff --git a/bsps/powerpc/gen5200/start/bspstart.c b/bsps/powerpc/gen5200/start/bspstart.c
new file mode 100644
index 0000000000..209cc7738e
--- /dev/null
+++ b/bsps/powerpc/gen5200/start/bspstart.c
@@ -0,0 +1,172 @@
+/*===============================================================*\
+| Project: RTEMS generic MPC5200 BSP                              |
++-----------------------------------------------------------------+
+| Partially based on the code references which are named below.   |
+| Adaptions, modifications, enhancements and any recent parts of  |
+| the code are:                                                   |
+|                    Copyright (c) 2005                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.org/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+| this file contains the BSP initialization code                  |
+\*===============================================================*/
+/***********************************************************************/
+/*                                                                     */
+/*   Module:       bspstart.c                                          */
+/*   Date:         07/17/2003                                          */
+/*   Purpose:      RTEMS MPC5x00 C level startup code                  */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   Description:  This routine starts the application. It includes    */
+/*                 application, board, and monitor specific            */
+/*                 initialization and configuration. The generic CPU   */
+/*                 dependent initialization has been performed before  */
+/*                 this routine is invoked.                            */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   Code                                                              */
+/*   References:   MPC8260ads C level startup code                     */
+/*   Module:       bspstart.c                                          */
+/*   Project:      RTEMS 4.6.0pre1 / MCF8260ads BSP                    */
+/*   Version       1.2                                                 */
+/*   Date:         04/17/2002                                          */
+/*                                                                     */
+/*   Author(s) / Copyright(s):                                         */
+/*                                                                     */
+/*   The MPC860 specific stuff was written by Jay Monkman              */
+/*   (jmonkman@frasca.com)                                             */
+/*                                                                     */
+/*   Modified for the MPC8260ADS board by Andy Dachs                   */
+/*   <a.dachs@sstl.co.uk>                                              */
+/*   Surrey Satellite Technology Limited, 2001                         */
+/*   A 40MHz system clock is assumed.                                  */
+/*   The PON. RST.CONF. Dip switches (DS1) are                         */
+/*   1 - Off                                                           */
+/*   2 - On                                                            */
+/*   3 - Off                                                           */
+/*   4 - On                                                            */
+/*   5 - Off                                                           */
+/*   6 - Off                                                           */
+/*   7 - Off                                                           */
+/*   8 - Off                                                           */
+/*   Dip switches on DS2 and DS3 are all set to ON                     */
+/*   The LEDs on the board are used to signal panic and fatal_error    */
+/*   conditions.                                                       */
+/*   The mmu is unused at this time.                                   */
+/*                                                                     */
+/*   COPYRIGHT (c) 1989-2007.                                          */
+/*   On-Line Applications Research Corporation (OAR).                  */
+/*                                                                     */
+/*   The license and distribution terms for this file may be           */
+/*   found in the file LICENSE in this distribution or at     */
+/*   http://www.rtems.org/license/LICENSE.                             */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   Partially based on the code references which are named above.     */
+/*   Adaptions, modifications, enhancements and any recent parts of    */
+/*   the code are under the right of                                   */
+/*                                                                     */
+/*         IPR Engineering, Dachauer Straße 38, D-80335 München        */
+/*                        Copyright(C) 2003                            */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   IPR Engineering makes no representation or warranties with        */
+/*   respect to the performance of this computer program, and          */
+/*   specifically disclaims any responsibility for any damages,        */
+/*   special or consequential, connected with the use of this program. */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   Version history:  1.0                                             */
+/*                                                                     */
+/***********************************************************************/
+
+#include <rtems.h>
+#include <rtems/counter.h>
+
+#include <libcpu/powerpc-utility.h>
+
+#include <bsp.h>
+#include <bsp/vectors.h>
+#include <bsp/bootcard.h>
+#include <bsp/irq.h>
+#include <bsp/irq-generic.h>
+#include <bsp/mpc5200.h>
+
+/* Configuration parameter for clock driver */
+uint32_t bsp_time_base_frequency;
+
+/* Legacy */
+uint32_t bsp_clicks_per_usec;
+
+void bsp_start(void)
+{
+  /*
+   * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
+   * function store the result in global variables so that it can be used
+   * later...
+   */
+  get_ppc_cpu_type();
+  get_ppc_cpu_revision();
+
+  #if defined(HAS_UBOOT) && defined(SHOW_MORE_INIT_SETTINGS)
+    {
+      void dumpUBootBDInfo( bd_t * );
+      dumpUBootBDInfo( &bsp_uboot_board_info );
+    }
+  #endif
+
+  cpu_init();
+
+  if(get_ppc_cpu_revision() >= 0x2014) {
+    /* Special settings for MPC5200B (B variant) */
+    uint32_t xlb_cfg = mpc5200.config;
+
+    /* XXX: The Freescale documentation for BSDIS seems to be wrong */
+    xlb_cfg |= XLB_CFG_BSDIS;
+
+    xlb_cfg &= ~XLB_CFG_PLDIS;
+
+    mpc5200.config = xlb_cfg;
+  }
+
+  bsp_time_base_frequency = XLB_CLOCK / 4;
+  bsp_clicks_per_usec    = (XLB_CLOCK/4000000);
+  rtems_counter_initialize_converter(bsp_time_base_frequency);
+
+  /* Initialize exception handler */
+  ppc_exc_cache_wb_check = 0;
+  ppc_exc_initialize(
+    (uintptr_t) bsp_interrupt_stack_start,
+    (uintptr_t) bsp_interrupt_stack_size
+  );
+  ppc_exc_set_handler(ASM_ALIGN_VECTOR, ppc_exc_alignment_handler);
+
+  /* Initalize interrupt support */
+  bsp_interrupt_initialize();
+
+  /*
+   *  If the BSP was built with IRQ benchmarking enabled,
+   *  then intialize it.
+   */
+  #if (BENCHMARK_IRQ_PROCESSING == 1)
+    BSP_IRQ_Benchmarking_Reset();
+  #endif
+
+  #ifdef SHOW_MORE_INIT_SETTINGS
+    printk("Exit from bspstart\n");
+  #endif
+}
diff --git a/bsps/powerpc/gen5200/start/cpuinit.c b/bsps/powerpc/gen5200/start/cpuinit.c
new file mode 100644
index 0000000000..77787c4956
--- /dev/null
+++ b/bsps/powerpc/gen5200/start/cpuinit.c
@@ -0,0 +1,348 @@
+/*===============================================================*\
+| Project: RTEMS generic MPC5200 BSP                              |
++-----------------------------------------------------------------+
+| Partially based on the code references which are named below.   |
+| Adaptions, modifications, enhancements and any recent parts of  |
+| the code are:                                                   |
+|                    Copyright (c) 2005                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.org/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+| this file contains the code to initialize the cpu               |
+\*===============================================================*/
+/***********************************************************************/
+/*                                                                     */
+/*   Module:       cpuinit.c                                           */
+/*   Date:         07/17/2003                                          */
+/*   Purpose:      RTEMS MPC5x00 C level startup code                  */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   Description:  This file contains additional functions for         */
+/*                 initializing the MPC5x00 CPU                        */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   Code                                                              */
+/*   References:   MPC8260ads additional CPU initialization            */
+/*   Module:       cpuinit.c                                           */
+/*   Project:      RTEMS 4.6.0pre1 / MCF8260ads BSP                    */
+/*   Version       1.1                                                 */
+/*   Date:         10/22/2002                                          */
+/*                                                                     */
+/*   Author(s) / Copyright(s):                                         */
+/*                                                                     */
+/*   Written by Jay Monkman (jmonkman@frasca.com)                      */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   Partially based on the code references which are named above.     */
+/*   Adaptions, modifications, enhancements and any recent parts of    */
+/*   the code are under the right of                                   */
+/*                                                                     */
+/*         IPR Engineering, Dachauer Straße 38, D-80335 München        */
+/*                        Copyright(C) 2003                            */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   IPR Engineering makes no representation or warranties with        */
+/*   respect to the performance of this computer program, and          */
+/*   specifically disclaims any responsibility for any damages,        */
+/*   special or consequential, connected with the use of this program. */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   Version history:  1.0                                             */
+/*                                                                     */
+/***********************************************************************/
+
+#include <stdbool.h>
+#include <string.h>
+
+#include <libcpu/powerpc-utility.h>
+#include <libcpu/mmu.h>
+
+#include <bsp.h>
+#include <bsp/mpc5200.h>
+
+#define SET_DBAT( n, uv, lv) \
+  do { \
+    PPC_SET_SPECIAL_PURPOSE_REGISTER( DBAT##n##L, lv); \
+    PPC_SET_SPECIAL_PURPOSE_REGISTER( DBAT##n##U, uv); \
+  } while (0)
+
+static void calc_dbat_regvals(
+  BAT *bat_ptr,
+  uint32_t base_addr,
+  uint32_t size,
+  bool flg_w,
+  bool flg_i,
+  bool flg_m,
+  bool flg_g,
+  uint32_t flg_bpp
+)
+{
+  uint32_t block_mask = 0xffffffff;
+  uint32_t end_addr = base_addr + size - 1;
+
+  /* Determine block mask, that overlaps the whole block */
+  while ((end_addr & block_mask) != (base_addr & block_mask)) {
+    block_mask <<= 1;
+  }
+
+  bat_ptr->batu.bepi = base_addr >> (32 - 15);
+  bat_ptr->batu.bl   = ~(block_mask >> (28 - 11));
+  bat_ptr->batu.vs   = 1;
+  bat_ptr->batu.vp   = 1;
+
+  bat_ptr->batl.brpn = base_addr  >> (32 - 15);
+  bat_ptr->batl.w    = flg_w;
+  bat_ptr->batl.i    = flg_i;
+  bat_ptr->batl.m    = flg_m;
+  bat_ptr->batl.g    = flg_g;
+  bat_ptr->batl.pp   = flg_bpp;
+}
+
+static inline void enable_bat_4_to_7(void)
+{
+  PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS(HID2, BSP_BBIT32(13));
+}
+
+static void cpu_init_bsp(void)
+{
+  BAT dbat;
+
+#if defined(MPC5200_BOARD_BRS5L) || defined(MPC5200_BOARD_BRS6L)
+  calc_dbat_regvals(
+    &dbat,
+    (uint32_t) bsp_ram_start,
+    (uint32_t) bsp_ram_size,
+    false,
+    false,
+    false,
+    false,
+    BPP_RW
+  );
+  SET_DBAT(0,dbat.batu,dbat.batl);
+
+  calc_dbat_regvals(
+    &dbat,
+    (uint32_t) bsp_rom_start,
+    (uint32_t) bsp_rom_size,
+    false,
+    false,
+    false,
+    false,
+    BPP_RX
+  );
+  SET_DBAT(1,dbat.batu,dbat.batl);
+
+  calc_dbat_regvals(
+    &dbat,
+    (uint32_t) MBAR,
+    128 * 1024,
+    false,
+    true,
+    false,
+    true,
+    BPP_RW
+  );
+  SET_DBAT(2,dbat.batu,dbat.batl);
+#elif defined (HAS_UBOOT)
+  uint32_t start = 0;
+
+  /*
+   * Accesses (also speculative accesses) outside of the RAM area are a
+   * disaster especially in combination with the BestComm.  For safety reasons
+   * we make the available RAM a little bit smaller to have an unused area at
+   * the end.
+   */
+  bsp_uboot_board_info.bi_memsize -= 4 * 1024;
+
+  /*
+   * Program BAT0 for RAM
+   */
+  calc_dbat_regvals(
+    &dbat,
+    bsp_uboot_board_info.bi_memstart,
+    bsp_uboot_board_info.bi_memsize,
+    false,
+    false,
+    false,
+    false,
+    BPP_RW
+  );
+  SET_DBAT(0,dbat.batu,dbat.batl);
+
+  /*
+   * Program BAT1 for Flash
+   *
+   * WARNING!! Some Freescale LITE5200B boards ship with a version of
+   * U-Boot that lies about the starting address of Flash.  This check
+   * corrects that.
+   */
+  if ((bsp_uboot_board_info.bi_flashstart + bsp_uboot_board_info.bi_flashsize)
+    < bsp_uboot_board_info.bi_flashstart) {
+    start = 0 - bsp_uboot_board_info.bi_flashsize;
+  } else {
+    start = bsp_uboot_board_info.bi_flashstart;
+  }
+  calc_dbat_regvals(
+    &dbat,
+    start,
+    bsp_uboot_board_info.bi_flashsize,
+    false,
+    false,
+    false,
+    false,
+    BPP_RX
+  );
+  SET_DBAT(1,dbat.batu,dbat.batl);
+
+  /*
+   * Program BAT2 for the MBAR
+   */
+  calc_dbat_regvals(
+    &dbat,
+    (uint32_t) MBAR,
+    128 * 1024,
+    false,
+    true,
+    false,
+    true,
+    BPP_RW
+  );
+  SET_DBAT(2,dbat.batu,dbat.batl);
+
+  /*
+   * If there is SRAM, program BAT3 for that memory
+   */
+  if (bsp_uboot_board_info.bi_sramsize != 0) {
+    calc_dbat_regvals(
+      &dbat,
+      bsp_uboot_board_info.bi_sramstart,
+      bsp_uboot_board_info.bi_sramsize,
+      false,
+      true,
+      true,
+      true,
+      BPP_RW
+    );
+    SET_DBAT(3,dbat.batu,dbat.batl);
+  }
+#else
+#warning "Using BAT register values set by environment"
+#endif
+
+#if defined(MPC5200_BOARD_DP2)
+  enable_bat_4_to_7();
+
+  /* FPGA */
+  calc_dbat_regvals(
+    &dbat,
+    0xf0020000,
+    128 * 1024,
+    false,
+    true,
+    false,
+    true,
+    BPP_RW
+  );
+  SET_DBAT(4, dbat.batu, dbat.batl);
+#elif defined(MPC5200_BOARD_PM520_ZE30)
+  enable_bat_4_to_7();
+
+  /* External CC770 CAN controller available in version 2 */
+  calc_dbat_regvals(
+    &dbat,
+    0xf2000000,
+    128 * 1024,
+    false,
+    true,
+    false,
+    true,
+    BPP_RW
+  );
+  SET_DBAT(4, dbat.batu, dbat.batl);
+#elif defined(MPC5200_BOARD_BRS5L)
+  calc_dbat_regvals(
+    &dbat,
+    (uint32_t) bsp_dpram_start,
+    128 * 1024,
+    false,
+    true,
+    false,
+    true,
+    BPP_RW
+  );
+  SET_DBAT(3,dbat.batu,dbat.batl);
+#elif defined(MPC5200_BOARD_BRS6L)
+  enable_bat_4_to_7();
+
+  /* FPGA */
+  calc_dbat_regvals(
+    &dbat,
+    MPC5200_BRS6L_FPGA_BEGIN,
+    MPC5200_BRS6L_FPGA_SIZE,
+    false,
+    true,
+    false,
+    true,
+    BPP_RW
+  );
+  SET_DBAT(3,dbat.batu,dbat.batl);
+
+  /* MRAM */
+  calc_dbat_regvals(
+    &dbat,
+    MPC5200_BRS6L_MRAM_BEGIN,
+    MPC5200_BRS6L_MRAM_SIZE,
+    true,
+    false,
+    false,
+    false,
+    BPP_RW
+  );
+  SET_DBAT(4,dbat.batu,dbat.batl);
+#endif
+}
+
+void cpu_init(void)
+{
+  uint32_t msr;
+
+  #if BSP_INSTRUCTION_CACHE_ENABLED
+    rtems_cache_enable_instruction();
+  #endif
+
+  /* Set up DBAT registers in MMU */
+  cpu_init_bsp();
+
+  #if defined(SHOW_MORE_INIT_SETTINGS)
+    { extern void ShowBATS(void);
+      ShowBATS();
+    }
+  #endif
+
+  /* Read MSR */
+  msr = ppc_machine_state_register();
+
+  /* Enable data MMU in MSR */
+  msr |= MSR_DR;
+
+  /* Update MSR */
+  ppc_set_machine_state_register( msr);
+
+  #if BSP_DATA_CACHE_ENABLED
+    rtems_cache_enable_data();
+  #endif
+}
diff --git a/bsps/powerpc/gen5200/start/linkcmds.brs5l b/bsps/powerpc/gen5200/start/linkcmds.brs5l
new file mode 100644
index 0000000000..58407e5f56
--- /dev/null
+++ b/bsps/powerpc/gen5200/start/linkcmds.brs5l
@@ -0,0 +1,15 @@
+/**
+ * @file
+ *
+ * Linker command file for the BRS5L board.
+ */
+
+MEMORY {
+	/* For the 4k adjustment see cpuinit.c */
+	RAM : ORIGIN = 0x0, LENGTH = 128M - 4k
+	ROM : ORIGIN = 0xffe00000, LENGTH = 2M
+	DPRAM : ORIGIN = 0xff000000, LENGTH = 1k
+	REGS : ORIGIN = 0xf0000000, LENGTH = 64k
+}
+
+INCLUDE linkcmds.gen5200_base
diff --git a/bsps/powerpc/gen5200/start/linkcmds.brs6l b/bsps/powerpc/gen5200/start/linkcmds.brs6l
new file mode 100644
index 0000000000..ae80a72ad5
--- /dev/null
+++ b/bsps/powerpc/gen5200/start/linkcmds.brs6l
@@ -0,0 +1,15 @@
+/**
+ * @file
+ *
+ * Linker command file for the BRS6L board.
+ */
+
+MEMORY {
+	/* For the 4k adjustment see cpuinit.c */
+	RAM : ORIGIN = 0x0, LENGTH = 128M - 4k
+	ROM : ORIGIN = 0xff800000, LENGTH = 8M
+	DPRAM : ORIGIN = 0xff000000, LENGTH = 0
+	REGS : ORIGIN = 0xf0000000, LENGTH = 64k
+}
+
+INCLUDE linkcmds.gen5200_base
diff --git a/bsps/powerpc/gen5200/start/linkcmds.dp2 b/bsps/powerpc/gen5200/start/linkcmds.dp2
new file mode 100644
index 0000000000..4ad76d6fce
--- /dev/null
+++ b/bsps/powerpc/gen5200/start/linkcmds.dp2
@@ -0,0 +1,15 @@
+/**
+ * @file
+ *
+ * Linker command file for the Direct Prototyping Data Processing board.
+ */
+
+MEMORY {
+	/* For the 4k adjustment see cpuinit.c */
+	RAM : ORIGIN = 0x0, LENGTH = 64M - 4k
+	ROM : ORIGIN = 0xffe00000, LENGTH = 2M
+	REGS : ORIGIN = 0xf0000000, LENGTH = 64k
+	DPRAM : ORIGIN = 0x0, LENGTH = 0
+}
+
+INCLUDE linkcmds.gen5200_base
diff --git a/bsps/powerpc/gen5200/start/linkcmds.gen5200_base b/bsps/powerpc/gen5200/start/linkcmds.gen5200_base
new file mode 100644
index 0000000000..1a92c7c9dd
--- /dev/null
+++ b/bsps/powerpc/gen5200/start/linkcmds.gen5200_base
@@ -0,0 +1,357 @@
+/**
+ * @file
+ *
+ * Derived from internal linker script of GNU ld (GNU Binutils) 2.18 for elf32ppc emulation.
+ */
+
+OUTPUT_FORMAT ("elf32-powerpc", "elf32-powerpc", "elf32-powerpc")
+OUTPUT_ARCH (powerpc)
+ENTRY (start)
+STARTUP (start.o)
+
+bsp_ram_start = ORIGIN (RAM);
+bsp_ram_end = ORIGIN (RAM) + LENGTH (RAM);
+bsp_ram_size = LENGTH (RAM);
+
+bsp_rom_start = ORIGIN (ROM);
+bsp_rom_end = ORIGIN (ROM) + LENGTH (ROM);
+bsp_rom_size = LENGTH (ROM);
+
+bsp_dpram_start = ORIGIN (DPRAM);
+bsp_dpram_end = ORIGIN (DPRAM) + LENGTH (DPRAM);
+bsp_dpram_size = LENGTH (DPRAM);
+
+bsp_section_align = 32;
+
+RamBase = bsp_ram_start;
+RamSize = bsp_ram_size;
+HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
+
+MEMORY {
+	UNEXPECTED_SECTIONS : ORIGIN = 0xffffffff, LENGTH = 0
+}
+
+SECTIONS {
+	/*
+	 * BSP: MPC5200 registers
+	 */
+	.regs (NOLOAD) : { 
+		MBAR = .;
+		mpc5200 = .;
+	} > REGS
+
+	/*
+	 * BSP: Exception vectors
+	 */
+	.vectors 0x100 : {
+		*(.vectors)
+	} > RAM
+
+	/* 
+	 * BSP: The initial stack will live in this area - between the vectors
+	 * and the text section.
+	 */
+
+	.text 0x10000 : {
+		/*
+		 * BSP: Start of text section
+		 */
+		bsp_section_text_start = .;
+
+		/*
+		 * BSP: System startup entry
+		 */
+		KEEP (*(.entry))
+
+		/*
+		 * BSP: Moved into .text from .init
+		 */
+		KEEP (*(.init))
+
+		*(.text .stub .text.* .gnu.linkonce.t.*)
+		KEEP (*(.text.*personality*))
+		/* .gnu.warning sections are handled specially by elf32.em.  */
+		*(.gnu.warning)
+		*(.glink)
+		
+		/*
+		 * BSP: Special FreeBSD sysctl sections
+		 */
+		. = ALIGN (16);
+		__start_set_sysctl_set = .;
+		*(set_sysctl_*);
+		__stop_set_sysctl_set = ABSOLUTE(.);
+		*(set_domain_*);
+		*(set_pseudo_*);
+
+		/*
+		 * BSP: Moved into .text from .*
+		 */
+		*(.rodata .rodata.* .gnu.linkonce.r.*)
+		KEEP (*(SORT(.rtemsroset.*)))
+		*(.rodata1)
+		*(.interp)
+		*(.note.gnu.build-id)
+		*(.hash)
+		*(.gnu.hash)
+		*(.dynsym)
+		*(.dynstr)
+		*(.gnu.version)
+		*(.gnu.version_d)
+		*(.gnu.version_r)
+		*(.eh_frame_hdr)
+
+		/*
+		 * BSP: Magic PPC stuff
+		 */
+		*(.PPC.*)
+
+		/*
+		 * BSP: Required by cpukit/score/src/threadhandler.c
+		 */
+		PROVIDE (_fini = .);
+
+		/*
+		 * BSP: Moved into .text from .fini
+		 */
+		KEEP (*(.fini))
+
+		. = ALIGN (bsp_section_align);
+
+		PROVIDE (__etext = .);
+		PROVIDE (_etext = .);
+		PROVIDE (etext = .);
+	} > RAM
+
+	.tdata : {
+		_TLS_Data_begin = .;
+		*(.tdata .tdata.* .gnu.linkonce.td.*)
+		_TLS_Data_end = .;
+	} > RAM
+	.tbss : {
+		_TLS_BSS_begin = .;
+		*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+		_TLS_BSS_end = .;
+	} > RAM
+	_TLS_Data_size = _TLS_Data_end - _TLS_Data_begin;
+	_TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin;
+	_TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin;
+	_TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin;
+	_TLS_Size = _TLS_BSS_end - _TLS_Data_begin;
+	_TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
+
+	.sdata2 : {
+		PROVIDE (_SDA2_BASE_ = 32768);
+
+		*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
+
+		. = ALIGN (bsp_section_align);
+	} > RAM
+
+	.sbss2 : {
+		*(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)
+
+		. = ALIGN (bsp_section_align);
+
+		/*
+		 * BSP: End of text section
+		 */
+		bsp_section_text_end = .;
+	} > RAM
+
+	.data : {
+		/*
+		 * BSP: Start of data section
+		 */
+		bsp_section_data_start = .;
+
+		/*
+		 * BSP: Moved into .data from .ctors
+		 */
+		/* gcc uses crtbegin.o to find the start of
+		   the constructors, so we make sure it is
+		   first.  Because this is a wildcard, it
+		   doesn't matter if the user does not
+		   actually link against crtbegin.o; the
+		   linker won't look for a file to match a
+		   wildcard.  The wildcard also means that it
+		   doesn't matter which directory crtbegin.o
+		   is in.  */
+		KEEP (*crtbegin.o(.ctors))
+		KEEP (*crtbegin?.o(.ctors))
+		/* We don't want to include the .ctor section from
+		   the crtend.o file until after the sorted ctors.
+		   The .ctor section from the crtend file contains the
+		   end of ctors marker and it must be last */
+		KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+		KEEP (*(SORT(.ctors.*)))
+		KEEP (*(.ctors))
+
+		/*
+		 * BSP: Moved into .data from .dtors
+		 */
+		KEEP (*crtbegin.o(.dtors))
+		KEEP (*crtbegin?.o(.dtors))
+		KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+		KEEP (*(SORT(.dtors.*)))
+		KEEP (*(.dtors))
+
+		/*
+		 * BSP: Moved into .data from .*
+		 */
+		*(.tdata .tdata.* .gnu.linkonce.td.*)
+		*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+		*(.data1)
+		KEEP (*(.eh_frame))
+		*(.gcc_except_table .gcc_except_table.*)
+		KEEP (*(.jcr))
+		*(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*)
+		*(.fixup)
+		*(.got1)
+		*(.got2)
+		*(.dynamic)
+		*(.got)
+		*(.plt)
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP (*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP (*(SORT(.init_array.*)))
+		KEEP (*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP (*(.fini_array))
+		KEEP (*(SORT(.fini_array.*)))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		*(.data .data.* .gnu.linkonce.d.*)
+		KEEP (*(SORT(.rtemsrwset.*)))
+		KEEP (*(.gnu.linkonce.d.*personality*))
+		SORT(CONSTRUCTORS)
+
+		. = ALIGN (bsp_section_align);
+	} > RAM
+
+	.sdata : {
+		PROVIDE (_SDA_BASE_ = 32768);
+		*(.sdata .sdata.* .gnu.linkonce.s.*)
+
+		. = ALIGN (bsp_section_align);
+
+		_edata = .;
+		PROVIDE (edata = .);
+
+		/*
+		 * BSP: End of data section
+		 */
+		bsp_section_data_end = .;
+	} > RAM
+
+	.sbss : {
+		/*
+		 * BSP: Start of bss section
+		 */
+		bsp_section_bss_start = .;
+
+		__bss_start = .;
+
+		PROVIDE (__sbss_start = .); PROVIDE (___sbss_start = .);
+		*(.scommon)
+		*(.dynsbss)
+		*(.sbss .sbss.* .gnu.linkonce.sb.*)
+		PROVIDE (__sbss_end = .); PROVIDE (___sbss_end = .);
+
+		. = ALIGN (bsp_section_align);
+	} > RAM
+
+	.bss : {
+		*(COMMON)
+		*(.dynbss)
+		*(.bss .bss.* .gnu.linkonce.b.*)
+
+		. = ALIGN (bsp_section_align);
+
+		__end = .;
+		_end = .;
+		PROVIDE (end = .);
+
+		/*
+		 * BSP: End of bss section
+		 */
+		bsp_section_bss_end = .;
+	} > RAM
+
+	/*
+	 * BSP: Section sizes
+	 */
+	bsp_section_text_size = bsp_section_text_end - bsp_section_text_start;
+	bsp_section_data_size = bsp_section_data_end - bsp_section_data_start;
+	bsp_section_bss_size = bsp_section_bss_end - bsp_section_bss_start;
+
+	/*
+	 * BSP: Interrupt stack
+	 */
+	bsp_interrupt_stack_start = bsp_section_bss_end;
+	bsp_interrupt_stack_end = bsp_interrupt_stack_start + 32k;
+	bsp_interrupt_stack_size = bsp_interrupt_stack_end - bsp_interrupt_stack_start;
+
+	/*
+	 * BSP: Work area start
+	 */
+	bsp_work_area_start = bsp_interrupt_stack_end;
+	WorkAreaBase = bsp_work_area_start;
+	
+	/* Stabs debugging sections.  */
+	.stab          0 : { *(.stab) }
+	.stabstr       0 : { *(.stabstr) }
+	.stab.excl     0 : { *(.stab.excl) }
+	.stab.exclstr  0 : { *(.stab.exclstr) }
+	.stab.index    0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment       0 : { *(.comment) }
+	/* DWARF debug sections.
+	   Symbols in the DWARF debugging sections are relative to the beginning
+	   of the section so we begin them at 0.  */
+	/* DWARF 1 */
+	.debug          0 : { *(.debug) }
+	.line           0 : { *(.line) }
+	/* GNU DWARF 1 extensions */
+	.debug_srcinfo  0 : { *(.debug_srcinfo) }
+	.debug_sfnames  0 : { *(.debug_sfnames) }
+	/* DWARF 1.1 and DWARF 2 */
+	.debug_aranges  0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	/* DWARF 2 */
+	.debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+	.debug_abbrev   0 : { *(.debug_abbrev) }
+	.debug_line     0 : { *(.debug_line) }
+	.debug_frame    0 : { *(.debug_frame) }
+	.debug_str      0 : { *(.debug_str) }
+	.debug_loc      0 : { *(.debug_loc) }
+	.debug_macinfo  0 : { *(.debug_macinfo) }
+	/* SGI/MIPS DWARF 2 extensions */
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames  0 : { *(.debug_varnames) }
+	/* DWARF 3 */
+	.debug_pubtypes 0 : { *(.debug_pubtypes) }
+	.debug_ranges   0 : { *(.debug_ranges) }
+	/* DWARF extension */
+	.debug_macro    0 : { *(.debug_macro) }
+	.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
+
+	/DISCARD/ : {
+		*(.note.GNU-stack) *(.gnu_debuglink)
+	}
+
+	/*
+	 * This is a RTEMS specific section to catch all unexpected input
+	 * sections.  In case you get an error like
+	 *   "section `.unexpected_sections' will not fit in region
+	 *   `UNEXPECTED_SECTIONS'"
+	 * you have to figure out the offending input section and add it to the
+	 * appropriate output section definition above.
+	 */
+	.unexpected_sections : { *(*) } > UNEXPECTED_SECTIONS
+}
diff --git a/bsps/powerpc/gen5200/start/linkcmds.icecube b/bsps/powerpc/gen5200/start/linkcmds.icecube
new file mode 100644
index 0000000000..c05d45a852
--- /dev/null
+++ b/bsps/powerpc/gen5200/start/linkcmds.icecube
@@ -0,0 +1,15 @@
+/**
+ * @file
+ *
+ * Linker command file for the IceCube board.
+ */
+
+MEMORY {
+	/* For the 4k adjustment see cpuinit.c */
+	RAM : ORIGIN = 0x0, LENGTH = 128M - 4k
+	ROM : ORIGIN = 0xffe00000, LENGTH = 2M
+	REGS : ORIGIN = 0xf0000000, LENGTH = 64k
+	DPRAM : ORIGIN = 0x0, LENGTH = 0
+}
+
+INCLUDE linkcmds.gen5200_base
diff --git a/bsps/powerpc/gen5200/start/linkcmds.pm520_cr825 b/bsps/powerpc/gen5200/start/linkcmds.pm520_cr825
new file mode 100644
index 0000000000..49d596b577
--- /dev/null
+++ b/bsps/powerpc/gen5200/start/linkcmds.pm520_cr825
@@ -0,0 +1,15 @@
+/**
+ * @file
+ *
+ * Linker command file for the MicroSys PM520 board.
+ */
+
+MEMORY {
+	/* For the 4k adjustment see cpuinit.c */
+	RAM : ORIGIN = 0x0, LENGTH = 64M - 4k
+	ROM : ORIGIN = 0xffe00000, LENGTH = 2M
+	REGS : ORIGIN = 0xf0000000, LENGTH = 64k
+	DPRAM : ORIGIN = 0xff000000, LENGTH = 1k
+}
+
+INCLUDE linkcmds.gen5200_base
diff --git a/bsps/powerpc/gen5200/start/linkcmds.pm520_ze30 b/bsps/powerpc/gen5200/start/linkcmds.pm520_ze30
new file mode 100644
index 0000000000..49d596b577
--- /dev/null
+++ b/bsps/powerpc/gen5200/start/linkcmds.pm520_ze30
@@ -0,0 +1,15 @@
+/**
+ * @file
+ *
+ * Linker command file for the MicroSys PM520 board.
+ */
+
+MEMORY {
+	/* For the 4k adjustment see cpuinit.c */
+	RAM : ORIGIN = 0x0, LENGTH = 64M - 4k
+	ROM : ORIGIN = 0xffe00000, LENGTH = 2M
+	REGS : ORIGIN = 0xf0000000, LENGTH = 64k
+	DPRAM : ORIGIN = 0xff000000, LENGTH = 1k
+}
+
+INCLUDE linkcmds.gen5200_base
diff --git a/bsps/powerpc/gen5200/start/uboot_support.c b/bsps/powerpc/gen5200/start/uboot_support.c
new file mode 100644
index 0000000000..f373f558e7
--- /dev/null
+++ b/bsps/powerpc/gen5200/start/uboot_support.c
@@ -0,0 +1,23 @@
+/*
+ *  This file contains variables which assist the shared
+ *  U-Boot code.
+ *
+ *  COPYRIGHT (c) 1989-2008.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <stdint.h>
+
+#include <bsp.h>
+
+#if defined(HAS_UBOOT)
+/* Base address of U-Boot environment variables */
+const uint8_t *uboot_environment      = (const uint8_t *)0xfff40000;
+
+/* Length of area reserved for U-Boot environment variables */
+const size_t  uboot_environment_size = 0x10000;
+#endif