diff options
author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-04-20 10:19:28 +0200 |
---|---|---|
committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-04-20 13:08:36 +0200 |
commit | fbcd7c8fa65eb695e96a62ea1c1ac7a024fa9dfc (patch) | |
tree | a17e285cf22cd49cd42e8b3ad562febc3987d566 /bsps/mips | |
parent | bsps: Move console drivers to bsps (diff) | |
download | rtems-fbcd7c8fa65eb695e96a62ea1c1ac7a024fa9dfc.tar.bz2 |
bsps: Move start files to bsps
This patch is a part of the BSP source reorganization.
Update #3285.
Diffstat (limited to 'bsps/mips')
-rw-r--r-- | bsps/mips/csb350/start/start.S | 122 | ||||
-rw-r--r-- | bsps/mips/hurricane/start/start.S | 339 | ||||
-rw-r--r-- | bsps/mips/jmr3904/start/start.S | 196 | ||||
-rw-r--r-- | bsps/mips/malta/start/start.S | 221 | ||||
-rw-r--r-- | bsps/mips/rbtx4925/start/start.S | 360 | ||||
-rw-r--r-- | bsps/mips/rbtx4938/start/start.S | 359 |
6 files changed, 1597 insertions, 0 deletions
diff --git a/bsps/mips/csb350/start/start.S b/bsps/mips/csb350/start/start.S new file mode 100644 index 0000000000..9aea3f4cae --- /dev/null +++ b/bsps/mips/csb350/start/start.S @@ -0,0 +1,122 @@ +/* + * start.S -- startup file for Cogent CSB350 Au1100 based board + * + * Copyright (c) 2005 by Cogent Computer Systems + * Written by Jay Monkman <jtm@lopingdog.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#include <rtems/asm.h> +#include <bsp/regs.h> + + .text + .align 2 + +/* Without the following nop, GDB thinks _start is a data variable. + * This is probably a bug in GDB in handling a symbol that is at the + * start of the .text section. + */ + nop + + .globl _start + .ent _start +_start: + .set noreorder + + /* Get the address of start into $5 in a position independent + * fashion. This lets us know whether we have been relocated or not. + */ + $LF1 = . + 8 + bal $LF1 + nop +_branch: + move $5, $31 /* $5 == where are we */ + li $6, 0x8800000c /* $6 == where we want to be */ + + li v0, SR_CU1|SR_PE|SR_FR|SR_KX|SR_SX|SR_UX + mtc0 v0, C0_SR + mtc0 zero, C0_CAUSE + +1: + li v0, SR_PE|SR_FR|SR_KX|SR_SX|SR_UX + mtc0 v0, C0_SR +2: +/* Fix high bits, if any, of the PC so that exception handling + doesn't get confused. */ + la v0, 3f + jr v0 + nop +3: + la gp, _gp /* set the global data pointer */ + .end _start + +/* + * zero out the bss section. + */ + .globl zerobss + .ent zerobss +zerobss: + la v0, _fbss + la v1, _end +3: + sw zero,0(v0) + bltu v0,v1,3b + addiu v0,v0,4 /* executed in delay slot */ + + la t0, _stack_init /* initialize stack so we */ + /* We must subtract 24 bytes for the 3 8 byte arguments to main, in + case main wants to write them back to the stack. The caller is + supposed to allocate stack space for parameters in registers in + the old MIPS ABIs. We must do this even though we aren't passing + arguments, because main might be declared to have them. + + Some ports need a larger alignment for the stack, so we subtract + 32, which satisifes the stack for the arguments and keeps the + stack pointer better aligned. */ + subu t0,t0,32 + move sp,t0 /* set stack pointer */ + .end zerobss + + .globl exit .text + .globl init + .ent init +init: + + move a0,zero /* set command line to 0 */ + jal boot_card /* call the program start function */ + nop + + /* fall through to the "exit" routine */ + jal _sys_exit /* call libc exit to run the G++ */ + /* destructors */ + move a0,v0 /* pass through the exit code */ + .end init + +/* + * _sys_exit -- Exit from the application. Normally we cause a user trap + * to return to the ROM monitor for another run. NOTE: This is + * the only other routine we provide in the crt0.o object, since + * it may be tied to the "_start" routine. It also allows + * executables that contain a complete world to be linked with + * just the crt0.o object. + */ + .globl _sys_exit + .ent _sys_exit +_sys_exit: +7: +#ifdef GCRT0 + jal _mcleanup + nop +#endif + /* break inst. can cope with 0xfffff, but GAS limits the range: */ + break 1023 + nop + b 7b /* but loop back just in-case */ + nop + .end _sys_exit + +/* EOF crt0.S */ diff --git a/bsps/mips/hurricane/start/start.S b/bsps/mips/hurricane/start/start.S new file mode 100644 index 0000000000..e3d97cd167 --- /dev/null +++ b/bsps/mips/hurricane/start/start.S @@ -0,0 +1,339 @@ +/* + +Based upon IDT provided code with the following release: + +This source code has been made available to you by IDT on an AS-IS +basis. Anyone receiving this source is licensed under IDT copyrights +to use it in any way he or she deems fit, including copying it, +modifying it, compiling it, and redistributing it either with or +without modifications. No license under IDT patents or patent +applications is to be implied by the copyright license. + +Any user of this software should understand that IDT cannot provide +technical support for this software and will not be responsible for +any consequences resulting from the use of this software. + +Any person who transfers this source code or any derivative work must +include the IDT copyright notice, this paragraph, and the preceeding +two paragraphs in the transferred software. + +COPYRIGHT IDT CORPORATION 1996 +LICENSED MATERIAL - PROGRAM PROPERTY OF IDT +*/ + +/************************************************************************* +** +** Copyright 1991-95 Integrated Device Technology, Inc. +** All Rights Reserved +** +**************************************************************************/ + + +#include <rtems/mips/iregdef.h> +#include <rtems/mips/idtcpu.h> +#include <rtems/asm.h> + +#include <bsp.h> + +#if 0 + .extern _fdata,4 /* this is defined by the linker */ + .extern _edata,4 /* this is defined by the linker */ + .extern _idata,4 /* this is defined by the linker */ +#endif + .extern _fbss,4 /* this is defined by the linker */ + .extern end,4 /* this is defined by the linker */ + + .lcomm sim_mem_cfg_struct,12 + + .text + +/* For the V3 Eval board, we can safely assume that we have + at least 16 megabytes of RAM */ +#define HARD_CODED_MEM_SIZE 0x1000000 + +#define TMP_STKSIZE 1024 + +/* +** P_STACKSIZE is the size of the Prom Stack. +** the prom stack grows downward +*/ +#define P_STACKSIZE 0x2000 /* sets stack size to 8k */ + +/************************************************************************** +** +** start - Typical standalone start up code required for R3000/R4000 +** +** +** 1) Initialize the STATUS Register +** a) Clear parity error bit +** b) Set co_processor 1 usable bit ON +** c) Clear all IntMask Enables +** d) Set kernel/disabled mode +** 2) Initialize Cause Register +** a) clear software interrupt bits +** 3) Determine FPU installed or not +** if not, clear CoProcessor 1 usable bit +** 4) Clear bss area +** 5) MUST allocate temporary stack until memory size determined +** It MUST be uncached to prevent overwriting when caches are cleared +** 6) Install exception handlers +** 7) Determine memory and cache sizes +** 8) Establish permanent stack (cached or uncached as defined by bss) +** 9) Flush Instruction and Data caches +** 10) If there is a Translation Lookaside Buffer, Clear the TLB +** 11) Execute initialization code if the IDT/c library is to be used +** +** 12) Jump to user's "main()" (boot_card() for RTEMS) +** 13) Jump to promexit +** +** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. +** This is used to mark code specific to R3xxx or R4xxx processors. +** IDT/C 6.x defines __mips to be the ISA level for which we're +** generating code. This is used to make sure the stack etc. is +** double word aligned, when using -mips3 (default) or -mips2, +** when compiling with IDT/C6.x +** +***************************************************************************/ + +FRAME(start,sp,0,ra) + + .set noreorder +#if __mips_fpr == 64 + li v0,SR_CU1|SR_FR|SR_DE /* initally clear ERL, enable FPU with 64 bit regs, disable cache errors */ +#else + li v0,SR_CU1|SR_DE /* initally clear ERL, enable FPU with 32 bit regs, disable cache errors */ +#endif + + mtc0 v0,C0_SR /* clr IntMsks/ kernel/disabled mode */ + nop + mtc0 zero,C0_CAUSE /* clear software interrupts */ + nop + + la t0,0xBE200000 /* on Hurricane board, enable interrupt output signal from UART ch. B */ + li t1,0x8 /* UART INT B signal is left tri-state'd after reset, this results in processor interrupt signal being driven active low */ + sw t1,0x10(t0) + + li v0,CFG_C_NONCOHERENT # initialise default cache mode + mtc0 v0,C0_CONFIG + +/* +** check to see if an fpu is really plugged in +*/ + li t3,0xaaaa5555 /* put a's and 5's in t3 */ + mtc1 t3,fp0 /* try to write them into fp0 */ + mtc1 zero,fp1 /* try to write zero in fp */ + mfc1 t0,fp0 + mfc1 t1,fp1 + nop + bne t0,t3,1f /* branch if no match */ + nop + bne t1,zero,1f /* double check for positive id */ + nop + /* We have a FPU. clear fcsr */ + ctc1 zero, fcr31 + j 2f /* status register already correct */ + nop +1: + li v0,SR_DE /* clear ERL and disable FPA */ + + mtc0 v0, C0_SR /* reset status register */ +2: + la gp, _gp + +#if 0 + /* Initialize data sections from "rom" copy */ + la t0,_idata /* address of initialization data (copy of data sections placed in ROM) */ + la t1,_fdata /* start of initialized data section */ + la t2,_edata /* end of initialized data section */ +3: + lw t3,0(t0) + sw t3,0(t1) + addiu t1,t1,4 + bne t1,t2,3b + addiu t0,t0,4 +#endif + + /* clear bss before using it */ + la v0,_fbss /* start of bss */ + la v1,end /* end of bss */ +4: sw zero,0(v0) + bltu v0,v1,4b + add v0,4 + + +/************************************************************************ +** +** Temporary Stack - needed to handle stack saves until +** memory size is determined and permanent stack set +** +** MUST be uncached to avoid confusion at cache +** switching during memory sizing +** +*************************************************************************/ + /* For MIPS 3, we need to be sure that the stack is aligned on a + * double word boundary. + */ + andi t0, v0, 0x7 + beqz t0, 11f /* Last three bits Zero, already aligned */ + nop + add v0, 4 +11: + + or v0, K1BASE /* switch to uncached */ + add v1, v0, TMP_STKSIZE /* end of bss + length of tmp stack */ + sub v1, v1, (4*4) /* overhead */ + move sp, v1 /* set sp to top of stack */ +4: sw zero, 0(v0) + bltu v0, v1, 4b /* clear out temp stack */ + add v0, 4 + +/* jal init_exc_vecs */ /* install exception handlers */ +/* nop */ /* MUST do before memory probes */ + + /* Force processor into uncached space during memory/cache probes */ + la v0, 5f + li v1, K1BASE + or v0, v1 + j v0 + nop +5: + + li a0, HARD_CODED_MEM_SIZE /* Set memory size global */ + jal set_memory_size + nop + + la a0, sim_mem_cfg_struct + jal get_mem_conf /* Make call to get mem size */ + nop + la a0, sim_mem_cfg_struct + lw a0, 0(a0) /* Get memory size from struct */ + + jal config_cache /* determine size of D & I caches */ + nop + + move v0, a0 /* mem_size */ + + /* For MIPS 3, we need to be sure that the stack (and hence v0 + * here) is aligned on a double word boundary. + */ + andi t0, v0, 0x7 + beqz t0, 12f /* Last three bits Zero, already aligned */ + nop + subu v0, 4 /* mem_size was not aligned on doubleword bdry????*/ +12: + + + +/************************************************************************** +** +** Permanent Stack - now know top of memory, put permanent stack there +** +***************************************************************************/ + + la t2, _fbss /* cache mode as linked */ + and t2, 0xF0000000 /* isolate segment */ + la t1, 6f + j t1 /* back to original cache mode */ + nop +6: + or v0, t2 /* stack back to original cache mode */ + addiu v0,v0,-16 /* overhead */ + move sp, v0 /* now replace count w top of memory */ + move v1, v0 + subu v1, P_STACKSIZE /* clear requested stack size */ + +7: sw zero, 0(v1) /* clear P_STACKSIZE stack */ + bltu v1,v0,7b + add v1, 4 + .set reorder + +/* FIX THIS - This corrupts memory spaces */ +/* jal flush_cache_nowrite */ /* flush Data & Instruction caches */ + +/* jal mon_flush_cache */ + +/************************************************************************** +** +** If this chip supports a Translation Lookaside Buffer, clear it +** +***************************************************************************/ + + .set noreorder + mfc0 t1, C0_SR /* look at Status Register */ + nop + .set reorder + + jal init_tlb /* clear the tlb */ + +/* Force processor into cached instruction space for rest of initialization */ +#if 0 + la t0, 1f + li t1, K0BASE /* force into cached space */ + or t0, t1 + j t0 + nop +1: +#endif + +/************************************************************************ +** +** Initialization required if using IDT/c or libc.a, standard C Lib +** +** can SKIP if not necessary for application +** +************************************************************************/ +8: + +/* FIX THIS - Need the pmon equivalent + jal idtsim_init_sbrk + jal idtsim_init_file +*/ + +/*********************** END I/O initialization **********************/ + + + move a0,zero /* Set command line passed to main */ + jal boot_card + nop + + # jump to the "exit" routine + jal idtsim__exit + move a0,v0 # pass through the exit code + + + # FIX THIS - Need the pmon equivalent + # jal idtsim_promexit + +1: + beq zero,zero,1b + nop + +ENDFRAME(start) + +/* + * _sys_exit -- Exit from the application. Normally we cause a user trap + * to return to the ROM monitor for another run. NOTE: This is + * the only other routine we provide in the crt0.o object, since + * it may be tied to the "_start" routine. It also allows + * executables that contain a complete world to be linked with + * just the crt0.o object. + */ +FRAME(_sys_exit,sp,0,ra) + + break 1023 + nop +13: + b 13b # but loop back just in-case + nop + +ENDFRAME(_sys_exit) + + + + .globl __sizemem + .ent __sizemem +__sizemem: + li v0,HARD_CODED_MEM_SIZE + j ra + nop + .end __sizemem diff --git a/bsps/mips/jmr3904/start/start.S b/bsps/mips/jmr3904/start/start.S new file mode 100644 index 0000000000..92c0ddd956 --- /dev/null +++ b/bsps/mips/jmr3904/start/start.S @@ -0,0 +1,196 @@ +/* + * start.S -- startup file for JMR3904 BSP based upon crt0.S from + * newlib-1.8.2/libgloss/mips and adapted for RTEMS. + * + * crt0.S -- startup file for MIPS. + * + * Copyright (c) 1995, 1996, 1997 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ + +#include <rtems/asm.h> +#include <bsp/regs.h> + +#ifdef __mips16 +/* This file contains 32 bit assembly code. */ + .set nomips16 +#endif + +/* This is for referencing addresses that are not in the .sdata or + .sbss section under embedded-pic, or before we've set up gp. */ +#ifdef __mips_embedded_pic +# ifdef __mips64 +# define LA(t,x) la t,x-PICBASE ; daddu t,s0,t +# else +# define LA(t,x) la t,x-PICBASE ; addu t,s0,t +# endif +#else /* __mips_embedded_pic */ +# define LA(t,x) la t,x +#endif /* __mips_embedded_pic */ + + .text + .align 2 + +/* Without the following nop, GDB thinks _start is a data variable. + * This is probably a bug in GDB in handling a symbol that is at the + * start of the .text section. + */ + nop + + .globl _start + .ent _start +_start: + .set noreorder + /* Get the address of start into $5 in a position independent fashion. + ** This lets us know whether we have been relocated or not. + */ + $LF1 = . + 8 + bal $LF1 + nop +_branch: + move $5, $31 # $5 == where are we + li $6, 0x8800000c # $6 == where we want to be +/* #la $6,_branch */ + beq $5, $6, _start_in_ram + nop + /* relocate the code from EEPROM to RAM */ + la $7, _edata +relocate: + lw $8, ($5) # $8 = *EEPROM + addu $5, $5, 4 # EEPROM++ + sw $8, ($6) # *RAM = $8 + addu $6, $6, 4 # RAM++ + bne $6, $7, relocate # copied all the way to edata? + nop + la $6, _start_in_ram + jr $6 + nop + .end _start + + .globl _start_in_ram + .ent _start_in_ram +_start_in_ram: + nop + +#ifdef __mips_embedded_pic + PICBASE = .+8 + bal PICBASE + nop + move s0,$31 +#endif + + li v0, SR_CU1|SR_PE|SR_FR|SR_KX|SR_SX|SR_UX + mtc0 v0, C0_SR + mtc0 zero, C0_CAUSE + +/* Check for FPU presence */ +#ifndef __mips_soft_float +/* This doesn't work if there is no FPU. We get illegal instruction + exceptions. */ + li t2,0xAAAA5555 + mtc1 t2,fp0 /* write to FPR 0 */ + mtc1 zero,fp1 /* write to FPR 1 */ + mfc1 t0,fp0 + mfc1 t1,fp1 + nop + bne t0,t2,1f /* check for match */ + nop + bne t1,zero,1f /* double check */ + nop +#ifndef __mips64 /* Clear the FR bit */ + li v0, SR_CU1|SR_PE|SR_KX|SR_SX|SR_UX + mtc0 v0, C0_SR +#endif + j 2f + nop +#endif +1: + li v0, SR_PE|SR_FR|SR_KX|SR_SX|SR_UX + mtc0 v0, C0_SR +2: +/* Fix high bits, if any, of the PC so that exception handling + doesn't get confused. */ + LA (v0, 3f) + jr v0 + nop +3: + LA (gp, _gp) # set the global data pointer + .end _start_in_ram + +/* + * zero out the bss section. + */ + .globl zerobss + .ent zerobss +zerobss: + LA (v0, _fbss) + LA (v1, _end) +3: + sw zero,0(v0) + bltu v0,v1,3b + addiu v0,v0,4 # executed in delay slot + + la t0, _stack_init # initialize stack so we + /* We must subtract 24 bytes for the 3 8 byte arguments to main, in + case main wants to write them back to the stack. The caller is + supposed to allocate stack space for parameters in registers in + the old MIPS ABIs. We must do this even though we aren't passing + arguments, because main might be declared to have them. + + Some ports need a larger alignment for the stack, so we subtract + 32, which satisifes the stack for the arguments and keeps the + stack pointer better aligned. */ + subu t0,t0,32 + move sp,t0 # set stack pointer + .end zerobss + + .globl exit .text + .globl init + .ent init +init: + + move a0,zero # set command line to 0 + jal boot_card # call the program start function + nop + + /* fall through to the "exit" routine */ + jal _sys_exit /* call libc exit to run the G++ */ + /* destructors */ + move a0,v0 /* pass through the exit code */ + .end init + +/* + * _sys_exit -- Exit from the application. Normally we cause a user trap + * to return to the ROM monitor for another run. NOTE: This is + * the only other routine we provide in the crt0.o object, since + * it may be tied to the "_start" routine. It also allows + * executables that contain a complete world to be linked with + * just the crt0.o object. + */ + .globl bsp_reset +bsp_reset: + .globl _sys_exit + .ent _sys_exit +_sys_exit: +7: +#ifdef GCRT0 + jal _mcleanup + nop +#endif + /* break instruction can cope with 0xfffff, but GAS limits the range: */ + break 1023 + nop + b 7b # but loop back just in-case + nop + .end _sys_exit + +/* EOF crt0.S */ diff --git a/bsps/mips/malta/start/start.S b/bsps/mips/malta/start/start.S new file mode 100644 index 0000000000..8f5f96489f --- /dev/null +++ b/bsps/mips/malta/start/start.S @@ -0,0 +1,221 @@ +/* + * start.S -- startup file for JMR3904 BSP based upon crt0.S from + * newlib-1.8.2/libgloss/mips and adapted for RTEMS. + * + * crt0.S -- startup file for MIPS. + * + * Copyright (c) 1995, 1996, 1997 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ + +#include <rtems/asm.h> +#include <bsp/regs.h> + +#include <bsp.h> + +#ifdef __mips16 +/* This file contains 32 bit assembly code. */ + .set nomips16 +#endif + +/* This is for referencing addresses that are not in the .sdata or + .sbss section under embedded-pic, or before we've set up gp. */ +#ifdef __mips_embedded_pic +# ifdef __mips64 +# define LA(t,x) la t,x-PICBASE ; daddu t,s0,t +# else +# define LA(t,x) la t,x-PICBASE ; addu t,s0,t +# endif +#else /* __mips_embedded_pic */ +# define LA(t,x) la t,x +#endif /* __mips_embedded_pic */ + + .text + .align 2 + +/* Without the following nop, GDB thinks _start is a data variable. + * This is probably a bug in GDB in handling a symbol that is at the + * start of the .text section. + */ + nop + nop + nop + nop + nop + nop + nop + nop + nop + .globl _start + .ent _start +_start: + nop + nop + nop + nop + nop + nop + nop + nop + .set noreorder + /* Get the address of start into $5 in a position independent fashion. + ** This lets us know whether we have been relocated or not. + */ + $LF1 = . + 8 + bal $LF1 + nop +_branch: +#if 0 + move $5, $31 # $5 == where are we + li $6, 0x8800000c # $6 == where we want to be +/* #la $6,_branch */ + beq $5, $6, _start_in_ram + nop + /* relocate the code from EEPROM to RAM */ + la $7, _edata +relocate: + nop + lw $8, ($5) # $8 = *EEPROM + addu $5, $5, 4 # EEPROM++ + sw $8, ($6) # *RAM = $8 + addu $6, $6, 4 # RAM++ + bne $6, $7, relocate # copied all the way to edata? + nop + la $6, _start_in_ram + jr $6 + nop + .end _start + + .globl _start_in_ram + .ent _start_in_ram +#endif +_start_in_ram: + nop +#if 0 +#ifdef __mips_embedded_pic + PICBASE = .+8 + bal PICBASE + nop + move s0,$31 +#endif +#endif + li v0, SR_CU1|SR_PE|SR_FR|SR_KX|SR_SX|SR_UX + mtc0 v0, C0_SR + mtc0 zero, C0_CAUSE + +#if 0 +/* Check for FPU presence */ +#ifndef __mips_soft_float +/* This doesn't work if there is no FPU. We get illegal instruction + exceptions. */ + li t2,0xAAAA5555 + mtc1 t2,fp0 /* write to FPR 0 */ + mtc1 zero,fp1 /* write to FPR 1 */ + mfc1 t0,fp0 + mfc1 t1,fp1 + nop + bne t0,t2,1f /* check for match */ + nop + bne t1,zero,1f /* double check */ + nop +#ifndef __mips64 /* Clear the FR bit */ + li v0, SR_CU1|SR_PE|SR_KX|SR_SX|SR_UX + mtc0 v0, C0_SR +#endif + j 2f + nop +#endif +#endif + +1: + li v0, SR_PE|SR_FR|SR_KX|SR_SX|SR_UX + mtc0 v0, C0_SR +2: +/* Fix high bits, if any, of the PC so that exception handling + doesn't get confused. */ + LA (v0, 3f) + jr v0 + nop +3: + LA (gp, _gp) # set the global data pointer +#if 0 + .end _start_in_ram +#else + .end _start +#endif + +/* + * zero out the bss section. + */ + .globl zerobss + .ent zerobss +zerobss: + LA (v0, _fbss) + LA (v1, _end) +3: + sw zero,0(v0) + bltu v0,v1,3b + addiu v0,v0,4 # executed in delay slot + + la t0, _stack_init # initialize stack so we + /* We must subtract 24 bytes for the 3 8 byte arguments to main, in + case main wants to write them back to the stack. The caller is + supposed to allocate stack space for parameters in registers in + the old MIPS ABIs. We must do this even though we aren't passing + arguments, because main might be declared to have them. + + Some ports need a larger alignment for the stack, so we subtract + 32, which satisifes the stack for the arguments and keeps the + stack pointer better aligned. */ + subu t0,t0,32 + move sp,t0 # set stack pointer + .end zerobss + + .globl exit .text + .globl init + .ent init +init: + nop + jal init_tlb /* clear the tlb */ + move a0,zero # set command line to 0 + jal boot_card # call the program start function + nop + +dead: + b dead + nop + .end init + +/* + * _sys_exit -- Exit from the application. Normally we cause a user trap + * to return to the ROM monitor for another run. NOTE: This is + * the only other routine we provide in the crt0.o object, since + * it may be tied to the "_start" routine. It also allows + * executables that contain a complete world to be linked with + * just the crt0.o object. + */ + .globl _sys_exit + .ent _sys_exit +_sys_exit: +7: +#ifdef GCRT0 + jal _mcleanup + nop +#endif + /* break instruction can cope with 0xfffff, but GAS limits the range: */ + break 1023 + nop + b 7b # but loop back just in-case + nop + .end _sys_exit + +/* EOF crt0.S */ diff --git a/bsps/mips/rbtx4925/start/start.S b/bsps/mips/rbtx4925/start/start.S new file mode 100644 index 0000000000..058426f8c7 --- /dev/null +++ b/bsps/mips/rbtx4925/start/start.S @@ -0,0 +1,360 @@ +/* + +Based upon IDT provided code with the following release: + +This source code has been made available to you by IDT on an AS-IS +basis. Anyone receiving this source is licensed under IDT copyrights +to use it in any way he or she deems fit, including copying it, +modifying it, compiling it, and redistributing it either with or +without modifications. No license under IDT patents or patent +applications is to be implied by the copyright license. + +Any user of this software should understand that IDT cannot provide +technical support for this software and will not be responsible for +any consequences resulting from the use of this software. + +Any person who transfers this source code or any derivative work must +include the IDT copyright notice, this paragraph, and the preceeding +two paragraphs in the transferred software. + +COPYRIGHT IDT CORPORATION 1996 +LICENSED MATERIAL - PROGRAM PROPERTY OF IDT + + +************************************************************************* +** +** Copyright 1991-95 Integrated Device Technology, Inc. +** All Rights Reserved +** +** idt_csu.S -- IDT stand alone startup code +** +**************************************************************************/ +#include <rtems/mips/iregdef.h> +#include <rtems/mips/idtcpu.h> +#include <rtems/asm.h> + +#include <bsp.h> + + .extern mon_flush_cache + +#if 0 + .extern _fdata,4 /* this is defined by the linker */ + .extern _edata,4 /* this is defined by the linker */ + .extern _idata,4 /* this is defined by the linker */ +#endif + .extern _fbss,4 /* this is defined by the linker */ + .extern end,4 /* this is defined by the linker */ + + .lcomm sim_mem_cfg_struct,12 + + .text + +#define HARD_CODED_MEM_SIZE 0x1000000 /* RBTX4925 has 16 megabytes of RAM */ +#define PMON_VECTOR 0xbfc00500 + +#define TMP_STKSIZE 1024 + +/* +** P_STACKSIZE is the size of the Prom Stack. +** the prom stack grows downward +*/ +#define P_STACKSIZE 0x2000 /* sets stack size to 8k */ + + +/************************************************************************** +** +** start - Typical standalone start up code required for R3000/R4000 +** +** +** 1) Initialize the STATUS Register +** a) Clear parity error bit +** b) Set co_processor 1 usable bit ON +** c) Clear all IntMask Enables +** d) Set kernel/disabled mode +** 2) Initialize Cause Register +** a) clear software interrupt bits +** 3) Determine FPU installed or not +** if not, clear CoProcessor 1 usable bit +** 4) Initialize data areas. Clear bss area. +** 5) MUST allocate temporary stack until memory size determined +** It MUST be uncached to prevent overwriting when caches are cleared +** 6) Install exception handlers +** 7) Determine memory and cache sizes +** 8) Establish permanent stack (cached or uncached as defined by bss) +** 9) Flush Instruction and Data caches +** 10) If there is a Translation Lookaside Buffer, Clear the TLB +** 11) Execute initialization code if the IDT/c library is to be used +** +** 12) Jump to user's "main()" +** 13) Jump to promexit +** +** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. +** This is used to mark code specific to R3xxx or R4xxx processors. +** IDT/C 6.x defines __mips to be the ISA level for which we're +** generating code. This is used to make sure the stack etc. is +** double word aligned, when using -mips3 (default) or -mips2, +** when compiling with IDT/C6.x +** +***************************************************************************/ + +FRAME(start,sp,0,ra) + + .set noreorder +#if __mips_fpr == 64 + li v0,SR_CU1|SR_FR /* initally clear ERL, enable FPU with 64 bit regs */ +#else + li v0,SR_CU1 /* initally clear ERL, enable FPU with 32 bit regs */ +#endif + + mtc0 v0,C0_SR /* clr IntMsks/ kernel/disabled mode */ + nop + mtc0 zero,C0_CAUSE /* clear software interrupts */ + nop + + li v0,CFG_C_NONCOHERENT /* initialise default cache mode */ + mtc0 v0,C0_CONFIG + +/* +** check to see if a fpu is really plugged in +*/ + li t3,0xaaaa5555 /* put a's and 5's in t3 */ + mtc1 t3,fp0 /* try to write them into fp0 */ + mtc1 zero,fp1 /* try to write zero in fp */ + mfc1 t0,fp0 + mfc1 t1,fp1 + nop + bne t0,t3,1f /* branch if no match */ + nop + bne t1,zero,1f /* double check for positive id */ + nop + /* We have a FPU. clear fcsr */ + ctc1 zero, fcr31 + j 2f /* status register already correct */ + nop +1: + li v0,0x0 /* clear ERL and disable FPA */ + + mtc0 v0, C0_SR /* reset status register */ +2: + la gp, _gp /* Initialize gp register (pointer to "small" data)*/ + +#if 0 + /* Initialize data sections from "rom" copy */ + la t0,_idata /* address of initialization data (copy of data sections placed in ROM) */ + la t1,_fdata /* start of initialized data section */ + la t2,_edata /* end of initialized data section */ +3: + lw t3,0(t0) + sw t3,0(t1) + addiu t1,t1,4 + bne t1,t2,3b + addiu t0,t0,4 +#endif + + /* clear bss before using it */ + la v0,_fbss /* start of bss */ + la v1,end /* end of bss */ +4: sw zero,0(v0) + bltu v0,v1,4b + add v0,4 + + +/************************************************************************ +** +** Temporary Stack - needed to handle stack saves until +** memory size is determined and permanent stack set +** +** MUST be uncached to avoid confusion at cache +** switching during memory sizing +** +*************************************************************************/ + /* For MIPS 3, we need to be sure that the stack is aligned on a + * double word boundary. + */ + andi t0, v0, 0x7 + beqz t0, 11f /* Last three bits Zero, already aligned */ + nop + add v0, 4 +11: + + or v0, K1BASE /* switch to uncached */ + add v1, v0, TMP_STKSIZE /* end of bss + length of tmp stack */ + sub v1, v1, (4*4) /* overhead */ + move sp, v1 /* set sp to top of stack */ +4: sw zero, 0(v0) + bltu v0, v1, 4b /* clear out temp stack */ + add v0, 4 + +/* jal init_exc_vecs */ /* install exception handlers */ +/* nop */ /* MUST do before memory probes */ + + /* Force processor into uncached space during memory/cache probes */ + la v0, 5f + li v1, K1BASE + or v0, v1 + j v0 + nop +5: + + li a0, HARD_CODED_MEM_SIZE /* Set memory size global */ + jal set_memory_size + nop + + la a0, sim_mem_cfg_struct + jal get_mem_conf /* Make call to get mem size */ + nop + la a0, sim_mem_cfg_struct + lw a0, 0(a0) /* Get memory size from struct */ + + jal config_cache /* determine size of D & I caches */ + nop + + move v0, a0 /* mem_size */ + + /* For MIPS 3, we need to be sure that the stack (and hence v0 + * here) is aligned on a double word boundary. + */ + andi t0, v0, 0x7 + beqz t0, 12f /* Last three bits Zero, already aligned */ + nop + subu v0, 4 /* mem_size was not aligned on doubleword bdry????*/ +12: + + + +/************************************************************************** +** +** Permanent Stack - now know top of memory, put permanent stack there +** +***************************************************************************/ + + la t2, _fbss /* cache mode as linked */ + and t2, 0xF0000000 /* isolate segment */ + la t1, 6f + j t1 /* back to original cache mode */ + nop +6: + or v0, t2 /* stack back to original cache mode */ + addiu v0,v0,-16 /* overhead */ + move sp, v0 /* now replace count w top of memory */ + move v1, v0 + subu v1, P_STACKSIZE /* clear requested stack size */ + +7: sw zero, 0(v1) /* clear P_STACKSIZE stack */ + bltu v1,v0,7b + add v1, 4 + + +/* Invalidate data cache*/ + lui t0, 0x8000 /* Set starting address */ + addi t1, t0, 0x2000 /* Calculate end address (assume worst case of 32 KByte / 4 Way cache) */ + /* D-Cache Writeback and Invalidate */ +1: bge t0, t1, 2f /* if(t0>=end_addr) then exit */ + nop + cache 1, 0(t0) /* Index_Writeback_Inv_D way 0 */ + cache 1, 1(t0) /* Index_Writeback_Inv_D way 1 */ + cache 1, 2(t0) /* Index_Writeback_Inv_D way 2 */ + cache 1, 3(t0) /* Index_Writeback_Inv_D way 3 */ + b 1b + addi t0, t0, 32 +2: + +/* Invalidate instruction cache*/ + lui t0, 0x8000 /* Set starting address */ + addi t1, t0, 0x2000 /* Calculate end address (assume worst case of 32 KByte / 4 Way cache) */ + /* I-Cache Disable */ + mfc0 t2, C0_CONFIG /* get C0_Config */ + lui t3, 0x2 /* C0_CONFIG#17 ICE# */ + or t3, t2, t3 /* set ICE# bit */ + mtc0 t3, C0_CONFIG /* set C_Config */ + b 1f /* stop streaming */ + nop + /* I-Cache Invalidate */ +1: bge t0, t1, 2f /* if(t0>=end_addr) then exit */ + nop + cache 0, 0(t0) /* Index_Invalidate_I way 0 */ + cache 0, 1(t0) /* Index_Invalidate_I way 1 */ + cache 0, 2(t0) /* Index_Invalidate_I way 2 */ + cache 0, 3(t0) /* Index_Invalidate_I way 3 */ + b 1b + addi t0, t0, 32 + /* I-Cache Enable */ +2: mtc0 t2, C0_CONFIG /* set C0_Config */ + nop + +/* Lock first 4k of PMON into instruction cache. This includes interrupt service code which + we don't want to run out of slow flash device. */ + + la t0,0x9fc00000 + li t1, 0x1000 + + move t3, t0 + addu t1, t0, t1 +1: bge t0, t1, 2f + nop + lui t2, 0x1fff /* MASK */ + ori t2, t2, 0xf000 + and t2, t3, t2 /* virtual->physical */ + srl t2, t2, 4 /* [31:12] --> [35:8] */ + ori t2, t2, 0x00c4 /* Set Valid & Lock Bits */ + mtc0 t2, C0_TAGLO /* Load data to TagLo reg. */ + nop + cache 0x08, 3(t0) /* 2(I)=0x08: Index_Store_Tag(I$) Way3*/ + nop + cache 0x14, 3(t0) /* 5(I)=0x14: Fill(Memory->Cache) Way3*/ + b 1b + addi t0, t0, 32 +2: nop + + .set reorder + +/* +** Clear Translation Lookaside Buffer (TLB) +*/ + jal init_tlb /* clear the tlb */ + +/* +** End of CPU initialization, ready to start kernel +*/ + move a0,zero /* Set argc passed to main */ + jal boot_card + nop + +/* Kernel has been shutdown, jump to the "exit" routine */ + jal _sys_exit + move a0,v0 # pass through the exit code + +1: + beq zero,zero,1b + nop + +ENDFRAME(start) + +/* + * _sys_exit -- Exit from the application. Normally we cause a user trap + * to return to the ROM monitor for another run. NOTE: This is + * the only other routine we provide in the crt0.o object, since + * it may be tied to the "_start" routine. It also allows + * executables that contain a complete world to be linked with + * just the crt0.o object. + */ +FRAME(_sys_exit,sp,0,ra) + + break 1023 + nop +13: + b 13b # but loop back just in-case + nop + +ENDFRAME(_sys_exit) + + + + .globl __sizemem + .ent __sizemem +__sizemem: + li v0,HARD_CODED_MEM_SIZE + j ra + nop + .end __sizemem + diff --git a/bsps/mips/rbtx4938/start/start.S b/bsps/mips/rbtx4938/start/start.S new file mode 100644 index 0000000000..406f1b6bbd --- /dev/null +++ b/bsps/mips/rbtx4938/start/start.S @@ -0,0 +1,359 @@ +/* + +Based upon IDT provided code with the following release: + +This source code has been made available to you by IDT on an AS-IS +basis. Anyone receiving this source is licensed under IDT copyrights +to use it in any way he or she deems fit, including copying it, +modifying it, compiling it, and redistributing it either with or +without modifications. No license under IDT patents or patent +applications is to be implied by the copyright license. + +Any user of this software should understand that IDT cannot provide +technical support for this software and will not be responsible for +any consequences resulting from the use of this software. + +Any person who transfers this source code or any derivative work must +include the IDT copyright notice, this paragraph, and the preceeding +two paragraphs in the transferred software. + +COPYRIGHT IDT CORPORATION 1996 +LICENSED MATERIAL - PROGRAM PROPERTY OF IDT + + +************************************************************************* +** +** Copyright 1991-95 Integrated Device Technology, Inc. +** All Rights Reserved +** +** idt_csu.S -- IDT stand alone startup code +** +**************************************************************************/ +#include <rtems/mips/iregdef.h> +#include <rtems/mips/idtcpu.h> +#include <rtems/asm.h> + +#include <bsp.h> + + .extern mon_flush_cache + +#if 0 + .extern _fdata,4 /* this is defined by the linker */ + .extern _edata,4 /* this is defined by the linker */ + .extern _idata,4 /* this is defined by the linker */ +#endif + .extern _fbss,4 /* this is defined by the linker */ + .extern end,4 /* this is defined by the linker */ + + .lcomm sim_mem_cfg_struct,12 + + .text + +#define HARD_CODED_MEM_SIZE 0x1000000 /* RBTX4938 has 16 megabytes of RAM */ +#define PMON_VECTOR 0xbfc00500 + +#define TMP_STKSIZE 1024 + +/* +** P_STACKSIZE is the size of the Prom Stack. +** the prom stack grows downward +*/ +#define P_STACKSIZE 0x2000 /* sets stack size to 8k */ + +/************************************************************************** +** +** start - Typical standalone start up code required for R3000/R4000 +** +** +** 1) Initialize the STATUS Register +** a) Clear parity error bit +** b) Set co_processor 1 usable bit ON +** c) Clear all IntMask Enables +** d) Set kernel/disabled mode +** 2) Initialize Cause Register +** a) clear software interrupt bits +** 3) Determine FPU installed or not +** if not, clear CoProcessor 1 usable bit +** 4) Initialize data areas. Clear bss area. +** 5) MUST allocate temporary stack until memory size determined +** It MUST be uncached to prevent overwriting when caches are cleared +** 6) Install exception handlers +** 7) Determine memory and cache sizes +** 8) Establish permanent stack (cached or uncached as defined by bss) +** 9) Flush Instruction and Data caches +** 10) If there is a Translation Lookaside Buffer, Clear the TLB +** 11) Execute initialization code if the IDT/c library is to be used +** +** 12) Jump to user's "main()" +** 13) Jump to promexit +** +** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. +** This is used to mark code specific to R3xxx or R4xxx processors. +** IDT/C 6.x defines __mips to be the ISA level for which we're +** generating code. This is used to make sure the stack etc. is +** double word aligned, when using -mips3 (default) or -mips2, +** when compiling with IDT/C6.x +** +***************************************************************************/ + +FRAME(start,sp,0,ra) + + .set noreorder +#if __mips_fpr == 64 + li v0,SR_CU1|SR_FR /* initally clear ERL, enable FPU with 64 bit regs */ +#else + li v0,SR_CU1 /* initally clear ERL, enable FPU with 32 bit regs */ +#endif + + mtc0 v0,C0_SR /* clr IntMsks/ kernel/disabled mode */ + nop + mtc0 zero,C0_CAUSE /* clear software interrupts */ + nop + + li v0,CFG_C_NONCOHERENT /* initialise default cache mode */ + mtc0 v0,C0_CONFIG + +/* +** check to see if a fpu is really plugged in +*/ + li t3,0xaaaa5555 /* put a's and 5's in t3 */ + mtc1 t3,fp0 /* try to write them into fp0 */ + mtc1 zero,fp1 /* try to write zero in fp */ + mfc1 t0,fp0 + mfc1 t1,fp1 + nop + bne t0,t3,1f /* branch if no match */ + nop + bne t1,zero,1f /* double check for positive id */ + nop + /* We have a FPU. clear fcsr */ + ctc1 zero, fcr31 + j 2f /* status register already correct */ + nop +1: + li v0,0x0 /* clear ERL and disable FPA */ + + mtc0 v0, C0_SR /* reset status register */ +2: + la gp, _gp /* Initialize gp register (pointer to "small" data)*/ + +#if 0 + /* Initialize data sections from "rom" copy */ + la t0,_idata /* address of initialization data (copy of data sections placed in ROM) */ + la t1,_fdata /* start of initialized data section */ + la t2,_edata /* end of initialized data section */ +3: + lw t3,0(t0) + sw t3,0(t1) + addiu t1,t1,4 + bne t1,t2,3b + addiu t0,t0,4 +#endif + + /* clear bss before using it */ + la v0,_fbss /* start of bss */ + la v1,end /* end of bss */ +4: sw zero,0(v0) + bltu v0,v1,4b + add v0,4 + + +/************************************************************************ +** +** Temporary Stack - needed to handle stack saves until +** memory size is determined and permanent stack set +** +** MUST be uncached to avoid confusion at cache +** switching during memory sizing +** +*************************************************************************/ + /* For MIPS 3, we need to be sure that the stack is aligned on a + * double word boundary. + */ + andi t0, v0, 0x7 + beqz t0, 11f /* Last three bits Zero, already aligned */ + nop + add v0, 4 +11: + + or v0, K1BASE /* switch to uncached */ + add v1, v0, TMP_STKSIZE /* end of bss + length of tmp stack */ + sub v1, v1, (4*4) /* overhead */ + move sp, v1 /* set sp to top of stack */ +4: sw zero, 0(v0) + bltu v0, v1, 4b /* clear out temp stack */ + add v0, 4 + +/* jal init_exc_vecs */ /* install exception handlers */ +/* nop */ /* MUST do before memory probes */ + + /* Force processor into uncached space during memory/cache probes */ + la v0, 5f + li v1, K1BASE + or v0, v1 + j v0 + nop +5: + + li a0, HARD_CODED_MEM_SIZE /* Set memory size global */ + jal set_memory_size + nop + + la a0, sim_mem_cfg_struct + jal get_mem_conf /* Make call to get mem size */ + nop + la a0, sim_mem_cfg_struct + lw a0, 0(a0) /* Get memory size from struct */ + + jal config_cache /* determine size of D & I caches */ + nop + + move v0, a0 /* mem_size */ + + /* For MIPS 3, we need to be sure that the stack (and hence v0 + * here) is aligned on a double word boundary. + */ + andi t0, v0, 0x7 + beqz t0, 12f /* Last three bits Zero, already aligned */ + nop + subu v0, 4 /* mem_size was not aligned on doubleword bdry????*/ +12: + + + +/************************************************************************** +** +** Permanent Stack - now know top of memory, put permanent stack there +** +***************************************************************************/ + + la t2, _fbss /* cache mode as linked */ + and t2, 0xF0000000 /* isolate segment */ + la t1, 6f + j t1 /* back to original cache mode */ + nop +6: + or v0, t2 /* stack back to original cache mode */ + addiu v0,v0,-16 /* overhead */ + move sp, v0 /* now replace count w top of memory */ + move v1, v0 + subu v1, P_STACKSIZE /* clear requested stack size */ + +7: sw zero, 0(v1) /* clear P_STACKSIZE stack */ + bltu v1,v0,7b + add v1, 4 + + +/* Invalidate data cache*/ + lui t0, 0x8000 /* Set starting address */ + addi t1, t0, 0x2000 /* Calculate end address (assume worst case of 32 KByte / 4 Way cache) */ + /* D-Cache Writeback and Invalidate */ +1: bge t0, t1, 2f /* if(t0>=end_addr) then exit */ + nop + cache 1, 0(t0) /* Index_Writeback_Inv_D way 0 */ + cache 1, 1(t0) /* Index_Writeback_Inv_D way 1 */ + cache 1, 2(t0) /* Index_Writeback_Inv_D way 2 */ + cache 1, 3(t0) /* Index_Writeback_Inv_D way 3 */ + b 1b + addi t0, t0, 32 +2: + +/* Invalidate instruction cache*/ + lui t0, 0x8000 /* Set starting address */ + addi t1, t0, 0x2000 /* Calculate end address (assume worst case of 32 KByte / 4 Way cache) */ + /* I-Cache Disable */ + mfc0 t2, C0_CONFIG /* get C0_Config */ + lui t3, 0x2 /* C0_CONFIG#17 ICE# */ + or t3, t2, t3 /* set ICE# bit */ + mtc0 t3, C0_CONFIG /* set C_Config */ + b 1f /* stop streaming */ + nop + /* I-Cache Invalidate */ +1: bge t0, t1, 2f /* if(t0>=end_addr) then exit */ + nop + cache 0, 0(t0) /* Index_Invalidate_I way 0 */ + cache 0, 1(t0) /* Index_Invalidate_I way 1 */ + cache 0, 2(t0) /* Index_Invalidate_I way 2 */ + cache 0, 3(t0) /* Index_Invalidate_I way 3 */ + b 1b + addi t0, t0, 32 + /* I-Cache Enable */ +2: mtc0 t2, C0_CONFIG /* set C0_Config */ + nop + +/* Lock first 4k of PMON into instruction cache. This includes interrupt service code which + we don't want to run out of slow flash device. */ + + la t0,0x9fc00000 + li t1, 0x1000 + + move t3, t0 + addu t1, t0, t1 +1: bge t0, t1, 2f + nop + lui t2, 0x1fff /* MASK */ + ori t2, t2, 0xf000 + and t2, t3, t2 /* virtual->physical */ + srl t2, t2, 4 /* [31:12] --> [35:8] */ + ori t2, t2, 0x00c4 /* Set Valid & Lock Bits */ + mtc0 t2, C0_TAGLO /* Load data to TagLo reg. */ + nop + cache 0x08, 3(t0) /* 2(I)=0x08: Index_Store_Tag(I$) Way3*/ + nop + cache 0x14, 3(t0) /* 5(I)=0x14: Fill(Memory->Cache) Way3*/ + b 1b + addi t0, t0, 32 +2: nop + + .set reorder + +/* +** Clear Translation Lookaside Buffer (TLB) +*/ + jal init_tlb /* clear the tlb */ + +/* +** End of CPU initialization, ready to start kernel +*/ + move a0,zero /* Set command line passed to boot_card */ + jal boot_card + nop + +/* Kernel has been shutdown, jump to the "exit" routine */ + jal _sys_exit + move a0,v0 # pass through the exit code + +1: + beq zero,zero,1b + nop + +ENDFRAME(start) + +/* + * _sys_exit -- Exit from the application. Normally we cause a user trap + * to return to the ROM monitor for another run. NOTE: This is + * the only other routine we provide in the crt0.o object, since + * it may be tied to the "_start" routine. It also allows + * executables that contain a complete world to be linked with + * just the crt0.o object. + */ +FRAME(_sys_exit,sp,0,ra) + + break 1023 + nop +13: + b 13b # but loop back just in-case + nop + +ENDFRAME(_sys_exit) + + + + .globl __sizemem + .ent __sizemem +__sizemem: + li v0,HARD_CODED_MEM_SIZE + j ra + nop + .end __sizemem + |