bsps/mips: Move libcpu content to bsps

This patch is a part of the BSP source reorganization.

Update #3285.

4 files changed, 281 insertions, 0 deletions

diff --git a/bsps/mips/shared/irq/installisrentries.c b/bsps/mips/shared/irq/installisrentries.c
new file mode 100644
index 0000000000..9380a26f37
--- /dev/null
+++ b/bsps/mips/shared/irq/installisrentries.c
@@ -0,0 +1,29 @@
+#include <rtems.h>
+#include <rtems/mips/idtcpu.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <libcpu/isr_entries.h>
+
+void mips_install_isr_entries( void )
+{
+#if __mips == 1
+  memcpy( (void *)UT_VEC, exc_utlb_code, 40 );  /* utlbmiss vector */
+  memcpy( (void *)DB_VEC, exc_dbg_code, 40 );
+  memcpy( (void *)E_VEC, exc_norm_code, 40 );   /* exception vevtor */
+
+#elif __mips == 32
+  memcpy( (void *)T_VEC, exc_tlb_code, 40 );    /* tlbmiss vector */
+  memcpy( (void *)X_VEC, exc_xtlb_code, 40 );   /* xtlbmiss vector */
+  memcpy( (void *)C_VEC, exc_cache_code, 40 );  /* cache error vector */
+  memcpy( (void *)E_VEC, exc_norm_code, 40 );   /* exception vector */
+
+#elif __mips == 3
+  memcpy( (void *)T_VEC, exc_tlb_code, 40 );    /* tlbmiss vector */
+  memcpy( (void *)X_VEC, exc_xtlb_code, 40 );   /* xtlbmiss vector */
+  memcpy( (void *)C_VEC, exc_cache_code, 40 );  /* cache error vector */
+  memcpy( (void *)E_VEC, exc_norm_code, 40 );   /* exception vector */
+#endif
+
+  rtems_cache_flush_entire_data();
+}
diff --git a/bsps/mips/shared/irq/isr_entries.S b/bsps/mips/shared/irq/isr_entries.S
new file mode 100644
index 0000000000..2e3791cab2
--- /dev/null
+++ b/bsps/mips/shared/irq/isr_entries.S
@@ -0,0 +1,106 @@
+/*
+ *  This file contains the raw entry points for the exceptions.
+ *
+ *  COPYRIGHT (c) 1989-2000.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems/asm.h>
+#include <rtems/mips/iregdef.h>
+#include <rtems/mips/idtcpu.h>
+
+/*
+ *  MIPS ISA Level 1 entries
+ */
+
+#if __mips == 1
+
+FRAME(exc_norm_code,sp,0,ra)
+	la	k0, _ISR_Handler /* generic external int hndlr */
+	j	k0
+	nop
+ENDFRAME(exc_norm_code)
+
+FRAME(exc_dbg_code,sp,0,ra)
+        la      k0, _DBG_Handler /* debug interrupt */
+        j       k0
+	nop
+ENDFRAME(exc_dbg_code)
+
+/* XXX this is dependent on IDT/SIM and needs to be addressed */
+FRAME(exc_utlb_code,sp,0,ra)
+        la      k0, (R_VEC+((48)*8))
+        j       k0
+	nop
+ENDFRAME(exc_utlb_code)
+
+/*
+ * MIPS ISA Level 32
+ * XXX Again, reliance on SIM. Not good.??????????
+ */
+#elif __mips == 32
+FRAME(exc_tlb_code,sp,0,ra)
+        la      k0, _ISR_Handler
+        j       k0
+	nop
+ENDFRAME(exc_tlb_code)
+
+FRAME(exc_xtlb_code,sp,0,ra)
+        la      k0, _ISR_Handler
+        j       k0
+	nop
+
+ENDFRAME(exc_xtlb_code)
+
+FRAME(exc_cache_code,sp,0,ra)
+        la      k0, _ISR_Handler
+        j       k0
+	nop
+ENDFRAME(exc_cache_code)
+
+FRAME(exc_norm_code,sp,0,ra)
+	la	k0, _ISR_Handler /* generic external int hndlr */
+	j	k0
+	nop
+ENDFRAME(exc_norm_code)
+
+/*
+ * MIPS ISA Level 3
+ * XXX Again, reliance on SIM. Not good.
+ */
+#elif __mips == 3
+
+FRAME(exc_tlb_code,sp,0,ra)
+        la      k0, (R_VEC+((112)*8)) /* R4000 Sim location */
+        j       k0
+	nop
+ENDFRAME(exc_tlb_code)
+
+FRAME(exc_xtlb_code,sp,0,ra)
+        la      k0, (R_VEC+((112)*8)) /* R4000 Sim location */
+        j       k0
+	nop
+
+ENDFRAME(exc_xtlb_code)
+
+FRAME(exc_cache_code,sp,0,ra)
+        la      k0, (R_VEC+((112)*8)) /* R4000 Sim location */
+        j       k0
+	nop
+ENDFRAME(exc_cache_code)
+
+FRAME(exc_norm_code,sp,0,ra)
+	la	k0, _ISR_Handler /* generic external int hndlr */
+	j	k0
+	nop
+ENDFRAME(exc_norm_code)
+
+#else
+
+#error "isr_entries.S: ISA support problem"
+
+#endif
diff --git a/bsps/mips/shared/timer/gettime.S b/bsps/mips/shared/timer/gettime.S
new file mode 100644
index 0000000000..2661dfee33
--- /dev/null
+++ b/bsps/mips/shared/timer/gettime.S
@@ -0,0 +1,33 @@
+/*  gettime.s
+ *
+ *  This file contains the assembly code for the IDT 4650 timer driver.
+ *
+ *  Author:     Craig Lebakken <craigl@transition.com>
+ *
+ *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of Transition Networks not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      Transition Networks makes no representations about the suitability
+ *      of this software for any purpose.
+ */
+
+/* @(#)gettime.S       08/20/96     1.2 */
+
+#include <rtems/mips/iregdef.h>
+#include <rtems/mips/idtcpu.h>
+#include <rtems/asm.h>
+
+FRAME(mips_read_timer,sp,0,ra)
+	.set noreorder
+        mfc0 v0,C0_COUNT
+        nop
+        j ra
+	.set reorder
+ENDFRAME(mips_read_timer)
diff --git a/bsps/mips/shared/timer/timer.c b/bsps/mips/shared/timer/timer.c
new file mode 100644
index 0000000000..da5291a48a
--- /dev/null
+++ b/bsps/mips/shared/timer/timer.c
@@ -0,0 +1,113 @@
+/**
+ *  @file
+ *  @brief IDT 4650 Timer Driver.
+ *
+ *  This file manages the benchmark timer used by the RTEMS Timing Test
+ *  Suite.
+ */
+
+/*
+ *  Author:     Craig Lebakken <craigl@transition.com>
+ *
+ *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of Transition Networks not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      Transition Networks makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  derived from src/lib/libbsp/no_cpu/no_bsp/timer/timer.c
+ *
+ *  COPYRIGHT (c) 1989-1999.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <rtems/btimer.h>
+
+#define CLOCKS_PER_MICROSECOND ( CPU_CLOCK_RATE_MHZ )
+#define TIMER_MAX_VALUE 0xffffffff
+
+extern uint32_t   mips_read_timer( void );
+
+static bool benchmark_timer_find_average_overhead;
+static uint32_t   benchmark_timer_initial_value = 0;
+
+void benchmark_timer_initialize( void )
+{
+   benchmark_timer_initial_value = mips_read_timer();
+  /*
+   *  Somehow start the timer
+   */
+
+  /* Timer on 4650 is always running */
+}
+
+/*
+ *  The following controls the behavior of benchmark_timer_read().
+ *
+ *  AVG_OVEREHAD is the overhead for starting and stopping the timer.  It
+ *  is usually deducted from the number returned.
+ *
+ *  LEAST_VALID is the lowest number this routine should trust.  Numbers
+ *  below this are "noise" and zero is returned.
+ */
+
+#define AVG_OVERHEAD      8  /* It typically takes X.X microseconds */
+                             /* (Y countdowns) to start/stop the timer. */
+                             /* This value is in cycles. */
+#define LEAST_VALID       1  /* Don't trust a clicks value lower than this */
+
+benchmark_timer_t benchmark_timer_read( void )
+{
+  uint64_t   clicks;
+  uint32_t   total;
+
+  /*
+   *  Read the timer and see how many clicks it has been since we started.
+   */
+
+  clicks = mips_read_timer();   /* XXX: read some HW here */
+  if (clicks < benchmark_timer_initial_value)
+  {
+      clicks += TIMER_MAX_VALUE;
+  }
+  clicks -= benchmark_timer_initial_value;
+
+  /*
+   *  Total is calculated by taking into account the number of timer overflow
+   *  interrupts since the timer was initialized and clicks since the last
+   *  interrupts.
+   */
+#if 0 /* leave total in number of cycles */
+   total = clicks / CLOCKS_PER_MICROSECOND;
+#else
+   total = clicks;
+#endif
+
+  if ( benchmark_timer_find_average_overhead == 1 )
+    return total;          /* in # cycles units */
+  else {
+    if ( total < LEAST_VALID )
+      return 0;            /* below timer resolution */
+  /*
+   *  leave total in cycles
+   */
+      return (total - AVG_OVERHEAD);
+    }
+}
+
+void benchmark_timer_disable_subtracting_average_overhead(bool find_flag)
+{
+  benchmark_timer_find_average_overhead = find_flag;
+}