bsps: Move benchmark timer to bsps

This patch is a part of the BSP source reorganization.

Update #3285.

16 files changed, 1113 insertions, 0 deletions

diff --git a/bsps/m68k/av5282/btimer/btimer.c b/bsps/m68k/av5282/btimer/btimer.c
new file mode 100644
index 0000000000..8a8323e547
--- /dev/null
+++ b/bsps/m68k/av5282/btimer/btimer.c
@@ -0,0 +1,34 @@
+/*
+ *  Timer Init
+ *
+ *  Use the last DMA timer (DTIM3) as the diagnostic timer.
+ */
+
+#include <rtems.h>
+#include <rtems/btimer.h>
+#include <bsp.h>
+
+void
+benchmark_timer_initialize(void)
+{
+    int preScaleDivisor = 58;
+    int div = MCF5282_TIMER_DTMR_CLK_DIV1;
+    MCF5282_TIMER3_DTRR = 0x2710;
+    MCF5282_TIMER3_DTMR = 0;
+    MCF5282_TIMER3_DTMR = MCF5282_TIMER_DTMR_PS(preScaleDivisor - 1) | div |
+                          MCF5282_TIMER_DTMR_RST;
+}
+
+/*
+ * Return timer value in microsecond units
+ */
+uint32_t
+benchmark_timer_read(void)
+{
+    return MCF5282_TIMER3_DTCN;
+}
+
+void
+benchmark_timer_disable_subtracting_average_overhead(bool find_flag)
+{
+}
diff --git a/bsps/m68k/gen68340/btimer/btimer.c b/bsps/m68k/gen68340/btimer/btimer.c
new file mode 100644
index 0000000000..23cddd95b0
--- /dev/null
+++ b/bsps/m68k/gen68340/btimer/btimer.c
@@ -0,0 +1,256 @@
+/*
+ * ATTENTION: As MC68349 has no built-in Timer, the following code doesn't work
+ *            in a MC68349. You can't use FIFO full mode for the moment, but
+ *            it should be easy to fix this by using an external timer.
+ *
+ * Use TIMER 1 for TIMEOUT when using FIFO FULL mode in UART driver
+ * Use TIMER 2 for timing test suites
+ *
+ *  NOTE: It is important that the timer start/stop overhead be
+ *        determined when porting or modifying this code.
+ */
+
+/*
+ * Geoffroy Montel
+ * France Telecom - CNET/DSM/TAM/CAT
+ * 4, rue du Clos Courtel
+ * 35512 CESSON-SEVIGNE
+ * FRANCE
+ *
+ * e-mail: g_montel@yahoo.com
+ *
+ *  COPYRIGHT (c) 1989-1999.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <bsp.h>
+#include <rtems/btimer.h>
+#include <m340uart.h>
+#include <m340timer.h>
+#include <m68340.h>
+
+#define TIMER1_VECTOR 122
+#define TIMER1_IRQ_LEVEL 5
+#define TIMER1_INTERRUPT_ARBITRATION 5
+
+#define TIMER2_VECTOR 123
+#define TIMER2_IRQ_LEVEL 4
+#define TIMER2_INTERRUPT_ARBITRATION 4
+
+#define CLOCK_SPEED 25    /* in Mhz */
+
+#define max(a,b) (((a)>(b)) ? (a) : (b))
+
+void (*Restart_Fifo_Full_A_Timer)(void);
+void (*Restart_Check_A_Timer)(void);
+void (*Restart_Fifo_Full_B_Timer)(void);
+void (*Restart_Check_B_Timer)(void);
+
+int preload = 0;
+
+/*
+ * __Restart_Fifo_Full_Timer
+ *
+ * When a character is received, sets the TIMER to raise an interrupt at
+ * TIMEOUT.  It's necessary to prevent from not getting n-1 characters
+ * (with n the Uart Fifo size).
+ */
+static void __Restart_Fifo_Full_Timer (void)
+{
+  TSR1 |= m340_TO;
+  TCR1 &= ~m340_CPE;
+  WPREL11 = preload;
+  TCR1 |= m340_CPE;
+}
+
+/*
+ * __Restart_Check_Timer
+ *
+ * When no character has been received recently, check now and then if whether
+ * a there's a character in the FIFO
+ */
+static void __Restart_Check_Timer (void)
+{
+ TSR1 |= m340_TO;
+ TCR1 &= ~m340_CPE;
+ WPREL11 = 0xFFFF;
+ TCR1 |= m340_CPE;
+}
+
+/*
+ * __do_nothing
+ *
+ * We always restart the fifo full timer with a call to Restart_*_Timer
+ * if we do not use FIFO full, Restart_X_Timer are set to do __do_nothing
+ */
+static void __do_nothing (void)
+{
+}
+
+#define Fifo_Full_on_A \
+   (m340_uart_config[UART_CHANNEL_A].rx_mode==UART_FIFO_FULL && \
+    m340_uart_config[UART_CHANNEL_A].enable && \
+    m340_uart_config[UART_CHANNEL_A].mode==UART_INTERRUPTS)
+#define Fifo_Full_on_B \
+    (m340_uart_config[UART_CHANNEL_B].rx_mode==UART_FIFO_FULL && \
+    m340_uart_config[UART_CHANNEL_B].enable && \
+    m340_uart_config[UART_CHANNEL_B].mode==UART_INTERRUPTS)
+
+/*
+ * Fifo_Full_benchmark_timer_initialize
+ *
+ * initialize Timer 1 for FIFO full mode
+ */
+void Fifo_Full_benchmark_timer_initialize (void)
+{
+  float max_baud_rate;
+  int prescaler_output_tap = -1;
+  int nb_of_clock_ticks = 0;
+  rtems_isr_entry old_handler;
+
+  /*
+   *  USE TIMER 1 for UART FIFO FULL mode
+   */
+  if ( Fifo_Full_on_A || Fifo_Full_on_B ) {
+    /* Disable the timer */
+    TCR1 &= ~m340_SWR;
+
+    /* Reset the interrupts */
+    TSR1 &= ~(m340_TO | m340_TG | m340_TC);
+
+    /* Init the stop bit for normal operation, ignore FREEZE, user privileges,
+     * set interrupt arbitration.
+     */
+    TMCR1 = TIMER1_INTERRUPT_ARBITRATION;
+
+    /* interrupt priority level and interrupt vector */
+    TIR1 = TIMER1_VECTOR | (TIMER1_IRQ_LEVEL << 8);
+
+    /* compute prescaler */
+    if ( Fifo_Full_on_A && Fifo_Full_on_B) {
+      max_baud_rate = max(
+        m340_uart_config[UART_CHANNEL_A].rx_baudrate,
+        m340_uart_config[UART_CHANNEL_B].rx_baudrate
+      );
+    } else if ( Fifo_Full_on_A ) {
+      max_baud_rate = m340_uart_config[UART_CHANNEL_A].rx_baudrate;
+    } else
+      max_baud_rate = m340_uart_config[UART_CHANNEL_B].rx_baudrate;
+
+    /* find out config */
+    nb_of_clock_ticks = (10/max_baud_rate)*(CLOCK_SPEED*1000000)*1.2;
+    if (nb_of_clock_ticks < 0xFFFF) {
+      preload = nb_of_clock_ticks;
+      prescaler_output_tap = -1;
+    } else if (nb_of_clock_ticks/2 < 0xFFFF) {
+      preload = nb_of_clock_ticks/2;
+      prescaler_output_tap = m340_Divide_by_2;
+    } else if (nb_of_clock_ticks/4 < 0xFFFF) {
+      preload = nb_of_clock_ticks/4;
+      prescaler_output_tap = m340_Divide_by_4;
+    } else if (nb_of_clock_ticks/8 < 0xFFFF) {
+      preload = nb_of_clock_ticks/8;
+      prescaler_output_tap = m340_Divide_by_16;
+    } else if (nb_of_clock_ticks/16 < 0xFFFF) {
+      preload = nb_of_clock_ticks/16;
+      prescaler_output_tap = m340_Divide_by_16;
+    } else if (nb_of_clock_ticks/32 < 0xFFFF) {
+      preload = nb_of_clock_ticks/32;
+      prescaler_output_tap = m340_Divide_by_32;
+    } else if (nb_of_clock_ticks/64 < 0xFFFF) {
+      preload = nb_of_clock_ticks/64;
+      prescaler_output_tap = m340_Divide_by_64;
+    } else if (nb_of_clock_ticks/128 < 0xFFFF) {
+      preload = nb_of_clock_ticks/128;
+      prescaler_output_tap = m340_Divide_by_128;
+    } else if (nb_of_clock_ticks/256 < 0xFFFF) {
+      preload = nb_of_clock_ticks/256;
+      prescaler_output_tap = m340_Divide_by_256;
+    }
+
+    /* Input Capture/Output Compare (ICOC) */
+    TCR1 = m340_SWR | m340_TO_Enabled | m340_ICOC;
+    if (prescaler_output_tap!=-1) TCR1 |= prescaler_output_tap | m340_PSE;
+
+    /* install interrupt vector */
+    rtems_interrupt_catch(InterruptHandler, TIMER1_VECTOR, &old_handler);
+
+  } /* fifo full mode on a uart */
+
+  /* install routines */
+  if ( Fifo_Full_on_A ) {
+    Restart_Check_A_Timer     = __Restart_Check_Timer;
+    Restart_Fifo_Full_A_Timer = __Restart_Fifo_Full_Timer;
+  } else {
+    Restart_Check_A_Timer     = __do_nothing;
+    Restart_Fifo_Full_A_Timer = __do_nothing;
+  }
+
+  if ( Fifo_Full_on_B ) {
+    Restart_Check_B_Timer     = __Restart_Check_Timer;
+    Restart_Fifo_Full_B_Timer = __Restart_Fifo_Full_Timer;
+  } else {
+    Restart_Check_B_Timer     = __do_nothing;
+    Restart_Fifo_Full_B_Timer = __do_nothing;
+  }
+
+  /* start checking timer */
+  Restart_Check_A_Timer();
+  Restart_Check_B_Timer();
+}
+
+/*
+ * benchmark_timer_initialize
+ *
+ * init Timer for timing test suites
+ */
+void benchmark_timer_initialize (void)
+{
+  /* Disable the timer */
+  TCR2 &= ~m340_SWR;
+
+  /* Reset the interrupts */
+  TSR2 &= ~(m340_TO | m340_TG | m340_TC);
+
+  /* Init the stop bit for normal operation, ignore FREEZE, user privileges,
+     set interrupt arbitration */
+  TMCR1 = TIMER2_INTERRUPT_ARBITRATION;
+
+  /* interrupt priority level and interrupt vector */
+  TIR1 = TIMER2_VECTOR | (TIMER2_IRQ_LEVEL << 8);
+
+  /* Init the stop bit for normal operation, ignore FREEZE, user privileges,
+     set interrupt arbitration */
+  TMCR2 = TIMER2_INTERRUPT_ARBITRATION;
+
+  /* Preload register 1 */
+  WPREL21 = 0xFFFF;
+
+  /* Input Capture/Output Compare (ICOC) */
+  TCR2 = m340_SWR | m340_ICOC | m340_PSE | m340_Divide_by_16 | m340_CPE;
+}
+
+/*
+ * benchmark_timer_read
+ *
+ * Return timer value in microsecond units
+ */
+uint32_t benchmark_timer_read (void)
+{
+ /* there's CLOCK_SPEED / 16 micro seconds between two timer
+  * register decrements.
+  */
+ return (((0xFFFF - TCNTR2) * CLOCK_SPEED) / 16);
+}
+
+/*
+ * benchmark_timer_disable_subtracting_average_overhead
+ */
+void benchmark_timer_disable_subtracting_average_overhead(bool find_flag)
+{
+}
diff --git a/bsps/m68k/gen68360/btimer/btimer.c b/bsps/m68k/gen68360/btimer/btimer.c
new file mode 100644
index 0000000000..40a3e0a4c1
--- /dev/null
+++ b/bsps/m68k/gen68360/btimer/btimer.c
@@ -0,0 +1,83 @@
+/*
+ * Use TIMER 1 and TIMER 2 for Timing Test Suite
+ * The hardware on the MC68360 makes these routines very simple.
+ *
+ * Based on the `gen68302' board support package, and covered by the
+ * original distribution terms.
+ *
+ * W. Eric Norum
+ * Saskatchewan Accelerator Laboratory
+ * University of Saskatchewan
+ * Saskatoon, Saskatchewan, CANADA
+ * eric@skatter.usask.ca
+ */
+
+/*
+ *
+ *  Input parameters:  NONE
+ *
+ *  Output parameters:  NONE
+ *
+ *  NOTE: It is important that the timer start/stop overhead be
+ *        determined when porting or modifying this code.
+ *
+ *  COPYRIGHT (c) 1989-1999.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <rtems/btimer.h>
+#include <bsp.h>
+#include <rtems/m68k/m68360.h>
+
+void
+benchmark_timer_initialize (void)
+{
+	/*
+	 * Reset timers 1 and 2
+	 */
+	m360.tgcr &= ~0x00FF;
+	m360.tcn1 = 0;
+	m360.tcn2 = 0;
+	m360.ter1 = 0xFFFF;
+	m360.ter2 = 0xFFFF;
+
+	/*
+	 * Cascade timers 1 and 2
+	 */
+	m360.tgcr |= 0x0080;
+
+	/*
+	 * Configure timers 1 and 2 to a single 32-bit, 1 MHz timer.
+	 * HARDWARE:
+	 *	Change the `25' to match your processor clock
+	 */
+	m360.tmr2 = ((25-1) << 8) | 0x2;
+	m360.tmr1 = 0;
+
+	/*
+	 * Start the timers
+	 */
+	m360.tgcr |=  0x0011;
+}
+
+/*
+ * Return timer value in microsecond units
+ */
+uint32_t
+benchmark_timer_read (void)
+{
+	unsigned short val;
+
+	val = m360.tcn1;
+	return val;
+}
+
+void
+benchmark_timer_disable_subtracting_average_overhead(bool find_flag)
+{
+}
diff --git a/bsps/m68k/genmcf548x/btimer/btimer.c b/bsps/m68k/genmcf548x/btimer/btimer.c
new file mode 100644
index 0000000000..acac6f8f9b
--- /dev/null
+++ b/bsps/m68k/genmcf548x/btimer/btimer.c
@@ -0,0 +1,83 @@
+/*===============================================================*\
+| Project: RTEMS generic mcf548x BSP                              |
++-----------------------------------------------------------------+
+| File: timer.c                                                   |
++-----------------------------------------------------------------+
+| The file contains the diagnostic timer code of generic MCF548x  |
+| BSP.                                                            |
++-----------------------------------------------------------------+
+|                    Copyright (c) 2007                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+|                                                                 |
+| Parts of the code has been derived from the "dBUG source code"  |
+| package Freescale is providing for M548X EVBs. The usage of     |
+| the modified or unmodified code and it's integration into the   |
+| generic mcf548x BSP has been done according to the Freescale    |
+| license terms.                                                  |
+|                                                                 |
+| The Freescale license terms can be reviewed in the file         |
+|                                                                 |
+|    Freescale_license.txt                                        |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+| The generic mcf548x BSP has been developed on the basic         |
+| structures and modules of the av5282 BSP.                       |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.org/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+|   date                      history                        ID   |
+| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
+| 12.11.07                    1.0                            ras  |
+|                                                                 |
+\*===============================================================*/
+
+/*
+ *  Timer Init
+ *
+ *  Use the second slice timer (SLT1) as the diagnostic timer.
+ */
+
+#include <rtems.h>
+#include <rtems/btimer.h>
+#include <bsp.h>
+#include <mcf548x/mcf548x.h>
+
+bool benchmark_timer_find_average_overhead;
+static uint32_t microsecond_timer_value = 0;
+
+void benchmark_timer_initialize(void)
+{
+    MCF548X_SLT_SLTCNT1 = 0xFFFFFFFF;
+    MCF548X_SLT_SCR1 |= (MCF548X_SLT_SCR_TEN | MCF548X_SLT_SCR_RUN);
+}
+
+/*
+ * Return timer value in microsecond units
+ * XLB clock 100 MHz / 1us is equal to 100 counts
+ */
+uint32_t
+benchmark_timer_read(void)
+{
+    microsecond_timer_value = (0xFFFFFFFF - MCF548X_SLT_SCNT1)/100;
+
+    return microsecond_timer_value;
+}
+
+void
+benchmark_timer_disable_subtracting_average_overhead(bool find_flag)
+{
+    benchmark_timer_find_average_overhead = find_flag;
+}
diff --git a/bsps/m68k/mcf52235/btimer/btimer.c b/bsps/m68k/mcf52235/btimer/btimer.c
new file mode 100644
index 0000000000..f9122542c2
--- /dev/null
+++ b/bsps/m68k/mcf52235/btimer/btimer.c
@@ -0,0 +1,39 @@
+/*
+ *  Timer Init
+ *
+ *  Use the last DMA timer (DTIM3) as the diagnostic timer.
+ *
+ *  Author: W. Eric Norum <norume@aps.anl.gov>
+ *
+ *  COPYRIGHT (c) 2005.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <rtems/btimer.h>
+#include <bsp.h>
+
+void benchmark_timer_initialize(void)
+{
+  uint32_t preScaleDivisor = bsp_get_CPU_clock_speed() / 1000000;
+
+  MCF_DTIM3_DTMR = 0;
+  MCF_DTIM3_DTMR = MCF_DTIM_DTMR_PS(preScaleDivisor - 1) |
+    MCF_DTIM_DTMR_CLK_DIV1 | MCF_DTIM_DTMR_RST;
+}
+
+/*
+ * Return timer value in microsecond units
+ */
+benchmark_timer_t benchmark_timer_read(void)
+{
+  return MCF_DTIM3_DTCN;
+}
+
+void benchmark_timer_disable_subtracting_average_overhead(bool find_flag)
+{
+}
diff --git a/bsps/m68k/mcf5225x/btimer/btimer.c b/bsps/m68k/mcf5225x/btimer/btimer.c
new file mode 100644
index 0000000000..ac0ca6d7d0
--- /dev/null
+++ b/bsps/m68k/mcf5225x/btimer/btimer.c
@@ -0,0 +1,39 @@
+/*
+ *  Timer Init
+ *
+ *  Use the last DMA timer (DTIM3) as the diagnostic timer.
+ *
+ *  Author: W. Eric Norum <norume@aps.anl.gov>
+ *
+ *  COPYRIGHT (c) 2005-2010.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <rtems/btimer.h>
+#include <bsp.h>
+
+void benchmark_timer_initialize(void)
+{
+  uint32_t preScaleDivisor = bsp_get_CPU_clock_speed() / 1000000;
+
+  MCF_DTIM3_DTMR = 0;
+  MCF_DTIM3_DTMR = MCF_DTIM_DTMR_PS(preScaleDivisor - 1) |
+    MCF_DTIM_DTMR_CLK_DIV1 | MCF_DTIM_DTMR_RST;
+}
+
+/*
+ * Return timer value in microsecond units
+ */
+benchmark_timer_t benchmark_timer_read(void)
+{
+  return MCF_DTIM3_DTCN;
+}
+
+void benchmark_timer_disable_subtracting_average_overhead(bool find_flag)
+{
+}
diff --git a/bsps/m68k/mcf5235/btimer/btimer.c b/bsps/m68k/mcf5235/btimer/btimer.c
new file mode 100644
index 0000000000..6aae8e99e6
--- /dev/null
+++ b/bsps/m68k/mcf5235/btimer/btimer.c
@@ -0,0 +1,34 @@
+/*
+ *  Timer Init
+ *
+ *  Use the last DMA timer (DTIM3) as the diagnostic timer.
+ */
+
+#include <rtems.h>
+#include <rtems/btimer.h>
+#include <bsp.h>
+
+void
+benchmark_timer_initialize(void)
+{
+    int preScaleDivisor = 0x4A;
+    int div = MCF5235_TIMER_DTMR_CLK_DIV1;
+    MCF5235_TIMER_DTRR3 = 0x2710;
+    MCF5235_TIMER3_DTMR = 0;
+    MCF5235_TIMER3_DTMR = MCF5235_TIMER_DTMR_PS(preScaleDivisor) | div |
+                          MCF5235_TIMER_DTMR_RST;
+}
+
+/*
+ * Return timer value in microsecond units
+ */
+uint32_t
+benchmark_timer_read(void)
+{
+    return MCF5235_TIMER3_DTCN;
+}
+
+void
+benchmark_timer_disable_subtracting_average_overhead(bool find_flag)
+{
+}
diff --git a/bsps/m68k/mcf5329/btimer/btimer.c b/bsps/m68k/mcf5329/btimer/btimer.c
new file mode 100644
index 0000000000..0f762c0a6a
--- /dev/null
+++ b/bsps/m68k/mcf5329/btimer/btimer.c
@@ -0,0 +1,39 @@
+/*
+ *  Timer Init
+ *
+ *  Use the last DMA timer (DTIM3) as the diagnostic timer.
+ *
+ *  Author: W. Eric Norum <norume@aps.anl.gov>
+ *
+ *  COPYRIGHT (c) 2005.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <rtems/btimer.h>
+#include <bsp.h>
+
+void benchmark_timer_initialize(void)
+{
+  uint32_t preScaleDivisor = bsp_get_BUS_clock_speed() / 1000000;
+
+  MCF_DTIM3_DTMR = 0;
+  MCF_DTIM3_DTMR = MCF_DTIM_DTMR_PS(preScaleDivisor - 1) |
+    MCF_DTIM_DTMR_CLK_DIV1 | MCF_DTIM_DTMR_RST;
+}
+
+/*
+ * Return timer value in microsecond units
+ */
+benchmark_timer_t benchmark_timer_read(void)
+{
+  return MCF_DTIM3_DTCN;
+}
+
+void benchmark_timer_disable_subtracting_average_overhead(bool find_flag)
+{
+}
diff --git a/bsps/m68k/mrm332/btimer/btimer.c b/bsps/m68k/mrm332/btimer/btimer.c
new file mode 100644
index 0000000000..8c14f8fe58
--- /dev/null
+++ b/bsps/m68k/mrm332/btimer/btimer.c
@@ -0,0 +1,60 @@
+/*
+ *  COPYRIGHT (c) 1989-1999.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp.h>
+#include <rtems/btimer.h>
+
+bool benchmark_timer_find_average_overhead;
+
+extern rtems_isr Clock_isr(void);
+
+void benchmark_timer_initialize( void )
+{
+}
+
+/*
+ *  The following controls the behavior of benchmark_timer_read().
+ *
+ *  FIND_AVG_OVERHEAD *  instructs the routine to return the "raw" count.
+ *
+ *  AVG_OVEREHAD is the overhead for starting and stopping the timer.  It
+ *  is usually deducted from the number returned.
+ *
+ *  LEAST_VALID is the lowest number this routine should trust.  Numbers
+ *  below this are "noise" and zero is returned.
+ */
+
+#define AVG_OVERHEAD      0  /* It typically takes X.X microseconds */
+                             /* (Y countdowns) to start/stop the timer. */
+                             /* This value is in microseconds. */
+#define LEAST_VALID       1  /* Don't trust a clicks value lower than this */
+
+/*
+ * Return timer value in 1/2-microsecond units
+ */
+benchmark_timer_t benchmark_timer_read( void )
+{
+  uint32_t         total;
+  total = 0;
+
+  if ( benchmark_timer_find_average_overhead == true )
+    return total;          /* in XXX microsecond units */
+
+  if ( total < LEAST_VALID )
+    return 0;            /* below timer resolution */
+
+  return (total - AVG_OVERHEAD);
+}
+
+void benchmark_timer_disable_subtracting_average_overhead(
+  bool find_flag
+)
+{
+  benchmark_timer_find_average_overhead = find_flag;
+}
diff --git a/bsps/m68k/mvme147/btimer/btimer.c b/bsps/m68k/mvme147/btimer/btimer.c
new file mode 100644
index 0000000000..9d48fa7075
--- /dev/null
+++ b/bsps/m68k/mvme147/btimer/btimer.c
@@ -0,0 +1,67 @@
+/*
+ *  COPYRIGHT (c) 1989-1999.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ *
+ *  MVME147 port for TNI - Telecom Bretagne
+ *  by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr)
+ *  May 1996
+ */
+
+#include <rtems/btimer.h>
+#include <bsp.h>
+
+#define TIMER_INT_LEVEL 6
+
+#define COUNTDOWN_VALUE 0
+/* Allows 0.4096 second delay betwin ints */
+/* Each tick is 6.25 us */
+
+int Ttimer_val;
+bool benchmark_timer_find_average_overhead;
+
+rtems_isr timerisr(rtems_vector_number);
+
+void benchmark_timer_initialize(void)
+{
+  (void) set_vector(timerisr, TIMER_1_VECTOR, 0); /* install ISR */
+
+  Ttimer_val = 0;                 /* clear timer ISR count */
+  pcc->timer1_int_control = 0x00; /* Disable T1 Interr. */
+  pcc->timer1_preload = COUNTDOWN_VALUE;
+  /* write countdown preload value */
+  pcc->timer1_control = 0x00; /* load preload value */
+  pcc->timer1_control = 0x07; /* clear T1 overflow counter, enable counter */
+  pcc->timer1_int_control = TIMER_INT_LEVEL|0x08;
+  /* Enable Timer 1 and set its int. level */
+
+}
+
+#define AVG_OVERHEAD      0  /* No need to start/stop the timer to read
+				its value on the MVME147 PCC: reads are not
+				synchronized whith the counter updates*/
+#define LEAST_VALID       10 /* Don't trust a value lower than this */
+
+benchmark_timer_t benchmark_timer_read(void)
+{
+  uint32_t         total;
+  uint16_t         counter_value;
+
+  counter_value = pcc->timer1_count; /* read the counter value */
+
+  total = ((Ttimer_val * 0x10000) + counter_value); /* in 6.25 us units */
+  /* DC note : just look at the assembly generated
+     to see gcc's impressive optimization ! */
+  return total;
+
+}
+
+void benchmark_timer_disable_subtracting_average_overhead(
+  bool find_flag
+)
+{
+  benchmark_timer_find_average_overhead = find_flag;
+}
diff --git a/bsps/m68k/mvme147/btimer/timerisr.S b/bsps/m68k/mvme147/btimer/timerisr.S
new file mode 100644
index 0000000000..418cf64108
--- /dev/null
+++ b/bsps/m68k/mvme147/btimer/timerisr.S
@@ -0,0 +1,26 @@
+/*  timer_isr()
+ *
+ *  This routine provides the ISR for the PCC timer on the MVME147
+ *  board.   The timer is set up to generate an interrupt at maximum
+ *  intervals.
+ *
+ *  MVME147 port for TNI - Telecom Bretagne
+ *  by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr)
+ *  May 1996
+ */
+
+#include <rtems/asm.h>
+
+BEGIN_CODE
+
+.set T1_CONTROL_REGISTER,  0xfffe1018    | timer 1 control register
+
+        PUBLIC (timerisr)
+SYM (timerisr):
+	orb	#0x80, T1_CONTROL_REGISTER | clear T1 int status bit
+        addql   #1, SYM (Ttimer_val)     | increment timer value
+end_timerisr:
+	rte
+
+END_CODE
+END
diff --git a/bsps/m68k/mvme162/btimer/btimer.c b/bsps/m68k/mvme162/btimer/btimer.c
new file mode 100644
index 0000000000..c7dce0475d
--- /dev/null
+++ b/bsps/m68k/mvme162/btimer/btimer.c
@@ -0,0 +1,73 @@
+/*
+ *  This routine initializes the Tick Timer 1 on the MVME162 board.
+ *
+ *  COPYRIGHT (c) 1989-1999.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ *
+ *  Modifications of respective RTEMS file: COPYRIGHT (c) 1994.
+ *  EISCAT Scientific Association. M.Savitski
+ *
+ *  This material is a part of the MVME162 Board Support Package
+ *  for the RTEMS executive. Its licensing policies are those of the
+ *  RTEMS above.
+ */
+
+#include <rtems.h>
+#include <rtems/btimer.h>
+#include <bsp.h>
+
+/* Periodic tick interval */
+#define TICK_INTERVAL         0x10000U
+#define TIMER_INT_LEVEL       6
+
+uint32_t            Ttimer_val;
+bool                benchmark_timer_find_average_overhead;
+
+rtems_isr timerisr(rtems_vector_number vector);
+
+void benchmark_timer_initialize(void)
+{
+  (void) set_vector( timerisr, VBR0 * 0x10 + 0x8, 0 );
+
+  Ttimer_val = 0;                     /* clear timer ISR count */
+  lcsr->vector_base |= MASK_INT;      /* unmask VMEchip2 interrupts */
+  lcsr->intr_clear |= 0x01000000;     /* clear pending interrupt */
+  lcsr->to_ctl = 0xE7;                /* prescaler to 1 MHz (see Appendix A1) */
+  lcsr->timer_cmp_1 = TICK_INTERVAL;
+  lcsr->timer_cnt_1 = 0;              /* clear counter */
+  lcsr->board_ctl |= 7;               /* increment, reset-on-compare, */
+                                      /*   and clear-overflow-cnt */
+
+  lcsr->intr_level[0] |= TIMER_INT_LEVEL; /* set int level */
+  lcsr->intr_ena |= 0x01000000;           /* enable tick timer 1 interrupt */
+}
+
+#define AVG_OVERHEAD      3U    /* It typically takes 3.0 microseconds */
+                                /* (3 countdowns) to start/stop the timer. */
+#define LEAST_VALID       10U   /* Don't trust a value lower than this */
+
+benchmark_timer_t benchmark_timer_read(void)
+{
+  uint32_t            total;
+
+  total = (Ttimer_val * TICK_INTERVAL) + lcsr->timer_cnt_1;
+
+  if ( benchmark_timer_find_average_overhead == true )
+    return total;          /* in one-half microsecond units */
+
+  if ( total < LEAST_VALID )
+    return 0;            /* below timer resolution */
+
+  return (total-AVG_OVERHEAD) >> 1;
+}
+
+void benchmark_timer_disable_subtracting_average_overhead(
+  bool find_flag
+)
+{
+  benchmark_timer_find_average_overhead = find_flag;
+}
diff --git a/bsps/m68k/mvme162/btimer/timerisr.S b/bsps/m68k/mvme162/btimer/timerisr.S
new file mode 100644
index 0000000000..c433d91c59
--- /dev/null
+++ b/bsps/m68k/mvme162/btimer/timerisr.S
@@ -0,0 +1,44 @@
+/*  timer_isr()
+ *
+ *  This routine provides the ISR for the Z8036 timer on the MVME136
+ *  board.   The timer is set up to generate an interrupt at maximum
+ *  intervals.
+ *
+ *  Input parameters:  NONE
+ *
+ *  Output parameters:  NONE
+ *
+ *  COPYRIGHT (c) 1989-1999.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ *
+ *  Modifications of respective RTEMS file: COPYRIGHT (c) 1994.
+ *  EISCAT Scientific Association. M.Savitski
+ *
+ *  This material is a part of the MVME162 Board Support Package
+ *  for the RTEMS executive. Its licensing policies are those of the
+ *  RTEMS above.
+ */
+
+#include <rtems/asm.h>
+
+BEGIN_CODE
+
+.set INTR_CLEAR_REG,      0xfff40074      | interrupt clear register
+.set RELOAD,              0x01000000      | clear tick 1 interrupt
+
+        PUBLIC (Ttimer_val)
+        PUBLIC (timerisr)
+SYM (timerisr):
+        move.l  a0, -(a7)                 | save a0
+        movea.l #INTR_CLEAR_REG, a0       | a0 = addr of cmd status reg
+        ori.l   #RELOAD, (a0)             | reload countdown
+        addq.l  #1, SYM (Ttimer_val)      | increment timer value
+        move.l  (a7)+, a0                 | restore a0
+        rte
+
+END_CODE
+END
diff --git a/bsps/m68k/mvme167/btimer/btimer.c b/bsps/m68k/mvme167/btimer/btimer.c
new file mode 100644
index 0000000000..ed2ce26e51
--- /dev/null
+++ b/bsps/m68k/mvme167/btimer/btimer.c
@@ -0,0 +1,139 @@
+/**
+ * @file
+ *
+ * This file manages the benchmark timer used by the RTEMS Timing Test Suite.
+ * Each measured time period is demarcated by calls to
+ * benchmark_timer_initialize() and benchmark_timer_read().
+ * benchmark_timer_read() usually returns the number of microseconds
+ * since benchmark_timer_initialize() exitted.
+ *
+ * These functions are prototyped in rtems/btimer.h and
+ * must be implemented as part of the BSP.
+ *
+ * This port does not allow the application to select which timer on the
+ * MVME167 to use for the timer, nor does it allow the application to
+ * configure the timer. The timer uses the VMEchip2 Tick Timer #1. This timer
+ * is distinct from the clock, which uses Tick Timer #2 in the VMEchip2.
+ *
+ * All page references are to the MVME166/MVME167/MVME187 Single Board
+ * Computer Programmer's Reference Guide (MVME187PG/D2) with the April 1993
+ *  supplements/addenda (MVME187PG/D2A1).
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-1999.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ *
+ *  Modifications of respective RTEMS file:
+ *  Copyright (c) 1998, National Research Council of Canada
+ */
+
+#include <rtems.h>
+#include <rtems/btimer.h>
+#include <bsp.h>
+
+/* Periodic tick interval */
+#define TICK_INTERVAL         10000UL     /* T1's countdown constant (10 ms) */
+#define TIMER_INT_LEVEL       6           /* T1's interrupt level */
+#define TIMER_VECTOR (VBR0 * 0x10 + 0x8)  /* T1 is vector $X8 (p. 2-71)*/
+
+/* Number of interrupts since timer was re-initialized */
+uint32_t            Ttimer_val;
+
+/*
+ *  Set to true to return raw value. Normally zero. Depends on being allocated
+ *  in the .bss section and on that section being explicitly zeroed at boot
+ *  time.
+ */
+bool benchmark_timer_find_average_overhead;
+
+rtems_isr timerisr(rtems_vector_number);
+
+/*
+ *  This routine initializes the Tick Timer 1 on the MVME167 board.
+ *
+ *  Input parameters:  NONE
+ *
+ *  Output parameters:  NONE
+ *
+ *  NOTE: This routine may not work if the optimizer is enabled for some
+ *        compilers. The multiple writes may be optimized away.
+ *
+ *        It is important that the timer start/stop overhead be
+ *        determined when porting or modifying this code.
+ *
+ *  THE VMECHIP2 PRESCALER REGISTER IS ASSUMED TO BE SET!
+ *  The prescaler is used by all VMEchip2 timers, including the VMEbus grant
+ *  timeout counter, the DMAC time off timer, the DMAC timer on timer, and the
+ *  VMEbus global timeout timer. The prescaler value is normally set by the
+ *  boot ROM to provide a 1 MHz clock to the timers. For a 25 MHz MVME167, the
+ *  prescaler value should be 0xE7 (page 2-63).
+ */
+void benchmark_timer_initialize(void)
+{
+  (void) set_vector( timerisr, TIMER_VECTOR, 0 );
+
+  Ttimer_val = 0;                       /* clear timer ISR count */
+  lcsr->intr_ena &= 0xFEFFFFFF;         /* disable tick timer 1 interrupt */
+  lcsr->intr_clear |= 0x01000000;       /* clear tick timer 1 interrupt */
+  lcsr->intr_level[0] =                 /* set int level */
+        (lcsr->intr_level[0] & 0xFFFFFFF0) | TIMER_INT_LEVEL;
+  lcsr->timer_cmp_1 = TICK_INTERVAL;    /* period in compare register */
+  lcsr->timer_cnt_1 = 0;                /* clear tick timer 1 counter */
+  lcsr->board_ctl |= 7;                 /* start tick timer 1, reset-on-compare, */
+                                        /*   and clear overflow counter */
+
+  lcsr->intr_ena |= 0x01000000;         /* enable tick timer 1 interrupt */
+  lcsr->vector_base |= MASK_INT;        /* unmask VMEchip2 interrupts */
+}
+
+#define AVG_OVERHEAD      3UL   /* It typically takes 3.0 microseconds */
+                                /* (3 countdowns) to start/stop the timer. */
+#define LEAST_VALID       3UL   /* Don't trust a value lower than this */
+
+/*
+ *  This routine reads the Tick Timer 1 on the MVME167 board.
+ *
+ *  Input parameters:  NONE
+ *
+ *  Output parameters:  time in microseconds
+ *
+ *  AVG_OVEREHAD is the overhead for starting and stopping the timer.  It
+ *  is usually deducted from the number returned.
+ *
+ *  LEAST_VALID is the lowest number this routine should trust.  Numbers
+ *  below this are "noise" and zero is returned.
+ */
+benchmark_timer_t benchmark_timer_read(void)
+{
+  uint32_t            total;
+
+  total = (Ttimer_val * TICK_INTERVAL) + lcsr->timer_cnt_1;
+
+  if ( benchmark_timer_find_average_overhead )
+    return total;          /* in one microsecond units */
+
+  if ( total < LEAST_VALID )
+    return 0;            /* below timer resolution */
+
+  return total - AVG_OVERHEAD;
+}
+
+/*
+ *  This routine sets the benchmark_timer_find_average_overhead flag in this
+ *  module.
+ *
+ *  Input parameters:  NONE
+ *
+ *  Output parameters:  time in microseconds
+ */
+void benchmark_timer_disable_subtracting_average_overhead(
+  bool find_flag
+)
+{
+  benchmark_timer_find_average_overhead = find_flag;
+}
diff --git a/bsps/m68k/mvme167/btimer/timerisr.S b/bsps/m68k/mvme167/btimer/timerisr.S
new file mode 100644
index 0000000000..d96f0996a5
--- /dev/null
+++ b/bsps/m68k/mvme167/btimer/timerisr.S
@@ -0,0 +1,50 @@
+/**
+ *  @file
+ *
+ *  This ISR is used to bump a count of interval "overflow" interrupts which
+ *  have occurred since the timer was started. The number of overflows is taken
+ *  into account in the benchmark_timer_read() routine.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2014.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ *
+ *  Modifications of respective RTEMS file: COPYRIGHT (c) 1994.
+ *  Copyright (c) 1998, National Research Council of Canada
+ */
+
+#include <rtems/asm.h>
+
+BEGIN_CODE
+
+.set INTR_CLEAR_REG,    0xfff40074      | interrupt clear register
+.set T1_CNTRL_REG,      0xfff40060      | tick timer 1 control register
+.set CLEAR_INT,         0x01000000      | clear tick 1 interrupt
+.set CLEAR_OVF,         0x00000004      | clear tick 1 overflow counter
+
+        PUBLIC (Ttimer_val)
+        PUBLIC (timerisr)
+SYM (timerisr):
+        move.l  a0, -(a7)               | save a0
+        move.l  d0, -(a7)               | save d0
+        move.w  sr, -(a7)               | save ccr
+        movea.l #INTR_CLEAR_REG, a0     | a0 = addr of intr clr reg
+        ori.l   #CLEAR_INT, (a0)        | clear tick timer 1 intr
+        movea.l #T1_CNTRL_REG, a0       | a0 = addr of t1 cntrl reg
+        move.l  (a0), d0                | read overflow counter
+        lsr.l   #4, d0                  | put overflow in low order bits
+        andi.l  #0xF, d0                | keep only overflow
+        add.l   d0, SYM (Ttimer_val)    | increment timer value
+        ori.l   #CLEAR_OVF, (a0)        | clear overflow counter
+        move.w  (a7)+, sr               | restore ccr
+        move.l  (a7)+, d0               | restore d0
+        move.l  (a7)+, a0               | restore a0
+        rte
+
+END_CODE
+END
diff --git a/bsps/m68k/uC5282/btimer/btimer.c b/bsps/m68k/uC5282/btimer/btimer.c
new file mode 100644
index 0000000000..e01b9c8269
--- /dev/null
+++ b/bsps/m68k/uC5282/btimer/btimer.c
@@ -0,0 +1,47 @@
+/*
+ *  Timer Init
+ *
+ *  Use the last DMA timer (DTIM3) as the diagnostic timer.
+ *
+ *  Author: W. Eric Norum <norume@aps.anl.gov>
+ *
+ *  COPYRIGHT (c) 2005.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <bsp.h>
+#include <rtems/btimer.h>
+
+void
+benchmark_timer_initialize(void)
+{
+    int preScaleDivisor = bsp_get_CPU_clock_speed() / 1000000;
+    int div = MCF5282_TIMER_DTMR_CLK_DIV1;
+
+    if (preScaleDivisor > 256) {
+        preScaleDivisor /= 16;
+        div = MCF5282_TIMER_DTMR_CLK_DIV16;
+    }
+    MCF5282_TIMER3_DTMR = 0;
+    MCF5282_TIMER3_DTMR = MCF5282_TIMER_DTMR_PS(preScaleDivisor - 1) | div |
+                          MCF5282_TIMER_DTMR_RST;
+}
+
+/*
+ * Return timer value in microsecond units
+ */
+uint32_t
+benchmark_timer_read(void)
+{
+    return MCF5282_TIMER3_DTCN;
+}
+
+void
+benchmark_timer_disable_subtracting_average_overhead(bool find_flag)
+{
+}