diff options
author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-01-27 14:37:51 +0100 |
---|---|---|
committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-01-31 12:49:09 +0100 |
commit | 4cf93658eff5cf6b0c02e98a0d1ec33dea5ed85c (patch) | |
tree | 8ce105a37991b79f38da9da31c1cb6ce13ef6beb /bsps/m68k/shared | |
parent | bsps: Move network define to source files (diff) | |
download | rtems-4cf93658eff5cf6b0c02e98a0d1ec33dea5ed85c.tar.bz2 |
bsps: Rework cache manager implementation
The previous cache manager support used a single souce file
(cache_manager.c) which included an implementation header (cache_.h).
This required the use of specialized include paths to find the right
header file. Change this to include a generic implementation header
(cacheimpl.h) in specialized source files.
Use the following directories and files:
* bsps/shared/cache
* bsps/@RTEMS_CPU@/shared/cache
* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c
Update #3285.
Diffstat (limited to 'bsps/m68k/shared')
-rw-r--r-- | bsps/m68k/shared/cache/cache-mcf5223x.c | 38 | ||||
-rw-r--r-- | bsps/m68k/shared/cache/cache-mcf5225x.c | 34 | ||||
-rw-r--r-- | bsps/m68k/shared/cache/cache-mcf5235.c | 101 | ||||
-rw-r--r-- | bsps/m68k/shared/cache/cache-mcf5282.c | 124 | ||||
-rw-r--r-- | bsps/m68k/shared/cache/cache-mcf532x.c | 143 | ||||
-rw-r--r-- | bsps/m68k/shared/cache/cache.c | 3 | ||||
-rw-r--r-- | bsps/m68k/shared/cache/cache.h | 215 |
7 files changed, 658 insertions, 0 deletions
diff --git a/bsps/m68k/shared/cache/cache-mcf5223x.c b/bsps/m68k/shared/cache/cache-mcf5223x.c new file mode 100644 index 0000000000..60b2f7f335 --- /dev/null +++ b/bsps/m68k/shared/cache/cache-mcf5223x.c @@ -0,0 +1,38 @@ +/* + * COPYRIGHT (c) 1989-2008. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include <rtems.h> +#include <mcf5223x/mcf5223x.h> +#include "cache.h" + +/* + * Cannot be frozen + */ +static void _CPU_cache_freeze_data(void) {} +static void _CPU_cache_unfreeze_data(void) {} +static void _CPU_cache_freeze_instruction(void) {} +static void _CPU_cache_unfreeze_instruction(void) {} + +/* + * Write-through data cache -- flushes are unnecessary + */ +static void _CPU_cache_flush_1_data_line(const void *d_addr) {} +static void _CPU_cache_flush_entire_data(void) {} + +static void _CPU_cache_enable_instruction(void) {} +static void _CPU_cache_disable_instruction(void) {} +static void _CPU_cache_invalidate_entire_instruction(void) {} +static void _CPU_cache_invalidate_1_instruction_line(const void *addr) {} + +static void _CPU_cache_enable_data(void) {} +static void _CPU_cache_disable_data(void) {} +static void _CPU_cache_invalidate_entire_data(void) {} +static void _CPU_cache_invalidate_1_data_line(const void *addr) {} + +#include "../../../shared/cache/cacheimpl.h" diff --git a/bsps/m68k/shared/cache/cache-mcf5225x.c b/bsps/m68k/shared/cache/cache-mcf5225x.c new file mode 100644 index 0000000000..10c867ba7f --- /dev/null +++ b/bsps/m68k/shared/cache/cache-mcf5225x.c @@ -0,0 +1,34 @@ +/** + * @file + * + * Cache Management Support Routines for the MCF5225x + */ + +#include <rtems.h> +#include "cache.h" + +/* + * Cannot be frozen + */ +static void _CPU_cache_freeze_data(void) {} +static void _CPU_cache_unfreeze_data(void) {} +static void _CPU_cache_freeze_instruction(void) {} +static void _CPU_cache_unfreeze_instruction(void) {} + +/* + * Write-through data cache -- flushes are unnecessary + */ +static void _CPU_cache_flush_1_data_line(const void *d_addr) {} +static void _CPU_cache_flush_entire_data(void) {} + +static void _CPU_cache_enable_instruction(void) {} +static void _CPU_cache_disable_instruction(void) {} +static void _CPU_cache_invalidate_entire_instruction(void) {} +static void _CPU_cache_invalidate_1_instruction_line(const void *addr) {} + +static void _CPU_cache_enable_data(void) {} +static void _CPU_cache_disable_data(void) {} +static void _CPU_cache_invalidate_entire_data(void) {} +static void _CPU_cache_invalidate_1_data_line(const void *addr) {} + +#include "../../../shared/cache/cacheimpl.h" diff --git a/bsps/m68k/shared/cache/cache-mcf5235.c b/bsps/m68k/shared/cache/cache-mcf5235.c new file mode 100644 index 0000000000..35390b02ef --- /dev/null +++ b/bsps/m68k/shared/cache/cache-mcf5235.c @@ -0,0 +1,101 @@ +/* + * COPYRIGHT (c) 1989-2008. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include <rtems.h> +#include <mcf5235/mcf5235.h> +#include "cache.h" + +/* + * Default value for the cacr is set by the BSP + */ +extern uint32_t cacr_mode; + +/* + * Cannot be frozen + */ +static void _CPU_cache_freeze_data(void) {} +static void _CPU_cache_unfreeze_data(void) {} +static void _CPU_cache_freeze_instruction(void) {} +static void _CPU_cache_unfreeze_instruction(void) {} + +/* + * Write-through data cache -- flushes are unnecessary + */ +static void _CPU_cache_flush_1_data_line(const void *d_addr) {} +static void _CPU_cache_flush_entire_data(void) {} + +static void _CPU_cache_enable_instruction(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + cacr_mode &= ~MCF5XXX_CACR_DIDI; + m68k_set_cacr(cacr_mode); + rtems_interrupt_enable(level); +} + +static void _CPU_cache_disable_instruction(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + cacr_mode |= MCF5XXX_CACR_DIDI; + m68k_set_cacr(cacr_mode); + rtems_interrupt_enable(level); +} + +static void _CPU_cache_invalidate_entire_instruction(void) +{ + m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI); +} + +static void _CPU_cache_invalidate_1_instruction_line(const void *addr) +{ + /* + * Top half of cache is I-space + */ + addr = (void *)((int)addr | 0x400); + __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr)); +} + +static void _CPU_cache_enable_data(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + cacr_mode &= ~MCF5XXX_CACR_DISD; + m68k_set_cacr(cacr_mode); + rtems_interrupt_enable(level); +} + +static void _CPU_cache_disable_data(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + cacr_mode |= MCF5XXX_CACR_DISD; + m68k_set_cacr(cacr_mode); + rtems_interrupt_enable(level); +} + +static void _CPU_cache_invalidate_entire_data(void) +{ + m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); +} + +static void _CPU_cache_invalidate_1_data_line(const void *addr) +{ + /* + * Bottom half of cache is D-space + */ + addr = (void *)((int)addr & ~0x400); + __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr)); +} + +#include "../../../shared/cache/cacheimpl.h" diff --git a/bsps/m68k/shared/cache/cache-mcf5282.c b/bsps/m68k/shared/cache/cache-mcf5282.c new file mode 100644 index 0000000000..259572432a --- /dev/null +++ b/bsps/m68k/shared/cache/cache-mcf5282.c @@ -0,0 +1,124 @@ +/** + * @file + * + * Cache Management Support Routines for the MCF5282 + */ + +#include <rtems.h> +#include <mcf5282/mcf5282.h> /* internal MCF5282 modules */ +#include "cache.h" + +/* + * CPU-space access + */ +#define m68k_set_acr0(_acr0) \ + __asm__ volatile ("movec %0,%%acr0" : : "d" (_acr0)) +#define m68k_set_acr1(_acr1) \ + __asm__ volatile ("movec %0,%%acr1" : : "d" (_acr1)) + +#define NOP __asm__ volatile ("nop"); + +/* + * DEFAULT WHEN mcf5xxx_initialize_cacr not called + * Read/write copy of common cache + * Split I/D cache + * Allow CPUSHL to invalidate a cache line + * Enable buffered writes + * No burst transfers on non-cacheable accesses + * Default cache mode is *disabled* (cache only ACRx areas) + */ +static uint32_t cacr_mode = MCF5XXX_CACR_CENB | + MCF5XXX_CACR_DBWE | + MCF5XXX_CACR_DCM; + +void mcf5xxx_initialize_cacr(uint32_t cacr) +{ + cacr_mode = cacr; + m68k_set_cacr( cacr_mode ); +} + +/* + * Cannot be frozen + */ +static void _CPU_cache_freeze_data(void) {} +static void _CPU_cache_unfreeze_data(void) {} +static void _CPU_cache_freeze_instruction(void) {} +static void _CPU_cache_unfreeze_instruction(void) {} + +/* + * Write-through data cache -- flushes are unnecessary + */ +static void _CPU_cache_flush_1_data_line(const void *d_addr) {} +static void _CPU_cache_flush_entire_data(void) {} + +static void _CPU_cache_enable_instruction(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + cacr_mode &= ~MCF5XXX_CACR_DIDI; + m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI ); + NOP; + rtems_interrupt_enable(level); +} + +static void _CPU_cache_disable_instruction(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + cacr_mode |= MCF5XXX_CACR_DIDI; + m68k_set_cacr(cacr_mode); + rtems_interrupt_enable(level); +} + +static void _CPU_cache_invalidate_entire_instruction(void) +{ + m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI); + NOP; +} + +static void _CPU_cache_invalidate_1_instruction_line(const void *addr) +{ + /* + * Top half of cache is I-space + */ + addr = (void *)((int)addr | 0x400); + __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr)); +} + +static void _CPU_cache_enable_data(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + cacr_mode &= ~MCF5XXX_CACR_DISD; + m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); + rtems_interrupt_enable(level); +} + +static void _CPU_cache_disable_data(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + cacr_mode |= MCF5XXX_CACR_DISD; + m68k_set_cacr(cacr_mode); + rtems_interrupt_enable(level); +} + +static void _CPU_cache_invalidate_entire_data(void) +{ + m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); +} + +static void _CPU_cache_invalidate_1_data_line(const void *addr) +{ + /* + * Bottom half of cache is D-space + */ + addr = (void *)((int)addr & ~0x400); + __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr)); +} + +#include "../../../shared/cache/cacheimpl.h" diff --git a/bsps/m68k/shared/cache/cache-mcf532x.c b/bsps/m68k/shared/cache/cache-mcf532x.c new file mode 100644 index 0000000000..0203afee77 --- /dev/null +++ b/bsps/m68k/shared/cache/cache-mcf532x.c @@ -0,0 +1,143 @@ +/** + * @file + * + * Cache Management Support Routines for the MCF532x + */ + +#include <rtems.h> +#include <mcf532x/mcf532x.h> +#include "cache.h" + +#define m68k_set_cacr(_cacr) \ + __asm__ volatile ("movec %0,%%cacr" : : "d" (_cacr)) + +/* + * Read/write copy of common cache + * Default cache mode is *disabled* (cache only ACRx areas) + * Allow CPUSHL to invalidate a cache line + * Enable store buffer + */ +static uint32_t cacr_mode = MCF_CACR_ESB | + MCF_CACR_DCM(3); + +/* + * Cannot be frozen + */ +static void _CPU_cache_freeze_data(void) +{ +} + +static void _CPU_cache_unfreeze_data(void) +{ +} + +static void _CPU_cache_freeze_instruction(void) +{ +} + +static void _CPU_cache_unfreeze_instruction(void) +{ +} + +static void _CPU_cache_flush_1_data_line(const void *d_addr) +{ + register unsigned long adr = (((unsigned long) d_addr >> 4) & 0xff) << 4; + + __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); + adr += 1; + __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); + adr += 1; + __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); + adr += 1; + __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); +} + +static void _CPU_cache_flush_entire_data(void) +{ + register unsigned long set, adr; + + for(set = 0; set < 256; ++set) { + adr = (set << 4); + __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); + adr += 1; + __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); + adr += 1; + __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); + adr += 1; + __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); + } +} + +static void _CPU_cache_enable_instruction(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + if(!(cacr_mode & MCF_CACR_CENB)) + { + cacr_mode |= MCF_CACR_CENB; + m68k_set_cacr(cacr_mode); + } + rtems_interrupt_enable(level); +} + +static void _CPU_cache_disable_instruction(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + if((cacr_mode & MCF_CACR_CENB)) + { + cacr_mode &= ~MCF_CACR_CENB; + m68k_set_cacr(cacr_mode); + } + rtems_interrupt_enable(level); +} + +static void _CPU_cache_invalidate_entire_instruction(void) +{ + m68k_set_cacr(cacr_mode | MCF_CACR_CINVA); +} + +static void _CPU_cache_invalidate_1_instruction_line(const void *addr) +{ + register unsigned long adr = (((unsigned long) addr >> 4) & 0xff) << 4; + + __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); + adr += 1; + __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); + adr += 1; + __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); + adr += 1; + __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); +} + +static void _CPU_cache_enable_data(void) +{ + /* + * The 532x has a unified data and instruction cache, so we call through + * to enable instruction. + */ + _CPU_cache_enable_instruction(); +} + +static void _CPU_cache_disable_data(void) +{ + /* + * The 532x has a unified data and instruction cache, so we call through + * to disable instruction. + */ + _CPU_cache_disable_instruction(); +} + +static void _CPU_cache_invalidate_entire_data(void) +{ + _CPU_cache_invalidate_entire_instruction(); +} + +static void _CPU_cache_invalidate_1_data_line(const void *addr) +{ + _CPU_cache_invalidate_1_instruction_line(addr); +} + +#include "../../../shared/cache/cacheimpl.h" diff --git a/bsps/m68k/shared/cache/cache.c b/bsps/m68k/shared/cache/cache.c new file mode 100644 index 0000000000..3b5e87ef56 --- /dev/null +++ b/bsps/m68k/shared/cache/cache.c @@ -0,0 +1,3 @@ +#include <rtems.h> +#include "cache.h" +#include "../../../shared/cache/cacheimpl.h" diff --git a/bsps/m68k/shared/cache/cache.h b/bsps/m68k/shared/cache/cache.h new file mode 100644 index 0000000000..2fa78b651d --- /dev/null +++ b/bsps/m68k/shared/cache/cache.h @@ -0,0 +1,215 @@ +/* + * M68K Cache Manager Support + */ + +#if (defined(__mc68020__) && !defined(__mcpu32__)) +# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16 +#elif defined(__mc68030__) +# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16 +# define M68K_DATA_CACHE_ALIGNMENT 16 +#elif ( defined(__mc68040__) || defined (__mc68060__) ) +# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16 +# define M68K_DATA_CACHE_ALIGNMENT 16 +#elif ( defined(__mcf5200__) ) +# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16 +# if ( defined(__mcf528x__) ) +# define M68K_DATA_CACHE_ALIGNMENT 16 +# endif +#elif ( defined(__mcf5300__) ) +# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16 +# define M68K_DATA_CACHE_ALIGNMENT 16 +#elif defined(__mcfv4e__) +# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16 +# define M68K_DATA_CACHE_ALIGNMENT 16 +#endif + +#if defined(M68K_DATA_CACHE_ALIGNMENT) +#define CPU_DATA_CACHE_ALIGNMENT M68K_DATA_CACHE_ALIGNMENT +#endif + +#if defined(M68K_INSTRUCTION_CACHE_ALIGNMENT) +#define CPU_INSTRUCTION_CACHE_ALIGNMENT M68K_INSTRUCTION_CACHE_ALIGNMENT +#endif + +/* + * Since the cacr is common to all mc680x0, provide macros + * for masking values in that register. + */ + +/* + * Used to clear bits in the cacr. + */ +#define _CPU_CACR_AND(mask) \ + { \ + register unsigned long _value = mask; \ + register unsigned long _ctl = 0; \ + __asm__ volatile ( "movec %%cacr, %0; /* read the cacr */ \ + andl %2, %0; /* and with _val */ \ + movec %1, %%cacr" /* write the cacr */ \ + : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" ); \ + } + + +/* + * Used to set bits in the cacr. + */ +#define _CPU_CACR_OR(mask) \ + { \ + register unsigned long _value = mask; \ + register unsigned long _ctl = 0; \ + __asm__ volatile ( "movec %%cacr, %0; /* read the cacr */ \ + orl %2, %0; /* or with _val */ \ + movec %1, %%cacr" /* write the cacr */ \ + : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" ); \ + } + + +/* + * CACHE MANAGER: The following functions are CPU-specific. + * They provide the basic implementation for the rtems_* cache + * management routines. If a given function has no meaning for the CPU, + * it does nothing by default. + */ +#if ( (defined(__mc68020__) && !defined(__mcpu32__)) || defined(__mc68030__) ) + +#if defined(__mc68030__) + +/* Only the mc68030 has a data cache; it is writethrough only. */ + +void _CPU_cache_flush_1_data_line ( const void * d_addr ) {} +void _CPU_cache_flush_entire_data ( void ) {} + +void _CPU_cache_invalidate_1_data_line ( + const void * d_addr ) +{ + void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); + __asm__ volatile ( "movec %0, %%caar" :: "a" (p_address) ); /* write caar */ + _CPU_CACR_OR(0x00000400); +} + +void _CPU_cache_invalidate_entire_data ( void ) +{ + _CPU_CACR_OR( 0x00000800 ); +} + +void _CPU_cache_freeze_data ( void ) +{ + _CPU_CACR_OR( 0x00000200 ); +} + +void _CPU_cache_unfreeze_data ( void ) +{ + _CPU_CACR_AND( 0xFFFFFDFF ); +} + +void _CPU_cache_enable_data ( void ) +{ + _CPU_CACR_OR( 0x00000100 ); +} +void _CPU_cache_disable_data ( void ) +{ + _CPU_CACR_AND( 0xFFFFFEFF ); +} +#endif + + +/* Both the 68020 and 68030 have instruction caches */ + +void _CPU_cache_invalidate_1_instruction_line ( + const void * d_addr ) +{ + void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); + __asm__ volatile ( "movec %0, %%caar" :: "a" (p_address) ); /* write caar */ + _CPU_CACR_OR( 0x00000004 ); +} + +void _CPU_cache_invalidate_entire_instruction ( void ) +{ + _CPU_CACR_OR( 0x00000008 ); +} + +void _CPU_cache_freeze_instruction ( void ) +{ + _CPU_CACR_OR( 0x00000002); +} + +void _CPU_cache_unfreeze_instruction ( void ) +{ + _CPU_CACR_AND( 0xFFFFFFFD ); +} + +void _CPU_cache_enable_instruction ( void ) +{ + _CPU_CACR_OR( 0x00000001 ); +} + +void _CPU_cache_disable_instruction ( void ) +{ + _CPU_CACR_AND( 0xFFFFFFFE ); +} + + +#elif ( defined(__mc68040__) || defined (__mc68060__) ) + +/* Cannot be frozen */ +void _CPU_cache_freeze_data ( void ) {} +void _CPU_cache_unfreeze_data ( void ) {} +void _CPU_cache_freeze_instruction ( void ) {} +void _CPU_cache_unfreeze_instruction ( void ) {} + +void _CPU_cache_flush_1_data_line ( + const void * d_addr ) +{ + void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); + __asm__ volatile ( "cpushl %%dc,(%0)" :: "a" (p_address) ); +} + +void _CPU_cache_invalidate_1_data_line ( + const void * d_addr ) +{ + void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); + __asm__ volatile ( "cinvl %%dc,(%0)" :: "a" (p_address) ); +} + +void _CPU_cache_flush_entire_data ( void ) +{ + asm volatile ( "cpusha %%dc" :: ); +} + +void _CPU_cache_invalidate_entire_data ( void ) +{ + asm volatile ( "cinva %%dc" :: ); +} + +void _CPU_cache_enable_data ( void ) +{ + _CPU_CACR_OR( 0x80000000 ); +} + +void _CPU_cache_disable_data ( void ) +{ + _CPU_CACR_AND( 0x7FFFFFFF ); +} + +void _CPU_cache_invalidate_1_instruction_line ( + const void * i_addr ) +{ + void * p_address = (void *) _CPU_virtual_to_physical( i_addr ); + __asm__ volatile ( "cinvl %%ic,(%0)" :: "a" (p_address) ); +} + +void _CPU_cache_invalidate_entire_instruction ( void ) +{ + asm volatile ( "cinva %%ic" :: ); +} + +void _CPU_cache_enable_instruction ( void ) +{ + _CPU_CACR_OR( 0x00008000 ); +} + +void _CPU_cache_disable_instruction ( void ) +{ + _CPU_CACR_AND( 0xFFFF7FFF ); +} +#endif |