bsps: Move startup files to bsps

Adjust build support files to new directory layout.

This patch is a part of the BSP source reorganization.

Update #3285.

5 files changed, 869 insertions, 0 deletions

diff --git a/bsps/m68k/mcf5206elite/start/bsp_specs b/bsps/m68k/mcf5206elite/start/bsp_specs
new file mode 100644
index 0000000000..87638cc027
--- /dev/null
+++ b/bsps/m68k/mcf5206elite/start/bsp_specs
@@ -0,0 +1,9 @@
+%rename endfile old_endfile
+%rename startfile old_startfile
+
+*startfile:
+%{!qrtems: %(old_startfile)} \
+%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}}
+
+*endfile:
+%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s}
diff --git a/bsps/m68k/mcf5206elite/start/gdbinit b/bsps/m68k/mcf5206elite/start/gdbinit
new file mode 100644
index 0000000000..9954b8cb9a
--- /dev/null
+++ b/bsps/m68k/mcf5206elite/start/gdbinit
@@ -0,0 +1,217 @@
+#
+# GDB Init script for the Coldfire 5206e processor.
+#
+# The main purpose of this script is to perform minimum initialization of
+# processor so code can be loaded. Also, exception handling is performed.
+# 
+# Copyright (C) OKTET Ltd., St.-Petersburg, Russia
+# Author: Victor V. Vengerov <vvv@oktet.ru>
+#
+# This script partially based on gdb scripts written by 
+# Eric Norum, <eric@skatter.usask.ca>
+#
+#
+# The license and distribution terms for this file may be
+# found in the file LICENSE in this distribution or at
+# http://www.rtems.org/license/LICENSE.
+#
+
+define addresses
+
+set $mbar  = 0x10000001
+set $simr  = $mbar - 1 + 0x003
+set $icr1  = $mbar - 1 + 0x014
+set $icr2  = $mbar - 1 + 0x015
+set $icr3  = $mbar - 1 + 0x016
+set $icr4  = $mbar - 1 + 0x017
+set $icr5  = $mbar - 1 + 0x018
+set $icr6  = $mbar - 1 + 0x019
+set $icr7  = $mbar - 1 + 0x01A
+set $icr8  = $mbar - 1 + 0x01B
+set $icr9  = $mbar - 1 + 0x01C
+set $icr10 = $mbar - 1 + 0x01D
+set $icr11 = $mbar - 1 + 0x01E
+set $icr12 = $mbar - 1 + 0x01F
+set $icr13 = $mbar - 1 + 0x020
+set $imr   = $mbar - 1 + 0x036
+set $ipr   = $mbar - 1 + 0x03A
+set $rsr   = $mbar - 1 + 0x040
+set $sypcr = $mbar - 1 + 0x041
+set $swivr = $mbar - 1 + 0x042
+set $swsr  = $mbar - 1 + 0x043
+set $dcrr  = $mbar - 1 + 0x046
+set $dctr  = $mbar - 1 + 0x04A
+set $dcar0 = $mbar - 1 + 0x04C
+set $dcmr0 = $mbar - 1 + 0x050
+set $dccr0 = $mbar - 1 + 0x057
+set $dcar1 = $mbar - 1 + 0x058
+set $dcmr1 = $mbar - 1 + 0x05C
+set $dccr1 = $mbar - 1 + 0x063
+set $csar0 = $mbar - 1 + 0x064
+set $csmr0 = $mbar - 1 + 0x068
+set $cscr0 = $mbar - 1 + 0x06E
+set $csar1 = $mbar - 1 + 0x070
+set $csmr1 = $mbar - 1 + 0x074
+set $cscr1 = $mbar - 1 + 0x07A
+set $csar2 = $mbar - 1 + 0x07C
+set $csmr2 = $mbar - 1 + 0x080
+set $cscr2 = $mbar - 1 + 0x086
+set $csar3 = $mbar - 1 + 0x088
+set $csmr3 = $mbar - 1 + 0x08C
+set $cscr3 = $mbar - 1 + 0x092
+set $csar4 = $mbar - 1 + 0x094
+set $csmr4 = $mbar - 1 + 0x098
+set $cscr4 = $mbar - 1 + 0x09E
+set $csar5 = $mbar - 1 + 0x0A0
+set $csmr5 = $mbar - 1 + 0x0A4
+set $cscr5 = $mbar - 1 + 0x0AA
+set $csar6 = $mbar - 1 + 0x0AC
+set $csmr6 = $mbar - 1 + 0x0B0
+set $cscr6 = $mbar - 1 + 0x0B6
+set $csar7 = $mbar - 1 + 0x0B8
+set $csmr7 = $mbar - 1 + 0x0BC
+set $cscr7 = $mbar - 1 + 0x0C2
+set $dmcr  = $mbar - 1 + 0x0C6
+set $par   = $mbar - 1 + 0x0CA
+set $tmr1  = $mbar - 1 + 0x100
+set $trr1  = $mbar - 1 + 0x104
+set $tcr1  = $mbar - 1 + 0x108
+set $tcn1  = $mbar - 1 + 0x10C
+set $ter1  = $mbar - 1 + 0x111
+set $tmr2  = $mbar - 1 + 0x120
+set $trr2  = $mbar - 1 + 0x124
+set $tcr2  = $mbar - 1 + 0x128
+set $tcn2  = $mbar - 1 + 0x12C
+set $ter2  = $mbar - 1 + 0x131
+
+end
+
+#
+#  Setup CSAR0 for the FLASH ROM.
+#
+
+define setup-cs
+
+set *((short*) $csar0) = 0xffe0
+set *((int*)   $csmr0) = 0x000f0000
+set *((short*) $cscr0) = 0x1da3
+set *((short*) $csar1) = 0x5000
+set *((int*)   $csmr1) = 0x00000000
+set *((short*) $cscr1) = 0x3d43
+set *((short*) $csar2) = 0x3000
+set *((int*)   $csmr2) = 0x000f0000
+set *((short*) $cscr2) = 0x1903
+set *((short*) $csar3) = 0x4000
+set *((int*)   $csmr3) = 0x000f0000
+set *((short*) $cscr3) = 0x0083
+
+end
+
+#
+# Setup the DRAM controller.
+#
+
+define setup-dram
+
+set *((short*) $dcrr)  = 24
+set *((short*) $dctr)  = 0x0000
+set *((short*) $dcar0) = 0x0000
+set *((long*)  $dcmr0) = 0x000e0000
+set *((char*)  $dccr0) = 0x07
+set *((short*) $dcar1) = 0x0000
+set *((long*)  $dcmr1) = 0x00000000
+set *((char*)  $dccr1) = 0x00
+
+end
+
+
+#
+# Wake up the board
+#
+
+define initboard
+
+addresses
+setup-cs
+# setup-dram
+
+end
+
+define ss
+si
+x/i $pc
+end
+
+#
+# Display exception information
+#
+define exception-info
+set $excpc = *(unsigned int *)($sp+4)
+set $excfmt = (*(unsigned int *)$sp >> 28) & 0x0f
+set $excfs = ((*(unsigned int *)$sp >> 24) & 0x0c) | \
+             ((*(unsigned int *)$sp >> 16) & 0x03)
+set $excvec = (*(unsigned int *)$sp >> 18) & 0xff
+set $excsr = *(unsigned int *)$sp & 0xffff
+
+printf "EXCEPTION -- SR:0x%X  PC:0x%X  FRAME:0x%X VECTOR:%d\n", \
+        $excsr, $excpc, $sp, $excvec
+if $excvec == 2
+    printf "Access error exception"
+end
+if $excvec == 3
+    printf "Address error exception"
+end
+if $excvec == 4
+    printf "Illegal instruction exception"
+end
+if $excvec == 8
+    printf "Privelege violation exception"
+end
+if $excvec == 9
+    printf "Trace exception"
+end
+if $excvec == 10
+    printf "Unimplemented LINE-A opcode exception"
+end
+if $excvec == 11
+    printf "Unimplemented LINE-F opcode exception"
+end
+if $excvec == 12
+    printf "Debug interrupt"
+end
+if $excvec == 14
+    printf "Format error exception"
+end
+if $excfs == 0x04
+    printf " on instruction fetch"
+end
+if $excfs == 0x08
+    printf " on operand write"
+end
+if $excfs == 0x09
+    printf " on write to write-protected space"
+end
+if $excfs == 0x0c
+    printf " on operand read"
+end
+printf "\n"
+x/4i $excpc
+set $pc=$excpc
+set $sp=$sp+8
+end
+
+target bdm /dev/bdmcf0
+initboard
+load
+set $pc=start
+set $sp=0x20001ffc
+b bsp_cleanup
+b _stop
+b _unexp_exception
+commands
+silent
+exception-info
+end
+b _unexp_int
+b _reserved_int
+b _spurious_int
diff --git a/bsps/m68k/mcf5206elite/start/init5206e.c b/bsps/m68k/mcf5206elite/start/init5206e.c
new file mode 100644
index 0000000000..a128b81fd7
--- /dev/null
+++ b/bsps/m68k/mcf5206elite/start/init5206e.c
@@ -0,0 +1,229 @@
+/*
+ *  MCF5206e hardware startup routines
+ *
+ *  This is where the real hardware setup is done. A minimal stack
+ *  has been provided by the start.S code. No normal C or RTEMS
+ *  functions can be called from here.
+ *
+ *  This initialization code based on hardware settings of dBUG
+ *  monitor. This must be changed if you like to run it immediately
+ *  after reset.
+ */
+
+/*
+ *  Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
+ *  Author: Victor V. Vengerov <vvv@oktet.ru>
+ *
+ *  Based on work:
+ *  Author:
+ *    David Fiddes, D.J@fiddes.surfaid.org
+ *    http://www.calm.hw.ac.uk/davidf/coldfire/
+ *
+ *  COPYRIGHT (c) 1989-1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <bsp.h>
+#include "mcf5206/mcf5206e.h"
+
+extern void CopyDataClearBSSAndStart(unsigned long ramsize);
+extern void INTERRUPT_VECTOR(void);
+
+#define m68k_set_srambar( _rambar0 ) \
+  __asm__ volatile (  "movec %0,%%rambar0\n\t" \
+                  "nop\n\t" \
+                  : : "d" (_rambar0) )
+
+#define m68k_set_mbar( _mbar ) \
+  __asm__ volatile (  "movec %0,%%mbar\n\t" \
+                  "nop\n\t" \
+                  : : "d" (_mbar) )
+
+#define mcf5206e_enable_cache() \
+  m68k_set_cacr( MCF5206E_CACR_CENB )
+
+#define mcf5206e_disable_cache() \
+  __asm__ volatile (  "nop\n\t"    \
+                  "movec %0,%%cacr\n\t" \
+                  "nop\n\t" \
+                  "movec %0,%%cacr\n\t" \
+                  "nop\n\t" \
+                  : : "d" (MCF5206E_CACR_CINV) )
+
+/*
+ * Initialize MCF5206e on-chip modules
+ */
+void Init5206e(void)
+{
+  /* Set Module Base Address register */
+  m68k_set_mbar((MBAR & MCF5206E_MBAR_BA) | MCF5206E_MBAR_V);
+
+  /* Set System Protection Control Register (SYPCR):
+   * Bus Monitor Enable, Bus Monitor Timing = 1024 clocks,
+   * Software watchdog disabled
+   */
+  *MCF5206E_SYPCR(MBAR) = MCF5206E_SYPCR_BME |
+			  MCF5206E_SYPCR_BMT_1024;
+
+  /* Set Pin Assignment Register (PAR):
+   *     Output Timer 0 (not DREQ) on *TOUT[0] / *DREQ[1]
+   *     Input Timer 0 (not DREQ) on *TIN[0] / *DREQ[0]
+   *     IRQ, not IPL
+   *     UART2 RTS signal (not \RSTO)
+   *     PST/DDATA (not PPIO)
+   *     *WE (not CS/A)
+   */
+  *MCF5206E_PAR(MBAR) = MCF5206E_PAR_PAR9_TOUT |
+			MCF5206E_PAR_PAR8_TIN0 |
+			MCF5206E_PAR_PAR7_UART2 |
+			MCF5206E_PAR_PAR6_IRQ |
+			MCF5206E_PAR_PAR5_PST |
+			MCF5206E_PAR_PAR4_DDATA |
+			MCF5206E_PAR_WE0_WE1_WE2_WE3;
+
+  /* Set SIM Configuration Register (SIMR):
+   * Disable software watchdog timer and bus timeout monitor when
+   * internal freeze signal is asserted.
+   */
+  *MCF5206E_SIMR(MBAR) = MCF5206E_SIMR_FRZ0 | MCF5206E_SIMR_FRZ1;
+
+  /* Set Interrupt Mask Register: Disable all interrupts */
+  *MCF5206E_IMR(MBAR) = 0xFFFF;
+
+  /* Assign Interrupt Control Registers as it is defined in bsp.h */
+  *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL1) =
+			  (BSP_INTLVL_AVEC1 << MCF5206E_ICR_IL_S) |
+			  (BSP_INTPRIO_AVEC1 << MCF5206E_ICR_IP_S) |
+			  MCF5206E_ICR_AVEC;
+  *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL2) =
+			  (BSP_INTLVL_AVEC2 << MCF5206E_ICR_IL_S) |
+			  (BSP_INTPRIO_AVEC2 << MCF5206E_ICR_IP_S) |
+			  MCF5206E_ICR_AVEC;
+  *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL3) =
+			  (BSP_INTLVL_AVEC3 << MCF5206E_ICR_IL_S) |
+			  (BSP_INTPRIO_AVEC3 << MCF5206E_ICR_IP_S) |
+			  MCF5206E_ICR_AVEC;
+  *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL4) =
+			  (BSP_INTLVL_AVEC4 << MCF5206E_ICR_IL_S) |
+			  (BSP_INTPRIO_AVEC4 << MCF5206E_ICR_IP_S) |
+			  MCF5206E_ICR_AVEC;
+  *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL5) =
+			  (BSP_INTLVL_AVEC5 << MCF5206E_ICR_IL_S) |
+			  (BSP_INTPRIO_AVEC5 << MCF5206E_ICR_IP_S) |
+			  MCF5206E_ICR_AVEC;
+  *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL6) =
+			  (BSP_INTLVL_AVEC6 << MCF5206E_ICR_IL_S) |
+			  (BSP_INTPRIO_AVEC6 << MCF5206E_ICR_IP_S) |
+			  MCF5206E_ICR_AVEC;
+  *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL7) =
+			  (BSP_INTLVL_AVEC7 << MCF5206E_ICR_IL_S) |
+			  (BSP_INTPRIO_AVEC7 << MCF5206E_ICR_IP_S) |
+			  MCF5206E_ICR_AVEC;
+  *MCF5206E_ICR(MBAR,MCF5206E_INTR_TIMER_1) =
+			  (BSP_INTLVL_TIMER1 << MCF5206E_ICR_IL_S) |
+			  (BSP_INTPRIO_TIMER1 << MCF5206E_ICR_IP_S) |
+			  MCF5206E_ICR_AVEC;
+  *MCF5206E_ICR(MBAR,MCF5206E_INTR_TIMER_2) =
+			  (BSP_INTLVL_TIMER2 << MCF5206E_ICR_IL_S) |
+			  (BSP_INTPRIO_TIMER2 << MCF5206E_ICR_IP_S) |
+			  MCF5206E_ICR_AVEC;
+  *MCF5206E_ICR(MBAR,MCF5206E_INTR_MBUS) =
+			  (BSP_INTLVL_MBUS << MCF5206E_ICR_IL_S) |
+			  (BSP_INTPRIO_MBUS << MCF5206E_ICR_IP_S) |
+			  MCF5206E_ICR_AVEC;
+  *MCF5206E_ICR(MBAR,MCF5206E_INTR_UART_1) =
+			  (BSP_INTLVL_UART1 << MCF5206E_ICR_IL_S) |
+			  (BSP_INTPRIO_UART1 << MCF5206E_ICR_IP_S);
+  *MCF5206E_ICR(MBAR,MCF5206E_INTR_UART_2) =
+			  (BSP_INTLVL_UART2 << MCF5206E_ICR_IL_S) |
+			  (BSP_INTPRIO_UART2 << MCF5206E_ICR_IP_S);
+  *MCF5206E_ICR(MBAR,MCF5206E_INTR_DMA_0) =
+			  (BSP_INTLVL_DMA0 << MCF5206E_ICR_IL_S) |
+			  (BSP_INTPRIO_DMA0 << MCF5206E_ICR_IP_S) |
+			  MCF5206E_ICR_AVEC;
+  *MCF5206E_ICR(MBAR,MCF5206E_INTR_DMA_1) =
+			  (BSP_INTLVL_DMA1 << MCF5206E_ICR_IL_S) |
+			  (BSP_INTPRIO_DMA1 << MCF5206E_ICR_IP_S) |
+			  MCF5206E_ICR_AVEC;
+
+  /* Software Watchdog timer (not used now) */
+  *MCF5206E_SWIVR(MBAR) = 0x0F; /* Uninitialized interrupt */
+  *MCF5206E_SWSR(MBAR) = MCF5206E_SWSR_KEY1;
+  *MCF5206E_SWSR(MBAR) = MCF5206E_SWSR_KEY2;
+
+  /* Configuring Chip Selects */
+  /* CS2: SRAM memory */
+  *MCF5206E_CSAR(MBAR,2) = BSP_MEM_ADDR_ESRAM >> 16;
+  *MCF5206E_CSMR(MBAR,2) = BSP_MEM_MASK_ESRAM;
+  *MCF5206E_CSCR(MBAR,2) = MCF5206E_CSCR_WS1 |
+			   MCF5206E_CSCR_PS_32 |
+			   MCF5206E_CSCR_AA |
+			   MCF5206E_CSCR_EMAA |
+			   MCF5206E_CSCR_WR |
+			   MCF5206E_CSCR_RD;
+
+  /* CS3: GPIO on eLITE board */
+  *MCF5206E_CSAR(MBAR,3) = BSP_MEM_ADDR_GPIO >> 16;
+  *MCF5206E_CSMR(MBAR,3) = BSP_MEM_MASK_GPIO;
+  *MCF5206E_CSCR(MBAR,3) = MCF5206E_CSCR_WS15 |
+			   MCF5206E_CSCR_PS_16 |
+			   MCF5206E_CSCR_AA |
+			   MCF5206E_CSCR_EMAA |
+			   MCF5206E_CSCR_WR |
+			   MCF5206E_CSCR_RD;
+
+  {
+    uint32_t         *inttab = (uint32_t*)&INTERRUPT_VECTOR;
+    uint32_t         *intvec = (uint32_t*)BSP_MEM_ADDR_ESRAM;
+    register int i;
+
+    for (i = 0; i < 256; i++) {
+      *(intvec++) = *(inttab++);
+    }
+  }
+  m68k_set_vbr(BSP_MEM_ADDR_ESRAM);
+
+  /* CS0: Flash EEPROM */
+  *MCF5206E_CSAR(MBAR,0) = BSP_MEM_ADDR_FLASH >> 16;
+  *MCF5206E_CSCR(MBAR,0) = MCF5206E_CSCR_WS3 |
+			   MCF5206E_CSCR_AA |
+			   MCF5206E_CSCR_PS_16 |
+			   MCF5206E_CSCR_EMAA |
+			   MCF5206E_CSCR_WR |
+			   MCF5206E_CSCR_RD;
+  *MCF5206E_CSMR(MBAR,0) = BSP_MEM_MASK_FLASH;
+
+  /*
+   * Invalidate the cache and disable it
+   */
+  mcf5206e_disable_cache();
+
+  /*
+   * Setup ACRs so that if cache turned on, periphal accesses
+   * are not messed up.  (Non-cacheable, serialized)
+   */
+  m68k_set_acr0 ( 0
+      | MCF5206E_ACR_BASE(BSP_MEM_ADDR_ESRAM)
+      | MCF5206E_ACR_MASK(BSP_MEM_MASK_ESRAM)
+      | MCF5206E_ACR_EN
+      | MCF5206E_ACR_SM_ANY
+  );
+  m68k_set_acr1 ( 0
+      | MCF5206E_ACR_BASE(BSP_MEM_ADDR_FLASH)
+      | MCF5206E_ACR_MASK(BSP_MEM_MASK_FLASH)
+      | MCF5206E_ACR_EN
+      | MCF5206E_ACR_SM_ANY
+  );
+
+  mcf5206e_enable_cache();
+
+  /*
+   * Copy data, clear BSS, switch stacks and call boot_card()
+   */
+  CopyDataClearBSSAndStart (BSP_MEM_SIZE_ESRAM - 0x400);
+}
diff --git a/bsps/m68k/mcf5206elite/start/linkcmds b/bsps/m68k/mcf5206elite/start/linkcmds
new file mode 100644
index 0000000000..817c80e298
--- /dev/null
+++ b/bsps/m68k/mcf5206elite/start/linkcmds
@@ -0,0 +1,207 @@
+/*
+ * This file contains GNU linker directives for an MCF5206eLITE
+ * evaluation board.
+ *
+ * Variations in memory size and allocation can be made by
+ * overriding some values with linker command-line arguments.
+ *
+ * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
+ * Author: Victor V. Vengerov <vvv@oktet.ru>
+ *
+ * This file based on work:
+ * David Fiddes, D.J.Fiddes@hw.ac.uk
+ * http://www.calm.hw.ac.uk/davidf/coldfire/
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+/*
+ * Declare some sizes.
+ * XXX: The assignment of ". += XyzSize;" fails in older gld's if the
+ *      number used there is not constant.  If this happens to you, edit
+ *      the lines marked XXX below to use a constant value.
+ */
+
+/*
+ * Declare system clock frequency.
+ */
+_SYS_CLOCK_FREQUENCY = DEFINED(_SYS_CLOCK_FREQUENCY) ?
+                               _SYS_CLOCK_FREQUENCY : 54000000;
+
+/*
+ * Declare size of heap.
+ * A heap size of 0 means "Use all available memory for the heap".
+ * Initial stack located in on-chip SRAM and not declared there.
+ */
+HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
+RamBase = DEFINED(RamBase) ? RamBase : 0x30000000;
+RamSize = DEFINED(RamSize) ? RamSize : 0x00100000;
+
+/*
+ * Setup the memory map of the MCF5206eLITE evaluation board
+ *
+ * The "rom" section is in USER Flash on the board
+ * The "ram" section is placed in USER RAM starting at 10000h
+ * 
+ */
+MEMORY
+{
+  ram     : ORIGIN = 0x30000000, LENGTH = 0x00100000
+  rom     : ORIGIN = 0xFFE20000, LENGTH = 128k 
+}
+
+MBase = 0x10000000;
+
+ENTRY(start)
+STARTUP(start.o)
+
+/* Interrupt Vector table located at start of external static RAM */
+_VBR = 0x30000000;
+
+SECTIONS
+{
+     
+  /*
+   * Dynamic RAM
+   */
+  ram : {
+          RamBase = .;
+          RamBase = .;
+          /* Reserve space for interrupt table */
+          . += 0x400;
+  } >ram 
+
+  /*
+   * Text, data and bss segments
+   */
+   .text : {
+	   CREATE_OBJECT_SYMBOLS
+	   *(.text*)
+
+	   /*
+	    * C++ constructors/destructors
+	    */
+	   *(.gnu.linkonce.t.*)
+
+	   /*
+	    * Initialization and finalization code.
+	    */
+	   . = ALIGN (16);
+	   PROVIDE (_init = .);
+	   *crti.o(.init)
+	   *(.init)
+	   *crtn.o(.init)
+	   . = ALIGN (16);
+	   PROVIDE (_fini = .);
+	   *crti.o(.fini)
+	   *(.fini)
+	   *crtn.o(.fini)
+
+	   /*
+	    * Special FreeBSD sysctl sections.
+	    */
+	   . = ALIGN (16);
+	   __start_set_sysctl_set = .;
+	   *(set_sysctl_*);
+	   __stop_set_sysctl_set = ABSOLUTE(.);
+	   *(set_domain_*);
+	   *(set_pseudo_*);
+
+	   /*
+	    * C++ constructors/destructors
+	    */
+	   . = ALIGN (16);
+	   *crtbegin.o(.ctors)
+	   *(.ctors)
+	   *crtend.o(.ctors)
+	   *crtbegin.o(.dtors)
+	   *(.dtors)
+	   *crtend.o(.dtors)
+
+	   /*
+	    * Exception frame info
+	    */
+	   . = ALIGN (16);
+	   *(.eh_frame)
+
+	   /*
+	    * Read-only data
+	    */
+	   . = ALIGN (16);
+	   _rodata_start = .;
+	   *(.rodata*)
+           KEEP (*(SORT(.rtemsroset.*)))
+	   *(.gnu.linkonce.r*)
+
+	   . = ALIGN (16);
+           PROVIDE (etext = .);
+
+   } > ram
+
+  .tdata : {
+    _TLS_Data_begin = .;
+    *(.tdata .tdata.* .gnu.linkonce.td.*)
+    _TLS_Data_end = .;
+  } >ram
+
+  .tbss : {
+    _TLS_BSS_begin = .;
+    *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+    _TLS_BSS_end = .;
+  } >ram
+
+  _TLS_Data_size = _TLS_Data_end - _TLS_Data_begin;
+  _TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin;
+  _TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin;
+  _TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin;
+  _TLS_Size = _TLS_BSS_end - _TLS_Data_begin;
+  _TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
+
+   .data BLOCK (0x4) : {
+           copy_start = .;
+           *(.shdata)
+           . = ALIGN (0x10);
+           *(.data*)
+           KEEP (*(SORT(.rtemsrwset.*)))
+           . = ALIGN (0x10);
+           *(.gcc_exc)
+           *(.gcc_except_table*)
+	   *(.jcr)
+           . = ALIGN (0x10);
+           *(.gnu.linkonce.d*)
+           . = ALIGN (0x10);
+           _edata = .;
+	   copy_end = .;
+   } > ram
+
+  .bss BLOCK (0x4) :
+  {
+    clear_start = . ;
+    *(.shbss)
+    *(.dynbss)
+    *(.bss* .gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(0x10);
+    _end = .;
+    
+    clear_end = .;
+
+    WorkAreaBase = .;
+    WorkAreaBase = .;
+
+  } > ram
+
+  .stab 0 (NOLOAD) :
+  {
+    *(.stab)
+  }
+
+  .stabstr 0 (NOLOAD) :
+  {
+    *(.stabstr)
+  }
+ 
+}
diff --git a/bsps/m68k/mcf5206elite/start/linkcmds.flash b/bsps/m68k/mcf5206elite/start/linkcmds.flash
new file mode 100644
index 0000000000..8d429ab209
--- /dev/null
+++ b/bsps/m68k/mcf5206elite/start/linkcmds.flash
@@ -0,0 +1,207 @@
+/*
+ * This file contains GNU linker directives for an MCF5206eLITE
+ * evaluation board.
+ *
+ * Variations in memory size and allocation can be made by
+ * overriding some values with linker command-line arguments.
+ *
+ * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
+ * Author: Victor V. Vengerov <vvv@oktet.ru>
+ *
+ * This file based on work:
+ * David Fiddes, D.J.Fiddes@hw.ac.uk
+ * http://www.calm.hw.ac.uk/davidf/coldfire/
+ * 
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+/*
+ * Declare some sizes.
+ * XXX: The assignment of ". += XyzSize;" fails in older gld's if the
+ *      number used there is not constant.  If this happens to you, edit
+ *      the lines marked XXX below to use a constant value.
+ */
+/*
+ * Declare size of heap.
+ * A heap size of 0 means "Use all available memory for the heap".
+ * Initial stack located in on-chip SRAM and not declared there.
+ */
+HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
+
+/*
+ * Declare system clock frequency.
+ */
+_SYS_CLOCK_FREQUENCY = DEFINED(_SYS_CLOCK_FREQUENCY) ? _SYS_CLOCK_FREQUENCY : 54000000;
+
+/*
+ * Setup the memory map of the MCF5206eLITE evaluation board
+ *
+ * The "rom" section is in USER Flash on the board
+ * The "ram" section is placed in USER RAM starting at 10000h
+ * 
+ */
+MEMORY
+{
+  ram     : ORIGIN = 0x30000000, LENGTH = 0x00100000
+  rom     : ORIGIN = 0xFFE00000, LENGTH = 0x00100000
+}
+
+MBase = 0x10000000;
+
+ENTRY(start)
+STARTUP(start.o)
+
+/* Interrupt Vector table located at start of external static RAM */
+_VBR = 0x30000000;
+
+SECTIONS
+{
+  /*
+   * Flash ROM
+   */
+  rom : {
+        _RomBase = .;
+  } >rom
+
+  /*
+   * Dynamic RAM
+   */
+  ram : {
+          RamBase = .;
+          RamBase = .;
+  } >ram 
+
+  /*
+   * Text, data and bss segments
+   */
+   .text : AT(0x30020000) {
+           CREATE_OBJECT_SYMBOLS
+           *(.text*)
+
+	   /*
+	    * C++ constructors/destructors
+	    */
+	   *(.gnu.linkonce.t.*)
+
+	   /*
+	    * Initialization and finalization code.
+	    */
+           . = ALIGN (16);
+	   PROVIDE (_init = .);
+	   *crti.o(.init)
+	   *(.init)
+	   *crtn.o(.init)
+           . = ALIGN (16);
+	   PROVIDE (_fini = .);
+	   *crti.o(.fini)
+	   *(.fini)
+	   *crtn.o(.fini)
+
+	   /*
+	    * Special FreeBSD sysctl sections.
+	    */
+	   . = ALIGN (16);
+	   __start_set_sysctl_set = .;
+	   *(set_sysctl_*);
+	   __stop_set_sysctl_set = ABSOLUTE(.);
+	   *(set_domain_*);
+	   *(set_pseudo_*);
+
+	   /*
+	    * C++ constructors/destructors
+	    */
+	   . = ALIGN (16);
+	   *crtbegin.o(.ctors)
+	   *(.ctors)
+	   *crtend.o(.ctors)
+	   *crtbegin.o(.dtors)
+	   *(.dtors)
+	   *crtend.o(.dtors)
+
+	   /*
+	    * Exception frame info
+	    */
+	   . = ALIGN (16);
+	   *(.eh_frame)
+
+	   /*
+	    * Read-only data
+	    */
+	   . = ALIGN (16);
+	   _rodata_start = . ;
+	   *(.rodata)
+           KEEP (*(SORT(.rtemsroset.*)))
+	   *(.gnu.linkonce.r*)
+
+           . = ALIGN (16);
+           PROVIDE (etext = .);
+
+   } >rom
+
+  .tdata : {
+    _TLS_Data_begin = .;
+    *(.tdata .tdata.* .gnu.linkonce.td.*)
+    _TLS_Data_end = .;
+  } >rom
+
+  .tbss : {
+    _TLS_BSS_begin = .;
+    *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+    _TLS_BSS_end = .;
+  } >rom
+
+  _TLS_Data_size = _TLS_Data_end - _TLS_Data_begin;
+  _TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin;
+  _TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin;
+  _TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin;
+  _TLS_Size = _TLS_BSS_end - _TLS_Data_begin;
+  _TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
+
+   .data 0x30000400 : AT(LOADADDR(.text) + SIZEOF(.text)) {
+           copy_start = .;
+           . = ALIGN (0x10);
+           *(.shdata)
+           . = ALIGN (0x10);
+           *(.data)
+           KEEP (*(SORT(.rtemsrwset.*)))
+           . = ALIGN (0x10);
+           *(.gcc_exc)
+           *(.gcc_except_table*)
+           . = ALIGN (0x10);
+           *(.gnu.linkonce.d*)
+           . = ALIGN (0x10);
+           _edata = .;
+	   copy_end = .;
+   } >ram
+
+  .bss BLOCK (0x4) :
+  {
+    clear_start = . ;
+    *(.shbss)
+    *(.dynbss)
+    *(.bss* .gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(0x10);
+    _end = .;
+    
+    clear_end = .;
+
+    WorkAreaBase = .;
+    WorkAreaBase = .;
+
+  } > ram
+
+  .stab 0 (NOLOAD) :
+  {
+    *(.stab)
+  }
+
+  .stabstr 0 (NOLOAD) :
+  {
+    *(.stabstr)
+  }
+ 
+}