bsps: Move startup files to bsps

Adjust build support files to new directory layout.

This patch is a part of the BSP source reorganization.

Update #3285.

6 files changed, 787 insertions, 0 deletions

diff --git a/bsps/m68k/genmcf548x/start/bsp_specs b/bsps/m68k/genmcf548x/start/bsp_specs
new file mode 100644
index 0000000000..3a20757667
--- /dev/null
+++ b/bsps/m68k/genmcf548x/start/bsp_specs
@@ -0,0 +1,10 @@
+%rename endfile old_endfile
+%rename startfile old_startfile
+
+*startfile:
+%{!qrtems: %(old_startfile)} \
+%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}}
+
+*endfile:
+%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s}
+
diff --git a/bsps/m68k/genmcf548x/start/bspstart.c b/bsps/m68k/genmcf548x/start/bspstart.c
new file mode 100644
index 0000000000..6c1da2a738
--- /dev/null
+++ b/bsps/m68k/genmcf548x/start/bspstart.c
@@ -0,0 +1,206 @@
+/*===============================================================*\
+| Project: RTEMS generic mcf548x BSP                              |
++-----------------------------------------------------------------+
+| File: bspstart.c                                                |
++-----------------------------------------------------------------+
+| The file contains the startup code of generic MCF548x BSP       |
++-----------------------------------------------------------------+
+|                    Copyright (c) 2007                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+|                                                                 |
+| Parts of the code has been derived from the "dBUG source code"  |
+| package Freescale is providing for M548X EVBs. The usage of     |
+| the modified or unmodified code and it's integration into the   |
+| generic mcf548x BSP has been done according to the Freescale    |
+| license terms.                                                  |
+|                                                                 |
+| The Freescale license terms can be reviewed in the file         |
+|                                                                 |
+|    Freescale_license.txt                                        |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+| The generic mcf548x BSP has been developed on the basic         |
+| structures and modules of the av5282 BSP.                       |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.org/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+|   date                      history                        ID   |
+| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
+| 12.11.07                    1.0                            ras  |
+|                                                                 |
+\*===============================================================*/
+
+#include <bsp.h>
+#include <bsp/bootcard.h>
+
+extern uint32_t _CPU_cacr_shadow;
+
+/*
+* These labels (!) are defined in the linker command file or when the linker is
+* invoked.
+* NOTE: The information (size) is the address of the object, not the object
+* itself.
+*/
+
+extern char _SdramBase[];
+extern char _BootFlashBase[];
+extern char _CodeFlashBase[];
+extern char _SdramSize[];
+extern char _BootFlashSize[];
+extern char _CodeFlashSize[];
+extern char _TopRamReserved [];
+extern char WorkAreaBase [];
+
+/*
+ * CPU-space access
+ */
+#define m68k_set_acr2(_acr2) __asm__ volatile ("movec %0,#0x0005" : : "d" (_acr2))
+#define m68k_set_acr3(_acr3) __asm__ volatile ("movec %0,#0x0007" : : "d" (_acr3))
+
+/*
+ * Set initial CACR mode, mainly enables branch/instruction/data cache.  The
+ * FPU must be switched on in the BSP startup code since the
+ * _Thread_Start_multitasking() will restore the floating-point context of the
+ * initialization task if necessary.
+ */
+static const uint32_t BSP_CACR_INIT = MCF548X_CACR_DEC /* enable data cache */
+  | MCF548X_CACR_BEC /* enable branch cache */
+  | MCF548X_CACR_IEC /* enable instruction cache */
+  | MCF548X_CACR_DDCM(DCACHE_ON_WRIGHTTHROUGH)
+      /* set data cache mode to write-through */
+  | MCF548X_CACR_DESB /* enable data store buffer */
+  | MCF548X_CACR_DDSP /* data access only in supv. mode */
+  | MCF548X_CACR_IDSP; /* instr. access only in supv. mode */
+
+/*
+ * CACR maintenance functions
+ */
+
+void bsp_cacr_set_flags( uint32_t flags)
+{
+  rtems_interrupt_level level;
+
+  rtems_interrupt_disable( level);
+  _CPU_cacr_shadow |= flags;
+  m68k_set_cacr( _CPU_cacr_shadow);
+  rtems_interrupt_enable( level);
+}
+
+void bsp_cacr_set_self_clear_flags( uint32_t flags)
+{
+  rtems_interrupt_level level;
+  uint32_t cacr = 0;
+
+  rtems_interrupt_disable( level);
+  cacr = _CPU_cacr_shadow | flags;
+  m68k_set_cacr( cacr);
+  rtems_interrupt_enable( level);
+}
+
+void bsp_cacr_clear_flags( uint32_t flags)
+{
+  rtems_interrupt_level level;
+
+  rtems_interrupt_disable( level);
+  _CPU_cacr_shadow &= ~flags;
+  m68k_set_cacr( _CPU_cacr_shadow);
+  rtems_interrupt_enable( level);
+}
+
+/*
+ * Coldfire acr and mmu settings
+ */
+ static void acr_mmu_mapping(void)
+   {
+
+  /*
+   * Cache disabled for internal register area (256 kB).
+   * Choose the smallest maskable size of 1MB.
+   */
+  m68k_set_acr0(MCF548X_ACR_BA((uint32_t)(__MBAR))                           |
+                MCF548X_ACR_ADMSK_AMM((uint32_t)(0xFFFFF))                   |
+                MCF548X_ACR_E                                                |
+                MCF548X_ACR_SP               /* supervisor protection */     |
+                MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
+                MCF548X_ACR_CM(CM_OFF_PRECISE));
+
+#ifdef M5484FIREENGINE
+
+
+  /*
+   * Cache enabled for entire SDRAM (64 MB)
+   */
+  m68k_set_acr1(MCF548X_ACR_BA((uint32_t)(_SdramBase))                       |
+                MCF548X_ACR_ADMSK_AMM((uint32_t)(_SdramSize - 1))            |
+                MCF548X_ACR_E                                                |
+                MCF548X_ACR_SP               /* supervisor protection */     |
+                MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
+                MCF548X_ACR_CM(CM_ON_WRIGHTTHROUGH));
+
+  /*
+   * Cache enabled for entire boot flash (2 MB)
+   */
+  m68k_set_acr2(MCF548X_ACR_BA((uint32_t)(_BootFlashBase))                   |
+                MCF548X_ACR_ADMSK_AMM((uint32_t)(_BootFlashSize - 1))        |
+                MCF548X_ACR_E                                                |
+                MCF548X_ACR_SP               /* supervisor protection */     |
+                MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
+                MCF548X_ACR_CM(CM_ON_COPYBACK));
+
+  /*
+   * Cache enabled for entire code flash (16 MB)
+   */
+  m68k_set_acr3(MCF548X_ACR_BA((uint32_t)(_CodeFlashBase))                   |
+                MCF548X_ACR_ADMSK_AMM((uint32_t)(_CodeFlashSize - 1))        |
+                MCF548X_ACR_E                                                |
+                MCF548X_ACR_SP               /* supervisor protection */     |
+                MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
+                MCF548X_ACR_CM(CM_ON_COPYBACK));
+#endif
+
+   }
+
+/*
+ *  bsp_start
+ *
+ *  This routine does the bulk of the system initialisation.
+ */
+void bsp_start( void )
+{
+  /* Initialize CACR shadow register */
+  _CPU_cacr_shadow = BSP_CACR_INIT;
+
+  /*
+   * Load the shadow variable of CACR with initial mode and write it to the
+   * CACR.  Interrupts are still disabled, so there is no need for surrounding
+   * rtems_interrupt_enable() / rtems_interrupt_disable().
+   */
+  m68k_set_cacr( _CPU_cacr_shadow);
+
+  /*
+   * do mapping of acr's and/or mmu
+   */
+  acr_mmu_mapping();
+}
+
+
+/*
+ * Get the XLB clock speed
+ */
+uint32_t get_CPU_clock_speed(void)
+{
+    return (uint32_t)BSP_CPU_CLOCK_SPEED;
+}
diff --git a/bsps/m68k/genmcf548x/start/init548x.c b/bsps/m68k/genmcf548x/start/init548x.c
new file mode 100644
index 0000000000..c83c061f31
--- /dev/null
+++ b/bsps/m68k/genmcf548x/start/init548x.c
@@ -0,0 +1,321 @@
+/*===============================================================*\
+| Project: RTEMS generic mcf548x BSP                              |
++-----------------------------------------------------------------+
+| File: init548x.c                                                |
++-----------------------------------------------------------------+
+| The file contains the c part of MCF548x init code               |
++-----------------------------------------------------------------+
+|                    Copyright (c) 2007                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+|                                                                 |
+| Parts of the code has been derived from the "dBUG source code"  |
+| package Freescale is providing for M548X EVBs. The usage of     |
+| the modified or unmodified code and it's integration into the   |
+| generic mcf548x BSP has been done according to the Freescale    |
+| license terms.                                                  |
+|                                                                 |
+| The Freescale license terms can be reviewed in the file         |
+|                                                                 |
+|    Freescale_license.txt                                        |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+| The generic mcf548x BSP has been developed on the basic         |
+| structures and modules of the av5282 BSP.                       |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.org/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+|   date                      history                        ID   |
+| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
+| 12.11.07                    1.0                            ras  |
+|                                                                 |
+\*===============================================================*/
+
+#include <bsp.h>
+
+#include <string.h>
+
+#include <bsp/linker-symbols.h>
+
+#if defined(HAS_LOW_LEVEL_INIT)
+#define SYSTEM_PERIOD			10  	/* system bus period in ns */
+
+/* SDRAM Timing Parameters */
+#define SDRAM_TWR		    	2  		/* in clocks */
+#define SDRAM_CASL		    	2.5 	/* in clocks */
+#define SDRAM_TRCD		    	20		/* in ns */
+#define SDRAM_TRP		    	20		/* in ns */
+#define SDRAM_TRFC		    	75		/* in ns */
+#define SDRAM_TREFI		    	7800	/* in ns */
+#endif /* defined(HAS_LOW_LEVEL_INIT) */
+
+extern uint8_t _DataRom[];
+extern uint8_t _DataRam[];
+extern uint8_t _DataEnd[];
+extern uint8_t _BssStart[];
+extern uint8_t _BssEnd[];
+extern uint8_t _BootFlashBase[];
+extern uint8_t _CodeFlashBase[];
+extern uint8_t RamBase[];
+
+void gpio_init(void);
+void fbcs_init(void);
+void sdramc_init(void);
+void mcf548x_init(void);
+
+
+void mcf548x_init(void)
+{
+    size_t i;
+
+#if defined(HAS_LOW_LEVEL_INIT)
+    /* set XLB arbiter timeouts */
+    MCF548X_XLB_ADRTO = 0x00000100;
+    MCF548X_XLB_DATTO = 0x00000100;
+    MCF548X_XLB_BUSTO = 0x00000100;
+#endif
+
+    gpio_init();
+#if defined(HAS_LOW_LEVEL_INIT)
+    fbcs_init();
+    sdramc_init();
+#endif /* defined(HAS_LOW_LEVEL_INIT) */
+
+    /* Copy the vector table to RAM if necessary */
+    if (bsp_vector0_size == bsp_vector1_size) {
+      memcpy(bsp_vector1_begin, bsp_vector0_begin, (size_t) bsp_vector1_size);
+      m68k_set_vbr((uint32_t)bsp_vector1_begin);
+    }
+
+    /* Move initialized data from ROM to RAM. */
+    if (bsp_section_data_begin != bsp_section_data_load_begin) {
+      memcpy(
+        bsp_section_data_begin,
+        bsp_section_data_load_begin,
+        (size_t) bsp_section_data_size
+      );
+    }
+
+    /* Zero uninitialized data */
+    memset(bsp_section_bss_begin, 0, (size_t) bsp_section_bss_size);
+
+    for (i = 8; i < RTEMS_ARRAY_SIZE(mcf548x_intc_icr_init_values); ++i) {
+      volatile uint8_t *icr = &MCF548X_INTC_ICR0;
+
+      icr[i] = mcf548x_intc_icr_init_values[i];
+    }
+}
+/********************************************************************/
+#if defined(HAS_LOW_LEVEL_INIT)
+void
+fbcs_init (void)
+{
+#ifdef M5484FIREENGINE
+
+volatile uint32_t cscr, clk_ratio, fb_period, ws;
+
+/* boot flash already valid ? */
+if(!(MCF548X_FBCS_CSMR0 & MCF548X_FBCS_CSMR_V))
+  {
+
+    /*
+     * Boot Flash
+     */
+    MCF548X_FBCS_CSAR0 = MCF548X_FBCS_CSAR_BA((uint32_t)(_BootFlashBase));
+
+    cscr = (0
+            | MCF548X_FBCS_CSCR_ASET(1)
+            | MCF548X_FBCS_CSCR_WRAH(0)
+            | MCF548X_FBCS_CSCR_RDAH(0)
+            | MCF548X_FBCS_CSCR_AA
+            | MCF548X_FBCS_CSCR_PS_16);
+
+    /*
+     * Determine the necessary wait states based on the defined system
+     * period (XLB clock period) and the CLKIN to XLB ratio.
+     * The boot flash has a max access time of 110ns.
+     */
+    clk_ratio = (MCF548X_PCI_PCIGSCR >> 24) & 0x7;
+    fb_period = SYSTEM_PERIOD * clk_ratio;
+    ws = 110 / fb_period;
+
+    MCF548X_FBCS_CSCR0 = cscr | MCF548X_FBCS_CSCR_WS(ws);
+    MCF548X_FBCS_CSMR0 = (0
+                          | MCF548X_FBCS_CSMR_BAM_2M
+                          | MCF548X_FBCS_CSMR_V);
+
+  }
+
+/* code flash already valid ? */
+if(!(MCF548X_FBCS_CSMR1 & MCF548X_FBCS_CSMR_V))
+  {
+
+    /*
+     * Code Flash
+     */
+    MCF548X_FBCS_CSAR1 = MCF548X_FBCS_CSAR_BA((uint32_t)(_CodeFlashBase));
+
+    /*
+     * Determine the necessary wait states based on the defined system
+     * period (XLB clock period) and the CLKIN to XLB ratio.
+     * The user/code flash has a max access time of 120ns.
+     */
+    ws = 120 / fb_period;
+    MCF548X_FBCS_CSCR1 = cscr | MCF548X_FBCS_CSCR_WS(ws);
+    MCF548X_FBCS_CSMR1 = (0
+                          | MCF548X_FBCS_CSMR_BAM_16M
+                          | MCF548X_FBCS_CSMR_V);
+    }
+
+#endif
+}
+#endif /* defined(HAS_LOW_LEVEL_INIT) */
+
+/********************************************************************/
+#if defined(HAS_LOW_LEVEL_INIT)
+void
+sdramc_init (void)
+{
+
+	/*
+	 * Check to see if the SDRAM has already been initialized
+	 * by a run control tool
+	 */
+	if (!(MCF548X_SDRAMC_SDCR & MCF548X_SDRAMC_SDCR_REF))
+	{
+		/*
+         * Basic configuration and initialization
+         */
+		MCF548X_SDRAMC_SDRAMDS = (0
+			| MCF548X_SDRAMC_SDRAMDS_SB_E(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA)
+			| MCF548X_SDRAMC_SDRAMDS_SB_C(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA)
+			| MCF548X_SDRAMC_SDRAMDS_SB_A(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA)
+			| MCF548X_SDRAMC_SDRAMDS_SB_S(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA)
+			| MCF548X_SDRAMC_SDRAMDS_SB_D(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA)
+            );
+        MCF548X_SDRAMC_CS0CFG = (0
+            | MCF548X_SDRAMC_CSnCFG_CSBA((uint32_t)(RamBase))
+            | MCF548X_SDRAMC_CSnCFG_CSSZ(MCF548X_SDRAMC_CSnCFG_CSSZ_64MBYTE)
+            );
+        MCF548X_SDRAMC_SDCFG1 = (0
+			| MCF548X_SDRAMC_SDCFG1_SRD2RW(7)
+			| MCF548X_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1)
+			| MCF548X_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL*2) + 2))
+			| MCF548X_SDRAMC_SDCFG1_ACT2RW((int)(((SDRAM_TRCD/SYSTEM_PERIOD) - 1) + 0.5))
+			| MCF548X_SDRAMC_SDCFG1_PRE2ACT((int)(((SDRAM_TRP/SYSTEM_PERIOD) - 1) + 0.5))
+			| MCF548X_SDRAMC_SDCFG1_REF2ACT((int)(((SDRAM_TRFC/SYSTEM_PERIOD) - 1) + 0.5))
+			| MCF548X_SDRAMC_SDCFG1_WTLAT(3)
+            );
+		MCF548X_SDRAMC_SDCFG2 = (0
+			| MCF548X_SDRAMC_SDCFG2_BRD2PRE(4)
+			| MCF548X_SDRAMC_SDCFG2_BWT2RW(6)
+			| MCF548X_SDRAMC_SDCFG2_BRD2WT(7)
+			| MCF548X_SDRAMC_SDCFG2_BL(7)
+            );
+
+		/*
+         * Precharge and enable write to SDMR
+         */
+        MCF548X_SDRAMC_SDCR = (0
+			| MCF548X_SDRAMC_SDCR_MODE_EN
+			| MCF548X_SDRAMC_SDCR_CKE
+			| MCF548X_SDRAMC_SDCR_DDR
+			| MCF548X_SDRAMC_SDCR_MUX(1)
+			| MCF548X_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI/(SYSTEM_PERIOD*64)) - 1) + 0.5))
+			| MCF548X_SDRAMC_SDCR_IPALL
+            );
+
+		/*
+         * Write extended mode register
+         */
+		MCF548X_SDRAMC_SDMR = (0
+			| MCF548X_SDRAMC_SDMR_BNKAD_LEMR
+			| MCF548X_SDRAMC_SDMR_AD(0x0)
+			| MCF548X_SDRAMC_SDMR_CMD
+            );
+
+		/*
+         * Write mode register and reset DLL
+         */
+		MCF548X_SDRAMC_SDMR = (0
+			| MCF548X_SDRAMC_SDMR_BNKAD_LMR
+			| MCF548X_SDRAMC_SDMR_AD(0x163)
+			| MCF548X_SDRAMC_SDMR_CMD
+            );
+
+		/*
+         * Execute a PALL command
+         */
+		MCF548X_SDRAMC_SDCR |=MCF548X_SDRAMC_SDCR_IPALL;
+
+		/*
+         * Perform two REF cycles
+         */
+		MCF548X_SDRAMC_SDCR |= MCF548X_SDRAMC_SDCR_IREF;
+		MCF548X_SDRAMC_SDCR |= MCF548X_SDRAMC_SDCR_IREF;
+
+		/*
+         * Write mode register and clear reset DLL
+         */
+		MCF548X_SDRAMC_SDMR = (0
+			| MCF548X_SDRAMC_SDMR_BNKAD_LMR
+			| MCF548X_SDRAMC_SDMR_AD(0x063)
+			| MCF548X_SDRAMC_SDMR_CMD
+            );
+
+		/*
+         * Enable auto refresh and lock SDMR
+         */
+		MCF548X_SDRAMC_SDCR &= ~MCF548X_SDRAMC_SDCR_MODE_EN;
+        MCF548X_SDRAMC_SDCR |= (0
+			| MCF548X_SDRAMC_SDCR_REF
+			| MCF548X_SDRAMC_SDCR_DQS_OE(0xF)
+            );
+    }
+
+}
+#endif /* defined(HAS_LOW_LEVEL_INIT) */
+
+/********************************************************************/
+void
+gpio_init(void)
+{
+
+#ifdef M5484FIREENGINE
+
+    /*
+     * Enable Ethernet signals so that, if a cable is plugged into
+     * the ports, the lines won't be floating and potentially cause
+     * erroneous transmissions
+     */
+    MCF548X_GPIO_PAR_FECI2CIRQ = (0
+
+        | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC
+        | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO
+        | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MII
+        | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E17
+
+        | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MDC
+        | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO
+        | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MII
+        | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E07
+        );
+
+#endif
+    /* 
+     * make sure the "edge port" has all interrupts disabled
+     */
+    MCF548X_EPORT_EPIER = 0;
+}
diff --git a/bsps/m68k/genmcf548x/start/linkcmds.COBRA5475 b/bsps/m68k/genmcf548x/start/linkcmds.COBRA5475
new file mode 100644
index 0000000000..52bca8d018
--- /dev/null
+++ b/bsps/m68k/genmcf548x/start/linkcmds.COBRA5475
@@ -0,0 +1,82 @@
+/*===============================================================*\
+| Project: RTEMS generic mcf548x BSP                              |
++-----------------------------------------------------------------+
+| File: linkcmds.COBRA5475                                        |
++-----------------------------------------------------------------+
+| The file contains the linker directives for the generic MCF548x |
+| BSP to be used with an COBRA5475 board to load and execute      |
+| code in the RAM.                                                |
++-----------------------------------------------------------------+
+|                    Copyright (c) 2007                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+|                                                                 |
+| Parts of the code has been derived from the "dBUG source code"  |
+| package Freescale is providing for M548X EVBs. The usage of     |
+| the modified or unmodified code and it's integration into the   |
+| generic mcf548x BSP has been done according to the Freescale    |
+| license terms.                                                  |
+|                                                                 |
+| The Freescale license terms can be reviewed in the file         |
+|                                                                 |
+|    Freescale_license.txt                                        |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+| The generic mcf548x BSP has been developed on the basic         |
+| structures and modules of the av5282 BSP.                       |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.org/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+|   date                      history                        ID   |
+| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
+| 12.11.07                    1.0                            ras  |
+| 15.10.09                    1.1, adapted to COBRA5475      doe  |
+|                                                                 |
+\*===============================================================*/
+
+/* 
+ * Location and size of on-chip devices
+ */
+_SdramBase      = DEFINED(_SdramBase)      ? _SdramBase   : 0xf0000000;
+_SdramSize      = DEFINED(_SdramSize)      ? _SdramSize   : (128 * 1024*1024);
+_SysSramBase    = DEFINED(_SysSramBase)    ? _SysSramBase : __MBAR + 0x00010000;
+_SysSramSize    = DEFINED(_SysSramSize)    ? _SysSramSize : (32 * 1024);
+_McdapiBase     = DEFINED(_McdapiBase)     ? _McdapiBase  : _SysSramBase;                 
+_McdapiSize     = DEFINED(_McdapiSize)     ? _McdapiSize  : (12 * 1024);                  
+_CoreSramBase0  = DEFINED(_CoreSramBase0)  ? _CoreSramBase0 : 0xFF000000;
+_CoreSramBase1  = DEFINED(_CoreSramBase1)  ? _CoreSramBase1 : 0xFF001000;
+_CoreSramSize0  = DEFINED(_CoreSramSize0)  ? _CoreSramSize0 : (4 * 1024);
+_CoreSramSize1  = DEFINED(_CoreSramSize1)  ? _CoreSramSize1 : (4 * 1024);
+_BootFlashBase  = DEFINED(_BootFlashBase)  ? _BootFlashBase : 0xFC000000;
+_BootFlashSize  = DEFINED(_BootFlashSize)  ? _BootFlashSize : (32 * 1024*1024);
+
+bsp_initstack_size = DEFINED(StackSize)    ? StackSize  : 0x800;  /* 2 kB   */
+
+_VBR            = DEFINED(_VBR)            ? _VBR       : _SdramBase;
+
+__MBAR          = DEFINED(__MBAR)          ? __MBAR     : 0xFE000000;
+
+MEMORY
+{
+    sdram      : ORIGIN = 0xF0000000, LENGTH = 128M
+    boot_flash : ORIGIN = 0xFC000000, LENGTH = 32M
+}
+
+REGION_ALIAS ("REGION_TEXT", sdram);
+REGION_ALIAS ("REGION_TEXT_LOAD", sdram);
+REGION_ALIAS ("REGION_DATA", sdram);
+REGION_ALIAS ("REGION_DATA_LOAD", sdram);
+
+INCLUDE linkcmds.base
diff --git a/bsps/m68k/genmcf548x/start/linkcmds.m5484FireEngine b/bsps/m68k/genmcf548x/start/linkcmds.m5484FireEngine
new file mode 100644
index 0000000000..be746af7ff
--- /dev/null
+++ b/bsps/m68k/genmcf548x/start/linkcmds.m5484FireEngine
@@ -0,0 +1,84 @@
+/*===============================================================*\
+| Project: RTEMS generic mcf548x BSP                              |
++-----------------------------------------------------------------+
+| File: linkcmd                                                   |
++-----------------------------------------------------------------+
+| The file contains the linker directives for the generic MCF548x |
+| BSP to be used with an m5484FireEngine EVB to load and execute  |
+| code in the RAM.                                                |
++-----------------------------------------------------------------+
+|                    Copyright (c) 2007                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+|                                                                 |
+| Parts of the code has been derived from the "dBUG source code"  |
+| package Freescale is providing for M548X EVBs. The usage of     |
+| the modified or unmodified code and it's integration into the   |
+| generic mcf548x BSP has been done according to the Freescale    |
+| license terms.                                                  |
+|                                                                 |
+| The Freescale license terms can be reviewed in the file         |
+|                                                                 |
+|    Freescale_license.txt                                        |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+| The generic mcf548x BSP has been developed on the basic         |
+| structures and modules of the av5282 BSP.                       |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.org/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+|   date                      history                        ID   |
+| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
+| 12.11.07                    1.0                            ras  |
+|                                                                 |
+\*===============================================================*/
+
+/* 
+ * Location and size of on-chip devices
+ */
+_SdramBase      = DEFINED(_SdramBase)      ? _SdramBase   : 0x00000000;
+_SdramSize      = DEFINED(_SdramSize)      ? _SdramSize   : (64 * 1024*1024);
+_SysSramBase    = DEFINED(_SysSramBase)    ? _SysSramBase : __MBAR + 0x00010000;
+_SysSramSize    = DEFINED(_SysSramSize)    ? _SysSramSize : (32 * 1024);
+_McdapiBase     = DEFINED(_McdapiBase)     ? _McdapiBase  : _SysSramBase;                 
+_McdapiSize     = DEFINED(_McdapiSize)     ? _McdapiSize  : (12 * 1024);                  
+_CoreSramBase0  = DEFINED(_CoreSramBase0)  ? _CoreSramBase0 : 0x20000000;
+_CoreSramBase1  = DEFINED(_CoreSramBase1)  ? _CoreSramBase1 : 0x20001000;
+_CoreSramSize0  = DEFINED(_CoreSramSize0)  ? _CoreSramSize0 : (4 * 1024);
+_CoreSramSize1  = DEFINED(_CoreSramSize1)  ? _CoreSramSize1 : (4 * 1024);
+_BootFlashBase  = DEFINED(_BootFlashBase)  ? _BootFlashBase : 0xFF800000;
+_BootFlashSize  = DEFINED(_BootFlashSize)  ? _BootFlashSize : (2 * 1024*1024);
+_CodeFlashBase  = DEFINED(_CodeFlashBase)  ? _CodeFlashBase : 0xE0000000;
+_CodeFlashSize  = DEFINED(_CodeFlashSize)  ? _CodeFlashSize : (16 * 1024*1024);
+
+bsp_initstack_size = DEFINED(StackSize)    ? StackSize  : 0x800;  /* 2 kB   */
+
+_VBR            = DEFINED(_VBR)            ? _VBR       : _SdramBase;
+
+__MBAR          = DEFINED(__MBAR)          ? __MBAR     : 0x10000000;
+
+MEMORY
+{
+    sdram      : ORIGIN = 0x00000000, LENGTH = 64M
+    code_flash : ORIGIN = 0xE0000000, LENGTH = 16M
+    boot_flash : ORIGIN = 0xFF800000, LENGTH = 2M
+}
+
+REGION_ALIAS ("REGION_TEXT", sdram);
+REGION_ALIAS ("REGION_TEXT_LOAD", sdram);
+REGION_ALIAS ("REGION_DATA", sdram);
+REGION_ALIAS ("REGION_DATA_LOAD", sdram);
+
+INCLUDE linkcmds.base
diff --git a/bsps/m68k/genmcf548x/start/linkcmds.m5484FireEngine.flash b/bsps/m68k/genmcf548x/start/linkcmds.m5484FireEngine.flash
new file mode 100644
index 0000000000..4db960f111
--- /dev/null
+++ b/bsps/m68k/genmcf548x/start/linkcmds.m5484FireEngine.flash
@@ -0,0 +1,84 @@
+/*===============================================================*\
+| Project: RTEMS generic mcf548x BSP                              |
++-----------------------------------------------------------------+
+| File: linkcmd.m5484FireEngine.flash                             |
++-----------------------------------------------------------------+
+| The file contains the linker directives for the generic MCF548x |
+| BSP to be used with an m5484FireEngine EVB to load and execute  |
+| code in the boot FLASH.                                         |
++-----------------------------------------------------------------+
+|                    Copyright (c) 2007                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+|                                                                 |
+| Parts of the code has been derived from the "dBUG source code"  |
+| package Freescale is providing for M548X EVBs. The usage of     |
+| the modified or unmodified code and it's integration into the   |
+| generic mcf548x BSP has been done according to the Freescale    |
+| license terms.                                                  |
+|                                                                 |
+| The Freescale license terms can be reviewed in the file         |
+|                                                                 |
+|    Freescale_license.txt                                        |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+| The generic mcf548x BSP has been developed on the basic         |
+| structures and modules of the av5282 BSP.                       |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.org/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+|   date                      history                        ID   |
+| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
+| 12.11.07                    1.0                            ras  |
+|                                                                 |
+\*===============================================================*/
+
+/* 
+ * Location and size of on-chip devices
+ */
+_SdramBase     = DEFINED(_SdramBase)      ? _SdramBase     : 0x00000000;
+_SdramSize     = DEFINED(_SdramSize)      ? _SdramSize     : (64 * 1024 * 1024);
+_SysSramBase   = DEFINED(_SysSramBase)    ? _SysSramBase   : __MBAR + 0x00010000;
+_SysSramSize   = DEFINED(_SysSramSize)    ? _SysSramSize   : (32 * 1024);
+_McdapiBase    = DEFINED(_McdapiBase)     ? _McdapiBase    : _SysSramBase;                 
+_McdapiSize    = DEFINED(_McdapiSize)     ? _McdapiSize    : (12 * 1024);                  
+_CoreSramBase0 = DEFINED(_CoreSramBase0)  ? _CoreSramBase0 : 0x20000000;
+_CoreSramBase1 = DEFINED(_CoreSramBase1)  ? _CoreSramBase1 : 0x20001000;
+_CoreSramSize0 = DEFINED(_CoreSramSize0)  ? _CoreSramSize0 : (4 * 1024);
+_CoreSramSize1 = DEFINED(_CoreSramSize1)  ? _CoreSramSize1 : (4 * 1024);
+_BootFlashBase = DEFINED(_BootFlashBase)  ? _BootFlashBase : 0xFF800000;
+_BootFlashSize = DEFINED(_BootFlashSize)  ? _BootFlashSize : (2 * 1024 * 1024);
+_CodeFlashBase = DEFINED(_CodeFlashBase)  ? _CodeFlashBase : 0xE0000000;
+_CodeFlashSize = DEFINED(_CodeFlashSize)  ? _CodeFlashSize : (16 * 1024 * 1024);
+
+bsp_initstack_size = DEFINED(StackSize)    ? StackSize  : 0x800;  /* 2 kB   */
+
+_VBR            = DEFINED(_VBR)            ? _VBR       : _SdramBase;
+
+__MBAR          = DEFINED(__MBAR)          ? __MBAR     : 0x10000000;
+
+MEMORY
+{
+    sdram      : ORIGIN = 0x00000000, LENGTH = 64M
+    code_flash : ORIGIN = 0xE0000000, LENGTH = 16M
+    boot_flash : ORIGIN = 0xFF800000, LENGTH = 2M
+}
+
+REGION_ALIAS ("REGION_TEXT", boot_flash);
+REGION_ALIAS ("REGION_TEXT_LOAD", boot_flash);
+REGION_ALIAS ("REGION_DATA", sdram);
+REGION_ALIAS ("REGION_DATA_LOAD", boot_flash);
+
+INCLUDE linkcmds.base