bsps: Import Xilinx GQSPI driver

This adds Xilinx's driver for the Xilinx GQSPI controller embedded in
the ZynqMP SoC. Within that device alone, it is possible to access this
peripheral from MicroBlaze, ARMv7, and ARMv8 cores. The imported files
are and should be able to remain unmodified. Import information is kept
in bsps/shared/dev/spi/VERSION.

4 files changed, 2030 insertions, 0 deletions

diff --git a/bsps/include/dev/spi/xqspipsu.h b/bsps/include/dev/spi/xqspipsu.h
new file mode 100644
index 0000000000..7d9b662464
--- /dev/null
+++ b/bsps/include/dev/spi/xqspipsu.h
@@ -0,0 +1,567 @@
+/******************************************************************************
+* Copyright (C) 2014 - 2022 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+
+/*****************************************************************************/
+/**
+ *
+ * @file xqspipsu.h
+ * @addtogroup Overview
+ * @{
+ * @details
+ *
+ * This section explains the implementation the functions required to use the
+ * QSPIPSU hardware to perform a transfer. These are accessible to the user
+ * via xqspipsu.h.
+ *
+ * Generic QSPI interface allows for communication to any QSPI slave device.
+ * GQSPI contains a GENFIFO into which the bus transfers required are to be
+ * pushed with appropriate configuration. The controller provides TX and RX
+ * FIFO's and a DMA to be used for RX transfers. The controller executes each
+ * GENFIFO entry noting the configuration and places data on the bus as required
+ *
+ * The different options in GENFIFO are as follows:
+ * - IMM_DATA : Can be one byte of data to be transmitted, number of clocks or
+ *              number of bytes in transfer.
+ * - DATA_XFER : Indicates that data/clocks need to be transmitted or received.
+ * - EXPONENT : e when 2^e bytes are involved in transfer.
+ * - SPI_MODE : SPI/Dual SPI/Quad SPI
+ * - CS : Lower or Upper CS or Both
+ * - Bus : Lower or Upper Bus or Both
+ * - TX : When selected, controller transmits data in IMM or fetches number of
+ *        bytes mentioned form TX FIFO. If not selected, dummies are pumped.
+ * - RX : When selected, controller receives and fills the RX FIFO/allows RX DMA
+ *        of requested number of bytes. If not selected, RX data is discarded.
+ * - Stripe : Byte stripe over lower and upper bus or not.
+ * - Poll : Polls response to match for to a set value (used along with POLL_CFG
+ *          registers) and then proceeds to next GENFIFO entry.
+ *          This feature is not currently used in the driver.
+ *
+ * GENFIFO has manual and auto start options.
+ * All DMA requests need a 4-byte aligned destination address buffer and
+ * size of transfer should also be a multiple of 4.
+ * This driver supports DMA RX and IO RX.
+ *
+ * <b>Initialization & Configuration</b>
+ *
+ * This driver uses the GQSPI controller with RX DMA. It supports both
+ * interrupt and polled transfers. Manual start of GENFIFO is used.
+ * XQspiPsu_CfgInitialize() initializes the instance variables.
+ * Additional setting can be done using SetOptions/ClearOptions functions
+ * and SelectSlave function.
+ *
+ * <b>Transfer</b>
+ *
+ * Polled or Interrupt transfers can be done. The transfer function needs the
+ * message(s) to be transmitted in the form of an array of type XQspiPsu_Msg.
+ * This is supposed to contain the byte count and any TX/RX buffers as required.
+ * Flags can be used indicate further information such as whether the message
+ * should be striped. The transfer functions form and write GENFIFO entries,
+ * check the status of the transfer and report back to the application
+ * when done.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who Date     Changes
+ * ----- --- -------- -----------------------------------------------.
+ * 1.0   hk  08/21/14 First release
+ *       sk  03/13/15 Added IO mode support.
+ *       hk  03/18/15 Switch to I/O mode before clearing RX FIFO.
+ *                    Clear and disable DMA interrupts/status in abort.
+ *                    Use DMA DONE bit instead of BUSY as recommended.
+ *       sk  04/24/15 Modified the code according to MISRAC-2012.
+ *       sk  06/17/15 Removed NULL checks for Rx/Tx buffers. As
+ *                    writing/reading from 0x0 location is permitted.
+ * 1.1   sk  04/12/16 Added debug message prints.
+ * 1.2 nsk 07/01/16 Added LQSPI support
+ *                  Modified XQspiPsu_Select() macro in xqspipsu.h
+ *                  Added XQspiPsu_GetLqspiConfigReg() in xqspipsu.h
+ *                  Added required macros in xqspipsu_hw.h
+ *                  Modified XQspiPsu_SetOptions() to support
+ *                  LQSPI options and updated OptionsTable in
+ *                  xqspipsu_options.c
+ *       rk  07/15/16 Added support for TapDelays at different frequencies.
+ *     nsk 08/05/16 Added example support PollData and PollTimeout
+ *                  Added  XQSPIPSU_MSG_FLAG_POLL macro in xqspipsu.h
+ *                  Added XQspiPsu_Create_PollConfigData and
+ *                  XQspiPsu_PollData() functions in xqspipsu.c
+ * 1.3 nsk 09/16/16 Update PollData and Polltimeout support for dual parallel
+ *                  configuration. Updated XQspiPsu_PollData() and
+ *                  XQspiPsu_Create_PollConfigData() functions in xqspipsu.c
+ *                    and also modified the polldata example
+ *       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+ *                    generation.
+ *       ms  04/05/17 Modified Comment lines in functions of qspipsu
+ *                    examples to recognize it as documentation block
+ *                    and modified filename tag to include them in
+ *                    doxygen examples.
+ * 1.4 tjs 05/26/17 Added support for accessing upper DDR (0x800000000)
+ *                  while booting images from QSPI
+ * 1.5 tjs 08/08/17 Added index.html file for importing examples
+ *                  from system.mss
+ * 1.5 nsk 08/14/17 Added CCI support
+ * 1.5 tjs 09/14/17 Modified the checks for 4 byte addressing and commands.
+ * 1.6 tjs 10/16/17 Flow for accessing flash is made similar to u-boot
+ *                  and linux For CR-984966
+ * 1.6   tjs 11/02/17 Resolved the compilation errors for ICCARM. CR-988625
+ * 1.7   tjs 11/16/17 Removed the unsupported 4 Byte write and sector erase
+ *                    commands.
+ * 1.7 tjs 12/01/17 Added support for MT25QL02G Flash from Micron. CR-990642
+ * 1.7 tjs 12/19/17 Added support for S25FL064L from Spansion. CR-990724
+ * 1.7 tjs 01/11/18 Added support for MX66L1G45G flash from Macronix CR-992367
+ * 1.7 tjs 01/16/18 Removed the check for DMA MSB to be written. (CR#992560)
+ * 1.7 tjs 01/17/18 Added support to toggle the WP pin of flash. (PR#2448)
+ *                    Added XQspiPsu_SetWP() in xqspipsu_options.c
+ *                    Added XQspiPsu_WriteProtectToggle() in xqspipsu.c and
+ *                    also added write protect example.
+ * 1.7 tjs 03/14/18 Added support in EL1 NS mode (CR#974882)
+ * 1.7 tjs 26/03/18 In dual parallel mode enable both CS when issuing Write
+ *                     enable command. CR-998478
+ * 1.8 tjs 05/02/18 Added support for IS25LP064 and IS25WP064.
+ * 1.8 tjs 06/26/18 Added an example for accessing 64bit dma within
+ *                  32 bit application. CR#1004701
+ * 1.8 tjs 06/26/18 Removed checkpatch warnings
+ * 1.8 tjs 07/09/19 Fixed cppcheck, doxygen and gcc warnings.
+ * 1.8 tjs 07/18/18 Setup64BRxDma() should be called only if the RxAddress is
+ *                  greater than 32 bit address space. (CR#1006862)
+ * 1.8 tjs 07/18/18 Added support for the low density ISSI flash parts.
+ * 1.8 tjs 09/06/18 Fixed the code in XQspiPsu_GenFifoEntryData() for data
+ *                  transfer length up to 255 for reducing the extra loop.
+ * 1.9 tjs 11/22/17 Added the check for A72 and R5 processors (CR-987075)
+ * 1.9 tjs 04/17/18 Updated register addresses as per the latest revision
+ *		    of versal (CR#999610)
+ * 1.9  aru 01/17/19 Fixed the violations for  MISRAC-2012
+ *                  in safety mode .Done changes such as added U suffix,
+ *                  Declared pointer param as const.
+ * 1.9  nsk 02/01/19 Clear DMA_DST_ADDR_MSB register on 32bit machine, if the
+ *		     address is of only 32bit (CR#1020031)
+ * 1.9  nsk 02/01/19 Added QSPI idling support
+ *
+ * 1.9 akm 03/08/19 Set recommended clock and data tap delay values for 40MHZ,
+ *                  100MHZ and 150MHZ frequencies(CR#1023187)
+ * 1.9  nsk 03/27/19 Update 64bit dma support
+ *		     (CR#1018102).
+ * 1.9  akm 04/03/19 Fixed data alignment warnings on IAR compiler.
+ * 1.9  akm 04/03/19 Fixed compilation error in XQspiPsu_LqspiRead()
+ *                     function on IAR compiler.
+ * 1.10 sk  08/20/19 Fixed issues in poll timeout feature.
+ * 1.10 akm 08/22/19 Set recommended tap delay values for 37.5MHZ, 100MHZ and
+ *		     150MHZ frequencies in Versal.
+ * 1.10 akm 09/05/19 Added Multi Die Erase and Muti Die Read support.
+ * 1.11 akm 11/07/19 Removed LQSPI register access in Versal.
+ * 1.11	akm 11/15/19 Fixed Coverity deadcode warning in
+ * 				XQspipsu_Calculate_Tapdelay().
+ * 1.11 akm 02/19/20 Added XQspiPsu_StartDmaTransfer() and XQspiPsu_CheckDmaDone()
+ * 		     APIs for non-blocking transfer.
+ * 1.11 sd  01/02/20 Added clocking support
+ * 1.11 akm 03/09/20 Reorganize the source code, enable qspi controller and
+ *		     interrupts in XQspiPsu_CfgInitialize() API.
+ * 1.11 akm 03/26/20 Fixed issue by updating XQspiPsu_CfgInitialize to return
+ *		     XST_DEVICE_IS_STARTED instead of asserting, when the
+ *		     instance is already configured(CR#1058525).
+ * 1.12	akm 09/02/20 Updated the Makefile to support parallel make execution.
+ * 1.13 akm 01/04/21 Fix MISRA-C violations.
+ * 1.13 sne 04/23/21 Fixed doxygen warnings.
+ * 1.14 akm 06/24/21 Allow enough time for the controller to reset the FIFOs.
+ * 1.14 akm 08/12/21 Perform Dcache invalidate at the end of the DMA transfer.
+ *
+ * </pre>
+ *
+ ******************************************************************************/
+
+#ifndef XQSPIPSU_H_		/**< prevent circular inclusions */
+#define XQSPIPSU_H_		/**< by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspipsu_hw.h"
+#include "xil_cache.h"
+#include "xil_mem.h"
+#if defined  (XCLOCKING)
+#include "xil_clocking.h"
+#endif
+
+/**************************** Type Definitions *******************************/
+/**
+ * The handler data type allows the user to define a callback function to
+ * handle the asynchronous processing for the QSPIPSU device.  The application
+ * using this driver is expected to define a handler of this type to support
+ * interrupt driven mode.  The handler executes in an interrupt context, so
+ * only minimal processing should be performed.
+ *
+ * @param	CallBackRef is the callback reference passed in by the upper
+ *		layer when setting the callback functions, and passed back to
+ *		the upper layer when the callback is invoked. Its type is
+ *		not important to the driver, so it is a void pointer.
+ * @param	StatusEvent holds one or more status events that have occurred.
+ *		See the XQspiPsu_SetStatusHandler() for details on the status
+ *		events that can be passed in the callback.
+ * @param	ByteCount indicates how many bytes of data were successfully
+ *		transferred.  This may be less than the number of bytes
+ *		requested if the status event indicates an error.
+ */
+typedef void (*XQspiPsu_StatusHandler) (const void *CallBackRef, u32 StatusEvent,
+					u32 ByteCount);
+
+/**
+ * This typedef contains configuration information for a flash message.
+ */
+typedef struct {
+	u8 *TxBfrPtr;	/**< Tx Buffer pointer */
+	u8 *RxBfrPtr;	/**< Rx Buffer pointer */
+	u32 ByteCount;	/**< Byte Count */
+	u32 BusWidth;	/**< Bus Width */
+	u32 Flags;	/**< Flags */
+	u8 PollData;	/**< Poll Data */
+	u32 PollTimeout;/**< Poll Timeout */
+	u8 PollStatusCmd; /**< Poll Status command */
+	u8 PollBusMask;	  /**< Poll Bus mask */
+	u64 RxAddr64bit;  /**< 64 bit Rx address */
+	u8 Xfer64bit;	  /**< 64 bit Tx address */
+} XQspiPsu_Msg;
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID  of device */
+	UINTPTR BaseAddress;	/**< Base address of the device */
+	u32 InputClockHz;	/**< Input clock frequency */
+	u8  ConnectionMode;	/**< Single, Stacked and Parallel mode */
+	u8  BusWidth;		/**< Bus width available on board */
+	u8 IsCacheCoherent;	/**< Describes whether Cache Coherent or not */
+#if defined  (XCLOCKING)
+	u32 RefClk;		/**< Input clocks */
+#endif
+} XQspiPsu_Config;
+
+/**
+ * The XQspiPsu driver instance data. The user is required to allocate a
+ * variable of this type for every QSPIPSU device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XQspiPsu_Config Config;	 /**< Configuration structure */
+	u32 IsReady;		 /**< Device is initialized and ready */
+
+	u8 *SendBufferPtr;	 /**< Buffer to send (state) */
+	u8 *RecvBufferPtr;	 /**< Buffer to receive (state) */
+	u64 RecvBuffer;		 /**< Buffer Address to receive (state) */
+	u8 *GenFifoBufferPtr;	 /**< Gen FIFO entries */
+	s32 TxBytes;	 /**< Number of bytes to transfer (state) */
+	s32 RxBytes;	 /**< Number of bytes left to transfer(state) */
+	s32 GenFifoEntries;	 /**< Number of Gen FIFO entries remaining */
+	u32 IsBusy;		 /**< A transfer is in progress (state) */
+	u32 ReadMode;		 /**< DMA or IO mode */
+	u32 GenFifoCS;		/**< Gen FIFO chip selection */
+	u32 GenFifoBus;		/**< Gen FIFO bus */
+	s32 NumMsg;		/**< Number of messages */
+	s32 MsgCnt;		/**< Message Count */
+	s32 IsUnaligned;	/**< Unaligned information */
+	u8 IsManualstart;	/**< Manual start information */
+	XQspiPsu_Msg *Msg;	/**< Message */
+	XQspiPsu_StatusHandler StatusHandler;	/**< Status Handler */
+	void *StatusRef;	/**< Callback reference for status handler */
+} XQspiPsu;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**
+ * Definitions for Intel, STM, Winbond and Spansion Serial Flash Device
+ * geometry.
+ */
+#define BYTES256_PER_PAGE	256U		/**< 256 Bytes per Page */
+#define BYTES512_PER_PAGE	512U		/**< 512 Bytes per Page */
+#define BYTES1024_PER_PAGE	1024U		/**< 1024 Bytes per Page */
+#define PAGES16_PER_SECTOR	16U		/**< 16 Pages per Sector */
+#define PAGES128_PER_SECTOR	128U		/**< 128 Pages per Sector */
+#define PAGES256_PER_SECTOR	256U		/**< 256 Pages per Sector */
+#define PAGES512_PER_SECTOR	512U		/**< 512 Pages per Sector */
+#define PAGES1024_PER_SECTOR	1024U		/**< 1024 Pages per Sector */
+#define NUM_OF_SECTORS2		2U		/**< 2 Sectors */
+#define NUM_OF_SECTORS4		4U		/**< 4 Sectors */
+#define NUM_OF_SECTORS8		8U		/**< 8 Sector */
+#define NUM_OF_SECTORS16	16U		/**< 16 Sectors */
+#define NUM_OF_SECTORS32	32U		/**< 32 Sectors */
+#define NUM_OF_SECTORS64	64U		/**< 64 Sectors */
+#define NUM_OF_SECTORS128	128U		/**< 128 Sectors */
+#define NUM_OF_SECTORS256	256U		/**< 256 Sectors */
+#define NUM_OF_SECTORS512	512U		/**< 512 Sectors */
+#define NUM_OF_SECTORS1024	1024U		/**< 1024 Sectors */
+#define NUM_OF_SECTORS2048	2048U		/**< 2048 Sectors */
+#define NUM_OF_SECTORS4096	4096U		/**< 4096 Sectors */
+#define NUM_OF_SECTORS8192	8192U		/**< 8192 Sectors */
+#define SECTOR_SIZE_64K		0X10000U	/**< 64K Sector */
+#define SECTOR_SIZE_128K	0X20000U	/**< 128K Sector */
+#define SECTOR_SIZE_256K	0X40000U	/**< 256K Sector */
+#define SECTOR_SIZE_512K	0X80000U	/**< 512K Sector */
+
+
+#define XQSPIPSU_READMODE_DMA	0x0U	/**< DMA read mode */
+#define XQSPIPSU_READMODE_IO	0x1U	/**< IO read mode */
+
+#define XQSPIPSU_SELECT_FLASH_CS_LOWER	0x1U	/**< Select lower flash */
+#define XQSPIPSU_SELECT_FLASH_CS_UPPER	0x2U	/**< Select upper flash */
+#define XQSPIPSU_SELECT_FLASH_CS_BOTH	0x3U	/**< Select both flash */
+
+#define XQSPIPSU_SELECT_FLASH_BUS_LOWER	0x1U	/**< Select lower bus flash */
+#define XQSPIPSU_SELECT_FLASH_BUS_UPPER	0x2U	/**< Select upper bus flash */
+#define XQSPIPSU_SELECT_FLASH_BUS_BOTH	0x3U	/**< Select both bus flash */
+
+#define XQSPIPSU_SELECT_MODE_SPI	0x1U	/**< Select SPI mode */
+#define XQSPIPSU_SELECT_MODE_DUALSPI	0x2U	/**< Select dual SPI mode */
+#define XQSPIPSU_SELECT_MODE_QUADSPI	0x4U	/**< Select quad SPI mode */
+
+#define XQSPIPSU_GENFIFO_CS_SETUP	0x05U	/**< Chip select setup in GENFIO */
+#define XQSPIPSU_GENFIFO_CS_HOLD	0x04U	/**< Chip select hold in GENFIFO */
+
+#define XQSPIPSU_CLK_ACTIVE_LOW_OPTION	0x2U	/**< Clk Active low option */
+#define XQSPIPSU_CLK_PHASE_1_OPTION	0x4U	/**< Clk phase 1 option */
+#define XQSPIPSU_MANUAL_START_OPTION	0x8U	/**< Manual start option */
+#if !defined (versal)
+#define XQSPIPSU_LQSPI_MODE_OPTION	0x20U	/**< LQSPI mode option */
+
+#define XQSPIPSU_LQSPI_LESS_THEN_SIXTEENMB	1U /**< LQSPI less Than 16 MB */
+#endif
+
+#define XQSPIPSU_GENFIFO_EXP_START	0x100U /**< Genfifo start */
+
+#define XQSPIPSU_DMA_BYTES_MAX		0x10000000U /**< DMA bytes max */
+
+#define XQSPIPSU_CLK_PRESCALE_2		0x00U	/**< Clock prescale 2 */
+#define XQSPIPSU_CLK_PRESCALE_4		0x01U	/**< Clock prescale 4 */
+#define XQSPIPSU_CLK_PRESCALE_8		0x02U	/**< Clock prescale 8 */
+#define XQSPIPSU_CLK_PRESCALE_16	0x03U	/**< Clock prescale 16 */
+#define XQSPIPSU_CLK_PRESCALE_32	0x04U	/**< Clock prescale 32 */
+#define XQSPIPSU_CLK_PRESCALE_64	0x05U	/**< Clock prescale 64 */
+#define XQSPIPSU_CLK_PRESCALE_128	0x06U	/**< Clock prescale 128 */
+#define XQSPIPSU_CLK_PRESCALE_256	0x07U	/**< Clock prescale 256 */
+#define XQSPIPSU_CR_PRESC_MAXIMUM	7U	/**< Prescale max */
+
+#define XQSPIPSU_CONNECTION_MODE_SINGLE		0U /**< Single mode connection */
+#define XQSPIPSU_CONNECTION_MODE_STACKED	1U /**< Stacked mode connection */
+#define XQSPIPSU_CONNECTION_MODE_PARALLEL	2U /**< Parallel mode connection */
+
+/*QSPI Frequencies*/
+#define XQSPIPSU_FREQ_37_5MHZ 37500000U	/**< Frequency 375 Mhz */
+#define XQSPIPSU_FREQ_40MHZ 40000000U	/**< Frequency 40 Mhz */
+#define XQSPIPSU_FREQ_100MHZ 100000000U	/**< Frequency 100 Mhz */
+#define XQSPIPSU_FREQ_150MHZ 150000000U	/**< Frequency 150 Mhz */
+
+/* Add more flags as required */
+#define XQSPIPSU_MSG_FLAG_STRIPE	0x1U /**< Stripe Msg flag */
+#define XQSPIPSU_MSG_FLAG_RX		0x2U /**< Rx Msg flag */
+#define XQSPIPSU_MSG_FLAG_TX		0x4U /**< Tx Msg flag */
+#define XQSPIPSU_MSG_FLAG_POLL		0x8U /**< POLL Msg flag */
+
+#define XQSPIPSU_RXADDR_OVER_32BIT	0x100000000U /**< Rx address over 32 bit */
+
+#define XQSPIPSU_SET_WP		1 /**< GQSPI configuration to toggle WP of flash */
+
+/**
+ * select QSPI controller
+ */
+#define XQspiPsu_Select(InstancePtr, Mask)	\
+	XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + \
+			XQSPIPSU_SEL_OFFSET, (Mask))
+
+/**
+ * Enable QSPI Controller
+ */
+#define XQspiPsu_Enable(InstancePtr)	\
+	XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + \
+			XQSPIPSU_EN_OFFSET, XQSPIPSU_EN_MASK)
+
+/**
+ * Disable QSPI controller  */
+#define XQspiPsu_Disable(InstancePtr)	\
+	XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + \
+			XQSPIPSU_EN_OFFSET, 0x0U)
+
+/**
+ * Read Configuration register of LQSPI Controller
+ */
+#if !defined (versal)
+#define XQspiPsu_GetLqspiConfigReg(InstancePtr)	\
+	XQspiPsu_In32((XQSPIPS_BASEADDR) + \
+			XQSPIPSU_LQSPI_CR_OFFSET)
+#endif
+
+/*****************************************************************************/
+/**
+ *
+ * This function enables the manual start option
+ *
+ * @param	InstancePtr is a pointer to the XQspiPsu instance.
+ *
+ * @return	None
+ *
+ * @note	None.
+ *
+ ******************************************************************************/
+static inline void XQspiPsu_ManualStartEnable(XQspiPsu *InstancePtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_ManualStartEnable\r\n");
+#endif
+
+	if (InstancePtr->IsManualstart == (u8)TRUE) {
+#ifdef DEBUG
+		xil_printf("\nManual Start\r\n");
+#endif
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
+		XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET) |
+			XQSPIPSU_CFG_START_GEN_FIFO_MASK);
+	}
+}
+/*****************************************************************************/
+/**
+ *
+ * This function writes the GENFIFO entry to assert CS.
+ *
+ * @param	InstancePtr is a pointer to the XQspiPsu instance.
+ *
+ * @return	None
+ *
+ * @note	None.
+ *
+ ******************************************************************************/
+static inline void XQspiPsu_GenFifoEntryCSAssert(const XQspiPsu *InstancePtr)
+{
+	u32 GenFifoEntry;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_GenFifoEntryCSAssert\r\n");
+#endif
+
+	GenFifoEntry = 0x0U;
+	GenFifoEntry |= (XQSPIPSU_GENFIFO_MODE_SPI | InstancePtr->GenFifoCS |
+					 InstancePtr->GenFifoBus | XQSPIPSU_GENFIFO_CS_SETUP);
+#ifdef DEBUG
+	xil_printf("\nFifoEntry=%08x\r\n", GenFifoEntry);
+#endif
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
+}
+
+/*****************************************************************************/
+/**
+ *
+ * This function writes the GENFIFO entry to de-assert CS.
+ *
+ * @param	InstancePtr is a pointer to the XQspiPsu instance.
+ *
+ * @return	None
+ *
+ * @note	None.
+ *
+ ******************************************************************************/
+static inline void XQspiPsu_GenFifoEntryCSDeAssert(const XQspiPsu *InstancePtr)
+{
+	u32 GenFifoEntry;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_GenFifoEntryCSDeAssert\r\n");
+#endif
+
+	GenFifoEntry = 0x0U;
+	GenFifoEntry |= (XQSPIPSU_GENFIFO_MODE_SPI | InstancePtr->GenFifoBus |
+					XQSPIPSU_GENFIFO_CS_HOLD);
+#ifdef DEBUG
+	xil_printf("\nFifoEntry=%08x\r\n", GenFifoEntry);
+#endif
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
+}
+
+/*****************************************************************************/
+/**
+ *
+ * This is a stub for the status callback. The stub is here in case the upper
+ * layers forget to set the handler.
+ *
+ * @param	CallBackRef is a pointer to the upper layer callback reference
+ * @param	StatusEvent is the event that just occurred.
+ * @param	ByteCount is the number of bytes transferred up until the event
+ *		occurred.
+ *
+ * @return	None.
+ *
+ * @note	None.
+ *
+ ******************************************************************************/
+static inline void StubStatusHandler(const void *CallBackRef, u32 StatusEvent,
+				u32 ByteCount)
+{
+	(const void) CallBackRef;
+	(void) StatusEvent;
+	(void) ByteCount;
+
+	Xil_AssertVoidAlways();
+}
+/************************** Function Prototypes ******************************/
+
+/* Initialization and reset */
+XQspiPsu_Config *XQspiPsu_LookupConfig(u16 DeviceId);
+s32 XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr,
+			   const XQspiPsu_Config *ConfigPtr,
+			   UINTPTR EffectiveAddr);
+void XQspiPsu_Reset(XQspiPsu *InstancePtr);
+void XQspiPsu_Abort(XQspiPsu *InstancePtr);
+
+/* Transfer functions and handlers */
+s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
+				u32 NumMsg);
+s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
+				u32 NumMsg);
+s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr);
+void XQspiPsu_SetStatusHandler(XQspiPsu *InstancePtr, void *CallBackRef,
+				XQspiPsu_StatusHandler FuncPointer);
+
+/* Non blocking Transfer functions */
+s32 XQspiPsu_StartDmaTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
+				u32 NumMsg);
+s32 XQspiPsu_CheckDmaDone(XQspiPsu *InstancePtr);
+
+/* Configuration functions */
+s32 XQspiPsu_SetClkPrescaler(const XQspiPsu *InstancePtr, u8 Prescaler);
+void XQspiPsu_SelectFlash(XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus);
+s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options);
+s32 XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options);
+u32 XQspiPsu_GetOptions(const XQspiPsu *InstancePtr);
+s32 XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode);
+void XQspiPsu_SetWP(const XQspiPsu *InstancePtr, u8 Value);
+void XQspiPsu_WriteProtectToggle(const XQspiPsu *InstancePtr, u32 Toggle);
+void XQspiPsu_Idle(const XQspiPsu *InstancePtr);
+
+/************************** Variable Prototypes ******************************/
+
+/**
+ * This table contains configuration information for each QSPIPSU device
+ * in the system.
+ */
+#ifndef __rtems__
+extern XQspiPsu_Config XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES];
+#endif /* __rtems__ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* XQSPIPSU_H_ */
+/** @} */
diff --git a/bsps/include/dev/spi/xqspipsu_control.h b/bsps/include/dev/spi/xqspipsu_control.h
new file mode 100644
index 0000000000..76b0a8ce7c
--- /dev/null
+++ b/bsps/include/dev/spi/xqspipsu_control.h
@@ -0,0 +1,102 @@
+/******************************************************************************
+* Copyright (C) 2020 - 2022 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+
+/*****************************************************************************/
+/**
+ *
+ * @file xqspipsu_control.h
+ * @addtogroup Overview
+ * @{
+ *
+ * This is the header file for the implementation of QSPIPSU driver.
+ * Generic QSPI interface allows for communication to any QSPI slave device.
+ * GQSPI contains a GENFIFO into which the bus transfers required are to be
+ * pushed with appropriate configuration. The controller provides TX and RX
+ * FIFO's and a DMA to be used for RX transfers. The controller executes each
+ * GENFIFO entry noting the configuration and places data on the bus as required
+ *
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who Date     Changes
+ * ----- --- -------- -----------------------------------------------.
+ * 1.11   akm  03/09/20 First release
+ * 1.13   akm  01/04/21 Fix MISRA-C violations.
+ * 1.15   akm  03/03/22 Enable tapdelay settings for applications on
+ * 			 Microblaze platform.
+ *
+ * </pre>
+ *
+ ******************************************************************************/
+
+/** @cond INTERNAL */
+#ifndef XQSPIPSU_CONTROL_H_		/**< prevent circular inclusions */
+#define XQSPIPSU_CONTROL_H_		/**< by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xqspipsu.h"
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (__MICROBLAZE__)
+#define TAPDLY_BYPASS_VALVE_40MHZ 0x01U
+#define TAPDLY_BYPASS_VALVE_100MHZ 0x01U
+#define USE_DLY_LPBK  0x01U
+#define USE_DATA_DLY_ADJ 0x01U
+#define DATA_DLY_ADJ_DLY 0X02U
+#define LPBK_DLY_ADJ_DLY0 0X02U
+#define LPBK_DLY_ADJ_DLY1 0X02U
+#endif
+
+#ifdef __MICROBLAZE__
+#define XPS_SYS_CTRL_BASEADDR   0xFF180000U     /**< System controller Baseaddress */
+#endif
+/************************** Function Prototypes ******************************/
+void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg);
+u32 XQspiPsu_SetIOMode(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg);
+void XQspiPsu_IORead(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
+		u32 StatusReg);
+void XQspiPsu_PollDataConfig(XQspiPsu *InstancePtr, XQspiPsu_Msg *FlashMsg);
+void XQspiPsu_TXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg);
+void XQspiPsu_SetupRxDma(const XQspiPsu *InstancePtr,
+					XQspiPsu_Msg *Msg);
+void XQspiPsu_Setup64BRxDma(const XQspiPsu *InstancePtr,
+					XQspiPsu_Msg *Msg);
+void XQspiPsu_RXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg);
+void XQspiPsu_TXRXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
+					u32 *GenFifoEntry);
+void XQspiPsu_GenFifoEntryDataLen(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
+		u32 *GenFifoEntry);
+u32 XQspiPsu_CreatePollDataConfig(const XQspiPsu *InstancePtr,
+		const XQspiPsu_Msg *FlashMsg);
+void XQspiPsu_PollDataHandler(XQspiPsu *InstancePtr, u32 StatusReg);
+u32 XQspiPsu_SelectSpiMode(u8 SpiMode);
+void XQspiPsu_SetDefaultConfig(XQspiPsu *InstancePtr);
+void XQspiPsu_FillTxFifo(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, u32 Size);
+void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr,	XQspiPsu_Msg *Msg, s32 Size);
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (__MICROBLAZE__)
+s32 XQspipsu_Set_TapDelay(const XQspiPsu *InstancePtr, u32 TapdelayBypass,
+						u32 LPBKDelay, u32 Datadelay);
+s32 XQspipsu_Calculate_Tapdelay(const XQspiPsu *InstancePtr, u8 Prescaler);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* XQSPIPSU_CONTROL_H_ */
+/** @endcond */
+/** @} */
diff --git a/bsps/include/dev/spi/xqspipsu_flash_config.h b/bsps/include/dev/spi/xqspipsu_flash_config.h
new file mode 100644
index 0000000000..323b223ee3
--- /dev/null
+++ b/bsps/include/dev/spi/xqspipsu_flash_config.h
@@ -0,0 +1,355 @@
+/******************************************************************************
+* Copyright (C) 2020 - 2022 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspipsu_flash_config.h
+*
+*
+* This file contains flash configuration table and flash related defines.
+* This file should be included in the example files and compiled along with
+* the examples (*.c).
+*
+* @note
+*
+* None.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.12  akm 07/07/20 First release
+* 1.12	akm 07/07/20 Add support for Macronix flash(MX66U2G45G, MX66L2G45G)
+*                    and ISSI flash(IS25LP01G, IS25WP01G) parts.
+* 1.13  akm 12/10/20 Set Read command as per the qspi bus width.
+* 1.14  akm 07/16/21 Enable Quad Mode for Winbond flashes.
+* 1.15  akm 11/19/21 Fix read/write failures on Spansion flash parts.
+*
+*</pre>
+*
+ ******************************************************************************/
+
+#ifndef XQSPIPSU_FLASH_CONFIG_H_		/* prevent circular inclusions */
+#define XQSPIPSU_FLASH_CONFIG_H_		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"	/* SDK generated parameters */
+#include "xqspipsu.h"		/* QSPIPSU device driver */
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The following constants define the commands which may be sent to the Flash
+ * device.
+ */
+#define WRITE_STATUS_CMD	0x01
+#define WRITE_CMD		0x02
+#define READ_CMD		0x03
+#define WRITE_DISABLE_CMD	0x04
+#define READ_STATUS_CMD		0x05
+#define WRITE_ENABLE_CMD	0x06
+#define VOLATILE_WRITE_ENABLE_CMD	0x50
+#define QUAD_MODE_ENABLE_BIT	0x06
+#define FAST_READ_CMD		0x0B
+#define DUAL_READ_CMD		0x3B
+#define QUAD_READ_CMD		0x6B
+#define BULK_ERASE_CMD		0xC7
+#define	SEC_ERASE_CMD		0xD8
+#define READ_ID			0x9F
+#define READ_CONFIG_CMD		0x35
+#define WRITE_CONFIG_CMD	0x01
+#define ENTER_4B_ADDR_MODE	0xB7
+#define EXIT_4B_ADDR_MODE	0xE9
+#define EXIT_4B_ADDR_MODE_ISSI	0x29
+/* 4-byte address opcodes */
+#define READ_CMD_4B			0x13
+#define FAST_READ_CMD_4B		0x0C
+#define DUAL_READ_CMD_4B		0x3C
+#define QUAD_READ_CMD_4B		0x6C
+#define WRITE_CMD_4B			0x12
+#define SEC_ERASE_CMD_4B		0xDC
+
+#define BANK_REG_RD		0x16
+#define BANK_REG_WR		0x17
+/* Bank register is called Extended Address Register in Micron */
+#define EXTADD_REG_RD		0xC8
+#define EXTADD_REG_WR		0xC5
+#define	DIE_ERASE_CMD		0xC4
+#define READ_FLAG_STATUS_CMD	0x70
+
+#define WRITE_STATUS_REG_2_CMD	0x31
+#define READ_STATUS_REG_2_CMD	0x35
+#define WB_QUAD_MODE_ENABLE_BIT	0x01
+
+/*
+ * The following constants define the offsets within a FlashBuffer data
+ * type for each kind of data.  Note that the read data offset is not the
+ * same as the write data because the QSPIPSU driver is designed to allow full
+ * duplex transfers such that the number of bytes received is the number
+ * sent and received.
+ */
+#define COMMAND_OFFSET		0 /* Flash instruction */
+#define ADDRESS_1_OFFSET	1 /* MSB byte of address to read or write */
+#define ADDRESS_2_OFFSET	2 /* Middle byte of address to read or write */
+#define ADDRESS_3_OFFSET	3 /* LSB byte of address to read or write */
+#define ADDRESS_4_OFFSET	4 /* LSB byte of address to read or write
+				   * when 4 byte address
+				   */
+#define DATA_OFFSET		5 /* Start of Data for Read/Write */
+#define DUMMY_OFFSET		4 /* Dummy byte offset for fast, dual and quad
+				   * reads
+				   */
+#define DUMMY_SIZE		1 /* Number of dummy bytes for fast, dual and
+				   * quad reads
+				   */
+#define DUMMY_CLOCKS		8 /* Number of dummy bytes for fast, dual and
+				   * quad reads
+				   */
+#define RD_ID_SIZE		4 /* Read ID command + 3 bytes ID response */
+#define BULK_ERASE_SIZE		1 /* Bulk Erase command size */
+#define SEC_ERASE_SIZE		4 /* Sector Erase command + Sector address */
+#define BANK_SEL_SIZE		2 /* BRWR or EARWR command + 1 byte bank
+				   * value
+				   */
+#define RD_CFG_SIZE		2 /* 1 byte Configuration register + RD CFG
+				   * command
+				   */
+#define WR_CFG_SIZE		3 /* WRR command + 1 byte each Status and
+				   * Config Reg
+				   */
+#define DIE_ERASE_SIZE	4	/* Die Erase command + Die address */
+
+/*
+ * The following constants specify the extra bytes which are sent to the
+ * Flash on the QSPIPSu interface, that are not data, but control information
+ * which includes the command and address
+ */
+#define OVERHEAD_SIZE		4
+
+/*
+ * Base address of Flash1
+ */
+#define FLASH1BASE 0x0000000
+
+/*
+ * Sixteen MB
+ */
+#define SIXTEENMB 0x1000000
+
+
+/*
+ * Mask for quad enable bit in Flash configuration register
+ */
+#define FLASH_QUAD_EN_MASK 0x02
+
+#define FLASH_SRWD_MASK 0x80
+
+/*
+ * Bank mask
+ */
+#define BANKMASK 0xF000000
+
+/*
+ * Bus width
+ */
+#define BUSWIDTH_SINGLE	0
+#define BUSWIDTH_DOUBLE	1
+
+/*
+ * Identification of Flash
+ * Micron:
+ * Byte 0 is Manufacturer ID;
+ * Byte 1 is first byte of Device ID - 0xBB or 0xBA
+ * Byte 2 is second byte of Device ID describes flash size:
+ * 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20
+ * Spansion:
+ * Byte 0 is Manufacturer ID;
+ * Byte 1 is Device ID - Memory Interface type - 0x20 or 0x02
+ * Byte 2 is second byte of Device ID describes flash size:
+ * 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20
+ */
+#define MICRON_ID_BYTE0		0x20
+#define SPANSION_ID_BYTE0	0x01
+#define WINBOND_ID_BYTE0	0xEF
+#define MACRONIX_ID_BYTE0	0xC2
+#define ISSI_ID_BYTE0		0x9D
+
+/**************************** Type Definitions *******************************/
+
+typedef struct{
+	u32 jedec_id;	/* JEDEC ID */
+
+	u32 SectSize;		/* Individual sector size or combined sector
+				 * size in case of parallel config
+				 */
+	u32 NumSect;		/* Total no. of sectors in one/two
+				 * flash devices
+				 */
+	u32 PageSize;		/* Individual page size or
+				 * combined page size in case of parallel
+				 * config
+				 */
+	u32 NumPage;		/* Total no. of pages in one/two flash
+				 * devices
+				 */
+	u32 FlashDeviceSize;	/* This is the size of one flash device
+				 * NOT the combination of both devices,
+				 * if present
+				 */
+	u32 SectMask;		/* Mask to get sector start address */
+	u8 NumDie;		/* No. of die forming a single flash */
+} FlashInfo;
+
+/************************** Variable Definitions *****************************/
+FlashInfo Flash_Config_Table[] = {
+	/* Spansion */
+	/*s25fl064l*/
+	{0x016017, SECTOR_SIZE_64K, NUM_OF_SECTORS128, BYTES256_PER_PAGE,
+		0x8000, 0x800000, 0xFFFF0000, 1},
+	/*s25fl128l*/
+	{0x016018, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE,
+		0x10000, 0x1000000, 0xFFFF0000, 1},
+	/*s25fl256l*/
+	{0x016019, SECTOR_SIZE_64K, NUM_OF_SECTORS512, BYTES256_PER_PAGE,
+		0x20000, 0x2000000, 0xFFFF0000, 1},
+	/*s25fl512s*/
+	{0x010220, SECTOR_SIZE_64K, NUM_OF_SECTORS1024, BYTES256_PER_PAGE,
+		0x40000, 0x4000000, 0xFFFF0000, 1},
+	/* Spansion 1Gbit is handled as 512Mbit stacked */
+	/* Micron */
+	/*n25q128a11*/
+	{0x20bb18, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE,
+		0x10000, 0x1000000, 0xFFFF0000, 1},
+	/*n25q128a13*/
+	{0x20ba18, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE,
+		0x10000, 0x1000000, 0xFFFF0000, 1},
+	/*n25q256ax1*/
+	{0x20bb19, SECTOR_SIZE_64K, NUM_OF_SECTORS512, BYTES256_PER_PAGE,
+		0x20000, 0x2000000, 0xFFFF0000, 1},
+	/*n25q256a*/
+	{0x20ba19, SECTOR_SIZE_64K, NUM_OF_SECTORS512, BYTES256_PER_PAGE,
+		0x20000, 0x2000000, 0xFFFF0000, 1},
+	/*mt25qu512a*/
+	{0x20bb20, SECTOR_SIZE_64K, NUM_OF_SECTORS1024, BYTES256_PER_PAGE,
+		0x40000, 0x4000000, 0xFFFF0000, 2},
+	/*n25q512ax3*/
+	{0x20ba20, SECTOR_SIZE_64K, NUM_OF_SECTORS1024, BYTES256_PER_PAGE,
+		0x40000, 0x4000000, 0xFFFF0000, 2},
+	/*n25q00a*/
+	{0x20bb21, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE,
+		0x80000, 0x8000000, 0xFFFF0000, 4},
+	/*n25q00*/
+	{0x20ba21, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE,
+		0x80000, 0x8000000, 0xFFFF0000, 4},
+	/*mt25qu02g*/
+	{0x20bb22, SECTOR_SIZE_64K, NUM_OF_SECTORS4096, BYTES256_PER_PAGE,
+		0x100000, 0x10000000, 0xFFFF0000, 4},
+	/*mt25ql02g*/
+	{0x20ba22, SECTOR_SIZE_64K, NUM_OF_SECTORS4096, BYTES256_PER_PAGE,
+		0x100000, 0x10000000, 0xFFFF0000, 4},
+	/* Winbond */
+	/*w25q128fw*/
+	{0xef6018, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE,
+		0x10000, 0x1000000, 0xFFFF0000, 1},
+	/*w25q128jv*/
+	{0xef7018, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE,
+		0x10000, 0x1000000, 0xFFFF0000, 1},
+	/*w25h02jv*/
+	{0xef9022, SECTOR_SIZE_64K, NUM_OF_SECTORS4096, BYTES256_PER_PAGE,
+		0x100000, 0x10000000, 0xFFFF0000, 4},
+	/* Macronix */
+	/*mx66l1g45g*/
+	{0xc2201b, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE,
+		0x80000, 0x8000000, 0xFFFF0000, 4},
+	/*mx66l1g55g*/
+	{0xc2261b, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE,
+		0x80000, 0x8000000, 0xFFFF0000, 4},
+	/*mx66u1g45g*/
+	{0xc2253b, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE,
+		0x80000, 0x8000000, 0xFFFF0000, 4},
+	/*mx66l2g45g*/
+	{0xc2201c, SECTOR_SIZE_64K, NUM_OF_SECTORS4096, BYTES256_PER_PAGE,
+		0x100000, 0x10000000, 0xFFFF0000, 1},
+	/*mx66u2g45g*/
+	{0xc2253c, SECTOR_SIZE_64K, NUM_OF_SECTORS4096, BYTES256_PER_PAGE,
+		0x100000, 0x10000000, 0xFFFF0000, 1},
+	/* ISSI */
+	/*is25wp080d*/
+	{0x9d7014, SECTOR_SIZE_64K, NUM_OF_SECTORS16, BYTES256_PER_PAGE,
+		0x1000, 0x100000, 0xFFFF0000, 1},
+	/*is25lp080d*/
+	{0x9d6014, SECTOR_SIZE_64K, NUM_OF_SECTORS16, BYTES256_PER_PAGE,
+		0x1000, 0x100000, 0xFFFF0000, 1},
+	/*is25wp016d*/
+	{0x9d7015, SECTOR_SIZE_64K, NUM_OF_SECTORS32, BYTES256_PER_PAGE,
+		0x2000, 0x200000, 0xFFFF0000, 1},
+	/*is25lp016d*/
+	{0x9d6015, SECTOR_SIZE_64K, NUM_OF_SECTORS32, BYTES256_PER_PAGE,
+		0x2000, 0x200000, 0xFFFF0000, 1},
+	/*is25wp032*/
+	{0x9d7016, SECTOR_SIZE_64K, NUM_OF_SECTORS64, BYTES256_PER_PAGE,
+		0x4000, 0x400000, 0xFFFF0000, 1},
+	/*is25lp032*/
+	{0x9d6016, SECTOR_SIZE_64K, NUM_OF_SECTORS64, BYTES256_PER_PAGE,
+		0x4000, 0x400000, 0xFFFF0000, 1},
+	/*is25wp064*/
+	{0x9d7017, SECTOR_SIZE_64K, NUM_OF_SECTORS128, BYTES256_PER_PAGE,
+		0x8000, 0x800000, 0xFFFF0000, 1},
+	/*is25lp064*/
+	{0x9d6017, SECTOR_SIZE_64K, NUM_OF_SECTORS128, BYTES256_PER_PAGE,
+		0x8000, 0x800000, 0xFFFF0000, 1},
+	/*is25wp128*/
+	{0x9d7018, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE,
+		0x10000, 0x1000000, 0xFFFF0000, 1},
+	/*is25lp128*/
+	{0x9d6018, SECTOR_SIZE_64K, NUM_OF_SECTORS256, BYTES256_PER_PAGE,
+		0x10000, 0x1000000, 0xFFFF0000, 1},
+	/*is25lp256d*/
+	{0x9d6019, SECTOR_SIZE_64K, NUM_OF_SECTORS512, BYTES256_PER_PAGE,
+		0x20000, 0x2000000, 0xFFFF0000, 1},
+	/*is25wp256d*/
+	{0x9d7019, SECTOR_SIZE_64K, NUM_OF_SECTORS512, BYTES256_PER_PAGE,
+		0x20000, 0x2000000, 0xFFFF0000, 1},
+	/*is25lp512m*/
+	{0x9d601a, SECTOR_SIZE_64K, NUM_OF_SECTORS1024, BYTES256_PER_PAGE,
+		0x40000, 0x4000000, 0xFFFF0000, 2},
+	/*is25wp512m*/
+	{0x9d701a, SECTOR_SIZE_64K, NUM_OF_SECTORS1024, BYTES256_PER_PAGE,
+		0x40000, 0x4000000, 0xFFFF0000, 2},
+	/*is25lp01g*/
+	{0x9d601b, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE,
+		0x80000, 0x8000000, 0xFFFF0000, 1},
+	/*is25wp01g*/
+	{0x9d701b, SECTOR_SIZE_64K, NUM_OF_SECTORS2048, BYTES256_PER_PAGE,
+		0x80000, 0x8000000, 0xFFFF0000, 1}
+};
+
+static INLINE u32 CalculateFCTIndex(u32 ReadId, u32 *FCTIndex)
+{
+	u32 Index;
+
+	for (Index = 0; Index < sizeof(Flash_Config_Table)/sizeof(Flash_Config_Table[0]);
+				Index++) {
+		if (ReadId == Flash_Config_Table[Index].jedec_id) {
+			*FCTIndex = Index;
+			return XST_SUCCESS;
+		}
+	}
+
+	return XST_FAILURE;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XQSPIPSU_FLASH_CONFIG_H_ */
+/** @} */
diff --git a/bsps/include/dev/spi/xqspipsu_hw.h b/bsps/include/dev/spi/xqspipsu_hw.h
new file mode 100644
index 0000000000..a798f9bb89
--- /dev/null
+++ b/bsps/include/dev/spi/xqspipsu_hw.h
@@ -0,0 +1,1006 @@
+/******************************************************************************
+* Copyright (C) 2014 - 2022 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xqspipsu_hw.h
+* @addtogroup Overview
+* @{
+*
+* This file contains low level access functions using the base address
+* directly without an instance.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------.
+* 1.0   hk  08/21/14 First release
+*       hk  03/18/15 Add DMA status register masks required.
+*       sk  04/24/15 Modified the code according to MISRAC-2012.
+* 1.2	nsk 07/01/16 Added LQSPI supported Masks
+*       rk  07/15/16 Added support for TapDelays at different frequencies.
+* 1.7	tjs	03/14/18 Added support in EL1 NS mode.
+* 1.9	tjs	04/17/18 Updated register addresses as per the latest revision
+* 					 of versal (CR#999610)
+* 1.9  aru 01/17/19 Fixed the violations for  MISRAC-2012
+*                  in safety mode .Done changes such as added U suffix
+* 1.11	akm 11/07/19 Removed LQSPI register access in Versal.
+* 1.15	akm 12/02/21 Fix Doxygen warnings.
+*
+* </pre>
+*
+******************************************************************************/
+#ifndef XQSPIPSU_HW_H		/**< prevent circular inclusions */
+#define XQSPIPSU_HW_H		/**< by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+/**
+ * @name Device Base Address
+ * Below macros gives QSPI, QSPIPSU base address.
+ * @{
+ */
+/**
+ * QSPI Base Address
+ */
+#if defined (versal)
+#define XQSPIPS_BASEADDR      0XF1030000U
+#else
+#define XQSPIPS_BASEADDR      0XFF0F0000U
+#endif
+
+#if defined (versal)
+#define XQSPIPSU_BASEADDR     0XF1030100U
+#else
+#define XQSPIPSU_BASEADDR     0xFF0F0100U
+#endif
+#define XQSPIPSU_OFFSET     0x100U
+/** @} */
+
+/**
+ * @name XQSPIPS Enable Register information
+ * QSPIPSU Enable Register
+ * @{
+ */
+/**
+ * Register: XQSPIPS_EN_REG
+ */
+#define XQSPIPS_EN_REG    ( ( XQSPIPS_BASEADDR ) + 0X00000014U )
+#define XQSPIPS_EN_SHIFT   0U
+#define XQSPIPS_EN_WIDTH   1U
+#define XQSPIPS_EN_MASK    0X00000001U
+/** @} */
+
+/**
+ * @name XQSPIPSU configuration Register information
+ * This register contains bits for configuring GQSPI controller
+ * @{
+ */
+/**
+ * Register: XQSPIPSU_CFG
+ */
+#define XQSPIPSU_CFG_OFFSET    0X00000000U
+
+#define XQSPIPSU_CFG_MODE_EN_SHIFT   30U
+#define XQSPIPSU_CFG_MODE_EN_WIDTH   2U
+#define XQSPIPSU_CFG_MODE_EN_MASK    0XC0000000U
+#define XQSPIPSU_CFG_MODE_EN_DMA_MASK	0X80000000U
+
+#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_SHIFT   29U
+#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_WIDTH   1U
+#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK    0X20000000U
+
+#define XQSPIPSU_CFG_START_GEN_FIFO_SHIFT   28U
+#define XQSPIPSU_CFG_START_GEN_FIFO_WIDTH   1U
+#define XQSPIPSU_CFG_START_GEN_FIFO_MASK    0X10000000U
+
+#define XQSPIPSU_CFG_ENDIAN_SHIFT   26U
+#define XQSPIPSU_CFG_ENDIAN_WIDTH   1U
+#define XQSPIPSU_CFG_ENDIAN_MASK    0X04000000U
+
+#define XQSPIPSU_CFG_EN_POLL_TO_SHIFT   20U
+#define XQSPIPSU_CFG_EN_POLL_TO_WIDTH   1U
+#define XQSPIPSU_CFG_EN_POLL_TO_MASK    0X00100000U
+
+#define XQSPIPSU_CFG_WP_HOLD_SHIFT   19U
+#define XQSPIPSU_CFG_WP_HOLD_WIDTH   1U
+#define XQSPIPSU_CFG_WP_HOLD_MASK    0X00080000U
+
+#define XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT   3U
+#define XQSPIPSU_CFG_BAUD_RATE_DIV_WIDTH   3U
+#define XQSPIPSU_CFG_BAUD_RATE_DIV_MASK    0X00000038U
+
+#define XQSPIPSU_CFG_CLK_PHA_SHIFT   2U
+#define XQSPIPSU_CFG_CLK_PHA_WIDTH   1U
+#define XQSPIPSU_CFG_CLK_PHA_MASK    0X00000004U
+
+#define XQSPIPSU_CFG_CLK_POL_SHIFT   1U
+#define XQSPIPSU_CFG_CLK_POL_WIDTH   1U
+#define XQSPIPSU_CFG_CLK_POL_MASK    0X00000002U
+/** @} */
+
+/**
+ * @name XQSPIPSU LQSPI Register information
+ * This register contains bits for configuring LQSPI
+ * @{
+ */
+/**
+ * Register: XQSPIPSU_LQSPI
+ */
+#if !defined (versal)
+#define XQSPIPSU_LQSPI_CR_OFFSET	0X000000A0U
+#define XQSPIPSU_LQSPI_CR_LINEAR_MASK     0x80000000U /**< LQSPI mode enable */
+#define XQSPIPSU_LQSPI_CR_TWO_MEM_MASK    0x40000000U /**< Both memories or one */
+#define XQSPIPSU_LQSPI_CR_SEP_BUS_MASK    0x20000000U /**< Separate memory bus */
+#define XQSPIPSU_LQSPI_CR_U_PAGE_MASK     0x10000000U /**< Upper memory page */
+#define XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK     0x01000000U /**< Upper memory page */
+#define XQSPIPSU_LQSPI_CR_MODE_EN_MASK    0x02000000U /**< Enable mode bits */
+#define XQSPIPSU_LQSPI_CR_MODE_ON_MASK    0x01000000U /**< Mode on */
+#define XQSPIPSU_LQSPI_CR_MODE_BITS_MASK  0x00FF0000U /**< Mode value for dual I/O
+                                                         or quad I/O */
+#define XQSPIPS_LQSPI_CR_INST_MASK       0x000000FFU /**< Read instr code */
+#define XQSPIPS_LQSPI_CR_RST_STATE       0x80000003U /**< Default LQSPI CR value */
+#define XQSPIPS_LQSPI_CR_4_BYTE_STATE       0x88000013U /**< Default 4 Byte LQSPI CR value */
+#define XQSPIPS_LQSPI_CFG_RST_STATE       0x800238C1U /**< Default LQSPI CFG value */
+#endif
+/** @} */
+
+/**
+ * @name XQSPIPSU Interrupt Status Register information
+ * QSPIPSU Interrupt Status Register
+ * @{
+ */
+/**
+ * Register: XQSPIPSU_ISR
+ */
+#define XQSPIPSU_ISR_OFFSET	0X00000004U
+
+#define XQSPIPSU_ISR_RXEMPTY_SHIFT   11U
+#define XQSPIPSU_ISR_RXEMPTY_WIDTH   1U
+#define XQSPIPSU_ISR_RXEMPTY_MASK    0X00000800U
+
+#define XQSPIPSU_ISR_GENFIFOFULL_SHIFT   10U
+#define XQSPIPSU_ISR_GENFIFOFULL_WIDTH   1U
+#define XQSPIPSU_ISR_GENFIFOFULL_MASK    0X00000400U
+
+#define XQSPIPSU_ISR_GENFIFONOT_FULL_SHIFT   9U
+#define XQSPIPSU_ISR_GENFIFONOT_FULL_WIDTH   1U
+#define XQSPIPSU_ISR_GENFIFONOT_FULL_MASK    0X00000200U
+
+#define XQSPIPSU_ISR_TXEMPTY_SHIFT   8U
+#define XQSPIPSU_ISR_TXEMPTY_WIDTH   1U
+#define XQSPIPSU_ISR_TXEMPTY_MASK    0X00000100U
+
+#define XQSPIPSU_ISR_GENFIFOEMPTY_SHIFT   7U
+#define XQSPIPSU_ISR_GENFIFOEMPTY_WIDTH   1U
+#define XQSPIPSU_ISR_GENFIFOEMPTY_MASK    0X00000080U
+
+#define XQSPIPSU_ISR_RXFULL_SHIFT   5U
+#define XQSPIPSU_ISR_RXFULL_WIDTH   1U
+#define XQSPIPSU_ISR_RXFULL_MASK    0X00000020U
+
+#define XQSPIPSU_ISR_RXNEMPTY_SHIFT   4U
+#define XQSPIPSU_ISR_RXNEMPTY_WIDTH   1U
+#define XQSPIPSU_ISR_RXNEMPTY_MASK    0X00000010U
+
+#define XQSPIPSU_ISR_TXFULL_SHIFT   3U
+#define XQSPIPSU_ISR_TXFULL_WIDTH   1U
+#define XQSPIPSU_ISR_TXFULL_MASK    0X00000008U
+
+#define XQSPIPSU_ISR_TXNOT_FULL_SHIFT   2U
+#define XQSPIPSU_ISR_TXNOT_FULL_WIDTH   1U
+#define XQSPIPSU_ISR_TXNOT_FULL_MASK    0X00000004U
+
+#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_SHIFT   1U
+#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_WIDTH   1U
+#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK    0X00000002U
+
+#define XQSPIPSU_ISR_WR_TO_CLR_MASK 0X00000002U
+/** @} */
+
+/**
+ * @name XQSPIPSU Interrupt Enable Register information
+ * This register bits for enabling interrupts
+ * @{
+ */
+/**
+ * Register: XQSPIPSU_IER
+ */
+#define XQSPIPSU_IER_OFFSET    0X00000008U
+
+#define XQSPIPSU_IER_RXEMPTY_SHIFT   11U
+#define XQSPIPSU_IER_RXEMPTY_WIDTH   1U
+#define XQSPIPSU_IER_RXEMPTY_MASK    0X00000800U
+
+#define XQSPIPSU_IER_GENFIFOFULL_SHIFT   10U
+#define XQSPIPSU_IER_GENFIFOFULL_WIDTH   1U
+#define XQSPIPSU_IER_GENFIFOFULL_MASK    0X00000400U
+
+#define XQSPIPSU_IER_GENFIFONOT_FULL_SHIFT   9U
+#define XQSPIPSU_IER_GENFIFONOT_FULL_WIDTH   1U
+#define XQSPIPSU_IER_GENFIFONOT_FULL_MASK    0X00000200U
+
+#define XQSPIPSU_IER_TXEMPTY_SHIFT   8U
+#define XQSPIPSU_IER_TXEMPTY_WIDTH   1U
+#define XQSPIPSU_IER_TXEMPTY_MASK    0X00000100U
+
+#define XQSPIPSU_IER_GENFIFOEMPTY_SHIFT   7U
+#define XQSPIPSU_IER_GENFIFOEMPTY_WIDTH   1U
+#define XQSPIPSU_IER_GENFIFOEMPTY_MASK    0X00000080U
+
+#define XQSPIPSU_IER_RXFULL_SHIFT   5U
+#define XQSPIPSU_IER_RXFULL_WIDTH   1U
+#define XQSPIPSU_IER_RXFULL_MASK    0X00000020U
+
+#define XQSPIPSU_IER_RXNEMPTY_SHIFT   4U
+#define XQSPIPSU_IER_RXNEMPTY_WIDTH   1U
+#define XQSPIPSU_IER_RXNEMPTY_MASK    0X00000010U
+
+#define XQSPIPSU_IER_TXFULL_SHIFT   3U
+#define XQSPIPSU_IER_TXFULL_WIDTH   1U
+#define XQSPIPSU_IER_TXFULL_MASK    0X00000008U
+
+#define XQSPIPSU_IER_TXNOT_FULL_SHIFT   2U
+#define XQSPIPSU_IER_TXNOT_FULL_WIDTH   1U
+#define XQSPIPSU_IER_TXNOT_FULL_MASK    0X00000004U
+
+#define XQSPIPSU_IER_POLL_TIME_EXPIRE_SHIFT   1U
+#define XQSPIPSU_IER_POLL_TIME_EXPIRE_WIDTH   1U
+#define XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK    0X00000002U
+/** @} */
+
+/**
+ * @name XQSPIPSU Interrupt Disable Register information
+ * This register bits for disabling interrupts
+ * @{
+ */
+/**
+ * Register: XQSPIPSU_IDR
+ */
+#define XQSPIPSU_IDR_OFFSET    0X0000000CU
+
+#define XQSPIPSU_IDR_RXEMPTY_SHIFT   11U
+#define XQSPIPSU_IDR_RXEMPTY_WIDTH   1U
+#define XQSPIPSU_IDR_RXEMPTY_MASK    0X00000800U
+
+#define XQSPIPSU_IDR_GENFIFOFULL_SHIFT   10U
+#define XQSPIPSU_IDR_GENFIFOFULL_WIDTH   1U
+#define XQSPIPSU_IDR_GENFIFOFULL_MASK    0X00000400U
+
+#define XQSPIPSU_IDR_GENFIFONOT_FULL_SHIFT   9U
+#define XQSPIPSU_IDR_GENFIFONOT_FULL_WIDTH   1U
+#define XQSPIPSU_IDR_GENFIFONOT_FULL_MASK    0X00000200U
+
+#define XQSPIPSU_IDR_TXEMPTY_SHIFT   8U
+#define XQSPIPSU_IDR_TXEMPTY_WIDTH   1U
+#define XQSPIPSU_IDR_TXEMPTY_MASK    0X00000100U
+
+#define XQSPIPSU_IDR_GENFIFOEMPTY_SHIFT   7U
+#define XQSPIPSU_IDR_GENFIFOEMPTY_WIDTH   1U
+#define XQSPIPSU_IDR_GENFIFOEMPTY_MASK    0X00000080U
+
+#define XQSPIPSU_IDR_RXFULL_SHIFT   5U
+#define XQSPIPSU_IDR_RXFULL_WIDTH   1U
+#define XQSPIPSU_IDR_RXFULL_MASK    0X00000020U
+
+#define XQSPIPSU_IDR_RXNEMPTY_SHIFT   4U
+#define XQSPIPSU_IDR_RXNEMPTY_WIDTH   1U
+#define XQSPIPSU_IDR_RXNEMPTY_MASK    0X00000010U
+
+#define XQSPIPSU_IDR_TXFULL_SHIFT   3U
+#define XQSPIPSU_IDR_TXFULL_WIDTH   1U
+#define XQSPIPSU_IDR_TXFULL_MASK    0X00000008U
+
+#define XQSPIPSU_IDR_TXNOT_FULL_SHIFT   2U
+#define XQSPIPSU_IDR_TXNOT_FULL_WIDTH   1U
+#define XQSPIPSU_IDR_TXNOT_FULL_MASK    0X00000004U
+
+#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_SHIFT   1U
+#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_WIDTH   1U
+#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_MASK    0X00000002U
+
+#define XQSPIPSU_IDR_ALL_MASK    0X0FBEU
+/** @} */
+
+/**
+ * @name XQSPIPSU Interrupt Mask Register information
+ * This register bits for masking interrupts
+ * @{
+ */
+/**
+ * Register: XQSPIPSU_IMR
+ */
+#define XQSPIPSU_IMR_OFFSET    0X00000010U
+
+#define XQSPIPSU_IMR_RXEMPTY_SHIFT   11U
+#define XQSPIPSU_IMR_RXEMPTY_WIDTH   1U
+#define XQSPIPSU_IMR_RXEMPTY_MASK    0X00000800U
+
+#define XQSPIPSU_IMR_GENFIFOFULL_SHIFT   10U
+#define XQSPIPSU_IMR_GENFIFOFULL_WIDTH   1U
+#define XQSPIPSU_IMR_GENFIFOFULL_MASK    0X00000400U
+
+#define XQSPIPSU_IMR_GENFIFONOT_FULL_SHIFT   9U
+#define XQSPIPSU_IMR_GENFIFONOT_FULL_WIDTH   1U
+#define XQSPIPSU_IMR_GENFIFONOT_FULL_MASK    0X00000200U
+
+#define XQSPIPSU_IMR_TXEMPTY_SHIFT   8U
+#define XQSPIPSU_IMR_TXEMPTY_WIDTH   1U
+#define XQSPIPSU_IMR_TXEMPTY_MASK    0X00000100U
+
+#define XQSPIPSU_IMR_GENFIFOEMPTY_SHIFT   7U
+#define XQSPIPSU_IMR_GENFIFOEMPTY_WIDTH   1U
+#define XQSPIPSU_IMR_GENFIFOEMPTY_MASK    0X00000080U
+
+#define XQSPIPSU_IMR_RXFULL_SHIFT   5U
+#define XQSPIPSU_IMR_RXFULL_WIDTH   1U
+#define XQSPIPSU_IMR_RXFULL_MASK    0X00000020U
+
+#define XQSPIPSU_IMR_RXNEMPTY_SHIFT   4U
+#define XQSPIPSU_IMR_RXNEMPTY_WIDTH   1U
+#define XQSPIPSU_IMR_RXNEMPTY_MASK    0X00000010U
+
+#define XQSPIPSU_IMR_TXFULL_SHIFT   3U
+#define XQSPIPSU_IMR_TXFULL_WIDTH   1U
+#define XQSPIPSU_IMR_TXFULL_MASK    0X00000008U
+
+#define XQSPIPSU_IMR_TXNOT_FULL_SHIFT   2U
+#define XQSPIPSU_IMR_TXNOT_FULL_WIDTH   1U
+#define XQSPIPSU_IMR_TXNOT_FULL_MASK    0X00000004U
+
+#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_SHIFT   1U
+#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_WIDTH   1U
+#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_MASK    0X00000002U
+/** @} */
+
+/**
+ * @name XQSPIPSU Enable Register information
+ * This register bits for enabling QSPI controller
+ * @{
+ */
+/**
+ * Register: XQSPIPSU_EN_REG
+ */
+#define XQSPIPSU_EN_OFFSET    0X00000014U
+
+#define XQSPIPSU_EN_SHIFT   0U
+#define XQSPIPSU_EN_WIDTH   1U
+#define XQSPIPSU_EN_MASK    0X00000001U
+/** @} */
+
+/**
+ * @name XQSPIPSU TX Data Register information
+ * This register bits for configuring TXFIFO
+ * @{
+ */
+/**
+ * Register: XQSPIPSU_TXD
+ */
+#define XQSPIPSU_TXD_OFFSET    0X0000001CU
+
+#define XQSPIPSU_TXD_SHIFT   0U
+#define XQSPIPSU_TXD_WIDTH   32U
+#define XQSPIPSU_TXD_MASK    0XFFFFFFFFU
+
+#define XQSPIPSU_TXD_DEPTH    64
+/** @} */
+
+/**
+ * @name XQSPIPSU RX Data Register information
+ * This register bits for configuring RXFIFO
+ * @{
+ */
+/**
+ * Register: XQSPIPSU_RXD
+ */
+#define XQSPIPSU_RXD_OFFSET    0X00000020U
+
+#define XQSPIPSU_RXD_SHIFT   0U
+#define XQSPIPSU_RXD_WIDTH   32U
+#define XQSPIPSU_RXD_MASK    0XFFFFFFFFU
+/** @} */
+
+/**
+ * @name XQSPIPSU TX/RX Threshold Register information
+ * This register bits for configuring TX/RX Threshold
+ * @{
+ */
+/**
+ * Register: XQSPIPSU_TX_THRESHOLD
+ */
+#define XQSPIPSU_TX_THRESHOLD_OFFSET    0X00000028U
+
+#define XQSPIPSU_TX_FIFO_THRESHOLD_SHIFT   0U
+#define XQSPIPSU_TX_FIFO_THRESHOLD_WIDTH   6U
+#define XQSPIPSU_TX_FIFO_THRESHOLD_MASK    0X0000003FU
+#define XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL    0X01U
+
+#define XQSPIPSU_RX_THRESHOLD_OFFSET    0X0000002CU
+
+#define XQSPIPSU_RX_FIFO_THRESHOLD_SHIFT   0U
+#define XQSPIPSU_RX_FIFO_THRESHOLD_WIDTH   6U
+#define XQSPIPSU_RX_FIFO_THRESHOLD_MASK    0X0000003FU
+#define XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL    0X01U
+
+#define XQSPIPSU_RXFIFO_THRESHOLD_OPT 32U
+/** @} */
+
+/**
+ * @name XQSPIPSU GPIO Register information
+ * @{
+ */
+/**
+ * Register: XQSPIPSU_GPIO
+ */
+#define XQSPIPSU_GPIO_OFFSET    0X00000030U
+
+#define XQSPIPSU_GPIO_WP_N_SHIFT   0U
+#define XQSPIPSU_GPIO_WP_N_WIDTH   1U
+#define XQSPIPSU_GPIO_WP_N_MASK    0X00000001U
+/** @} */
+
+/**
+ * @name XQSPIPSU Loopback Master Clock Delay Adjustment Register information
+ * This register contains bits for configuring loopback
+ * @{
+ */
+/**
+ * Register: XQSPIPSU_LPBK_DLY_ADJ
+ */
+#define XQSPIPSU_LPBK_DLY_ADJ_OFFSET    0X00000038U
+
+#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT   5U
+#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_WIDTH   1U
+#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK    0X00000020U
+
+#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_SHIFT   3U
+#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_WIDTH   2U
+#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_MASK    0X00000018U
+
+#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_SHIFT   0U
+#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_WIDTH   3U
+#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_MASK    0X00000007U
+/** @} */
+
+/**
+ * @name XQSPIPSU GEN_FIFO Register information
+ * This register contains bits for configuring GENFIFO
+ * @{
+ */
+/**
+ * Register: XQSPIPSU_GEN_FIFO
+ */
+#define XQSPIPSU_GEN_FIFO_OFFSET    0X00000040U
+
+#define XQSPIPSU_GEN_FIFO_DATA_SHIFT   0U
+#define XQSPIPSU_GEN_FIFO_DATA_WIDTH   20U
+#define XQSPIPSU_GEN_FIFO_DATA_MASK    0X000FFFFFU
+/** @} */
+
+/**
+ * @name XQSPIPSU Select Register information
+ * This register contains bits for selection GQSPI/LQSPI controller
+ * @{
+ */
+/**
+ * Register: XQSPIPSU_SEL
+ */
+#define XQSPIPSU_SEL_OFFSET    0X00000044U
+
+#define XQSPIPSU_SEL_SHIFT   0U
+#define XQSPIPSU_SEL_WIDTH   1U
+#if !defined (versal)
+#define XQSPIPSU_SEL_LQSPI_MASK    0X0U
+#endif
+#define XQSPIPSU_SEL_GQSPI_MASK    0X00000001U
+/** @} */
+
+/**
+ * @name XQSPIPSU FIFO Control Register information
+ * This register contains bits for controlling TXFIFO and RXFIFO
+ * @{
+ */
+/**
+ * Register: XQSPIPSU_FIFO_CTRL
+ */
+#define XQSPIPSU_FIFO_CTRL_OFFSET    0X0000004CU
+
+#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_SHIFT   2U
+#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_WIDTH   1U
+#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK    0X00000004U
+
+#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_SHIFT   1U
+#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_WIDTH   1U
+#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK    0X00000002U
+
+#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_SHIFT   0U
+#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_WIDTH   1U
+#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK    0X00000001U
+/** @} */
+
+/**
+ * @name XQSPIPSU GENFIFO Threshold Register information
+ * This register contains bits for configuring GENFIFO threshold
+ * @{
+ */
+/**
+ * Register: XQSPIPSU_GF_THRESHOLD
+ */
+#define XQSPIPSU_GF_THRESHOLD_OFFSET    0X00000050U
+
+#define XQSPIPSU_GEN_FIFO_THRESHOLD_SHIFT   0U
+#define XQSPIPSU_GEN_FIFO_THRESHOLD_WIDTH   5U
+#define XQSPIPSU_GEN_FIFO_THRESHOLD_MASK    0X0000001FU
+#define XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL    0X10U
+/** @} */
+
+/**
+ * @name XQSPIPSU Poll configuration Register information
+ * This register contains bits for configuring Poll feature
+ * @{
+ */
+/**
+ * Register: XQSPIPSU_POLL_CFG
+ */
+#define XQSPIPSU_POLL_CFG_OFFSET    0X00000054U
+
+#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT   31U
+#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_WIDTH   1U
+#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_MASK    0X80000000U
+
+#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT   30U
+#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_WIDTH   1U
+#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_MASK    0X40000000U
+
+#define XQSPIPSU_POLL_CFG_MASK_EN_SHIFT   8U
+#define XQSPIPSU_POLL_CFG_MASK_EN_WIDTH   8U
+#define XQSPIPSU_POLL_CFG_MASK_EN_MASK    0X0000FF00U
+
+#define XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT   0U
+#define XQSPIPSU_POLL_CFG_DATA_VALUE_WIDTH   8U
+#define XQSPIPSU_POLL_CFG_DATA_VALUE_MASK    0X000000FFU
+
+#define XQSPIPSU_P_TO_OFFSET    0X00000058U
+
+#define XQSPIPSU_P_TO_VALUE_SHIFT   0U
+#define XQSPIPSU_P_TO_VALUE_WIDTH   32U
+#define XQSPIPSU_P_TO_VALUE_MASK    0XFFFFFFFFU
+/** @} */
+
+/**
+ * @name XQSPIPSU Transfer Status Register information
+ * This register contains bits for transfer status
+ * @{
+ */
+/**
+ * Register: XQSPIPSU_XFER_STS
+ */
+#define XQSPIPSU_XFER_STS_OFFSET	0X0000005CU
+
+#define XQSPIPSU_XFER_STS_PEND_BYTES_SHIFT   0U
+#define XQSPIPSU_XFER_STS_PEND_BYTES_WIDTH   32U
+#define XQSPIPSU_XFER_STS_PEND_BYTES_MASK    0XFFFFFFFFU
+/** @} */
+
+/**
+ * @name XQSPIPSU GEN_FIFO Snapshot Register information
+ * This register contains bits for configuring GENFIFO
+ * @{
+ */
+/**
+ * Register: XQSPIPSU_GF_SNAPSHOT
+ */
+#define XQSPIPSU_GF_SNAPSHOT_OFFSET    0X00000060U
+
+#define XQSPIPSU_GF_SNAPSHOT_SHIFT   0U
+#define XQSPIPSU_GF_SNAPSHOT_WIDTH   20U
+#define XQSPIPSU_GF_SNAPSHOT_MASK    0X000FFFFFU
+/** @} */
+
+/**
+ * @name XQSPIPSU Receive Data Copy Register information
+ * @{
+ */
+/**
+ * Register: XQSPIPSU_RX_COPY
+ */
+#define XQSPIPSU_RX_COPY_OFFSET    0X00000064U
+
+#define XQSPIPSU_RX_COPY_UPPER_SHIFT   8U
+#define XQSPIPSU_RX_COPY_UPPER_WIDTH   8U
+#define XQSPIPSU_RX_COPY_UPPER_MASK    0X0000FF00U
+
+#define XQSPIPSU_RX_COPY_LOWER_SHIFT   0U
+#define XQSPIPSU_RX_COPY_LOWER_WIDTH   8U
+#define XQSPIPSU_RX_COPY_LOWER_MASK    0X000000FFU
+/** @} */
+
+/**
+ * @name XQSPIPSU Module Identification Register information
+ * @{
+ */
+/**
+ * Register: XQSPIPSU_MOD_ID
+ */
+#define XQSPIPSU_MOD_ID_OFFSET    0X000000FCU
+
+#define XQSPIPSU_MOD_ID_SHIFT   0U
+#define XQSPIPSU_MOD_ID_WIDTH   32U
+#define XQSPIPSU_MOD_ID_MASK    0XFFFFFFFFU
+/** @} */
+
+/**
+ * @name XQSPIPSU DMA Transfer Register information
+ * This register contains bits for configuring DMA
+ * @{
+ */
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_ADDR
+ */
+#define XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET    0X00000700U
+
+#define XQSPIPSU_QSPIDMA_DST_ADDR_SHIFT   2U
+#define XQSPIPSU_QSPIDMA_DST_ADDR_WIDTH   30U
+#define XQSPIPSU_QSPIDMA_DST_ADDR_MASK    0XFFFFFFFCU
+
+#define XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET    0X00000704U
+
+#define XQSPIPSU_QSPIDMA_DST_SIZE_SHIFT   2U
+#define XQSPIPSU_QSPIDMA_DST_SIZE_WIDTH   27U
+#define XQSPIPSU_QSPIDMA_DST_SIZE_MASK    0X1FFFFFFCU
+
+#define XQSPIPSU_QSPIDMA_DST_STS_OFFSET    0X00000708U
+
+#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_SHIFT   13U
+#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_WIDTH   3U
+#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_MASK    0X0000E000U
+
+#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_SHIFT   5U
+#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_WIDTH   8U
+#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_MASK    0X00001FE0U
+
+#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_SHIFT   1U
+#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_WIDTH   4U
+#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_MASK    0X0000001EU
+
+#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_SHIFT   0U
+#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_MASK    0X00000001U
+
+#define XQSPIPSU_QSPIDMA_DST_STS_WTC	0xE000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET    0X0000070CU
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_SHIFT   25U
+#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_WIDTH   7U
+#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_MASK    0XFE000000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_SHIFT   24U
+#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_MASK    0X01000000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_SHIFT   23U
+#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_MASK    0X00800000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_SHIFT   22U
+#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_MASK    0X00400000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_SHIFT   10U
+#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_WIDTH   12U
+#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_MASK    0X003FFC00U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_SHIFT   2U
+#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_WIDTH   8U
+#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_MASK    0X000003FCU
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_SHIFT   1U
+#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_MASK    0X00000002U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_SHIFT   0U
+#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK    0X00000001U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL	0x403FFA00U
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET    0X00000714U
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_SHIFT   7U
+#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_MASK    0X00000080U
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_SHIFT   6U
+#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_MASK    0X00000040U
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_SHIFT   5U
+#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_MASK    0X00000020U
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_SHIFT   4U
+#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_MASK    0X00000010U
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_SHIFT   3U
+#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_MASK    0X00000008U
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_SHIFT   2U
+#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_MASK    0X00000004U
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_SHIFT   1U
+#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK    0X00000002U
+
+#define XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK    0X000000FCU
+#define XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK    0X000000FEU
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET    0X00000718U
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_SHIFT   7U
+#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_MASK    0X00000080U
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_SHIFT   6U
+#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_MASK    0X00000040U
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_SHIFT   5U
+#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_MASK    0X00000020U
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_SHIFT   4U
+#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_MASK    0X00000010U
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_SHIFT   3U
+#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_MASK    0X00000008U
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_SHIFT   2U
+#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_MASK    0X00000004U
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_SHIFT   1U
+#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK    0X00000002U
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET    0X0000071CU
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_SHIFT   7U
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_MASK    0X00000080U
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_SHIFT   6U
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_MASK    0X00000040U
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_SHIFT   5U
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_MASK    0X00000020U
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_SHIFT   4U
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_MASK    0X00000010U
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_SHIFT   3U
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_MASK    0X00000008U
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_SHIFT   2U
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_MASK    0X00000004U
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_SHIFT   1U
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_MASK    0X00000002U
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_OFFSET    0X00000720U
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_SHIFT   7U
+#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_MASK    0X00000080U
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_SHIFT   6U
+#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_MASK    0X00000040U
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_SHIFT   5U
+#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_MASK    0X00000020U
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_SHIFT   4U
+#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_MASK    0X00000010U
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_SHIFT   3U
+#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_MASK    0X00000008U
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_SHIFT   2U
+#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_MASK    0X00000004U
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_SHIFT   1U
+#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_MASK    0X00000002U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET    0X00000724U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_SHIFT   27U
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_MASK    0X08000000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_SHIFT   24U
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_WIDTH   3U
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_MASK    0X07000000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_SHIFT   22U
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_WIDTH   1U
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_MASK    0X00400000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_SHIFT   19U
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_WIDTH   3U
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_MASK    0X00380000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_SHIFT   16U
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_WIDTH   3U
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_MASK    0X00070000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_SHIFT   4U
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_WIDTH   12U
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_MASK    0X0000FFF0U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_SHIFT   0U
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_WIDTH   4U
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_MASK    0X0000000FU
+
+#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET    0X00000728U
+
+#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_SHIFT   0U
+#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_WIDTH   12U
+#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK    0X00000FFFU
+
+#define XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET    0X00000EFCU
+
+#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_SHIFT   0U
+#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_WIDTH   32U
+#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_MASK    0XFFFFFFFFU
+/** @} */
+
+/**
+ * @name XQSPIPSU Generic FIFO masks information
+ * Generic FIFO masks information
+ * @{
+ */
+/**
+ * Generic FIFO masks
+ */
+#define XQSPIPSU_GENFIFO_IMM_DATA_MASK	0xFFU
+#define XQSPIPSU_GENFIFO_DATA_XFER	0x100U
+#define XQSPIPSU_GENFIFO_EXP		0x200U
+#define XQSPIPSU_GENFIFO_MODE_SPI	0x400U
+#define XQSPIPSU_GENFIFO_MODE_DUALSPI	0x800U
+#define XQSPIPSU_GENFIFO_MODE_QUADSPI	0xC00U
+#define XQSPIPSU_GENFIFO_MODE_MASK	0xC00U	/* And with ~MASK first */
+#define XQSPIPSU_GENFIFO_CS_LOWER	0x1000U
+#define XQSPIPSU_GENFIFO_CS_UPPER	0x2000U
+#define XQSPIPSU_GENFIFO_BUS_LOWER	0x4000U
+#define XQSPIPSU_GENFIFO_BUS_UPPER	0x8000U
+#define XQSPIPSU_GENFIFO_BUS_BOTH	0xC000U	/* inverse is no bus */
+#define XQSPIPSU_GENFIFO_BUS_MASK	0xC000U	/* And with ~MASK first */
+#define XQSPIPSU_GENFIFO_TX		0x10000U	/* inverse is zero pump */
+#define XQSPIPSU_GENFIFO_RX		0x20000U	/* inverse is RX discard */
+#define XQSPIPSU_GENFIFO_STRIPE		0x40000U
+#define XQSPIPSU_GENFIFO_POLL		0x80000U
+/** @} */
+
+/**
+ * @name XQSPIPSU RX Data Delay Register information
+ * @{
+ */
+/**
+ * QSPI Data delay register
+ */
+#define XQSPIPSU_DATA_DLY_ADJ_OFFSET    0X000000F8U
+
+#define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_SHIFT   31U
+#define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_WIDTH   1U
+#define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_MASK    0X80000000U
+
+#define XQSPIPSU_DATA_DLY_ADJ_DLY_SHIFT   28U
+#define XQSPIPSU_DATA_DLY_ADJ_DLY_WIDTH   3U
+#define XQSPIPSU_DATA_DLY_ADJ_DLY_MASK    0X70000000U
+/** @} */
+
+/**
+ * @name TAPDLY Bypass register  information
+ * @{
+ */
+/**
+ * Tapdelay Bypass register
+ */
+
+#if defined versal
+#define IOU_TAPDLY_BYPASS_OFFSET 0X0000003CU
+#else
+#define IOU_TAPDLY_BYPASS_OFFSET 0X00000390U
+#endif
+
+#define IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 0X02U
+#if !defined (versal)
+#define IOU_TAPDLY_BYPASS_LQSPI_RX_WIDTH 0X01U
+#define IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004U
+#endif
+
+#if defined versal
+#define IOU_TAPDLY_RESET_STATE 0x4U
+#else
+#define IOU_TAPDLY_RESET_STATE 0x7U
+#endif
+/** @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XQspiPsu_In32 Xil_In32   /**< Read the  32 bit register value */
+#define XQspiPsu_Out32 Xil_Out32 /**< Write the 32 bit register value */
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XQspiPsu_ReadReg(u32 BaseAddress. s32 RegOffset)
+*
+******************************************************************************/
+#define XQspiPsu_ReadReg(BaseAddress, RegOffset) XQspiPsu_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XQspiPsu_WriteReg(u32 BaseAddress, s32 RegOffset,
+*		u32 RegisterValue)
+*
+******************************************************************************/
+#define XQspiPsu_WriteReg(BaseAddress, RegOffset, RegisterValue) XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /**< XQSPIPSU_H */
+/** @} */