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authorSebastian Huber <sebastian.huber@embedded-brains.de>2018-07-31 11:38:56 +0200
committerSebastian Huber <sebastian.huber@embedded-brains.de>2018-08-01 11:13:58 +0200
commita7cd4b737c1120382c4fae826c61306761ee0b23 (patch)
tree413c6160338509f5843936772975ab6ff5b8e7a1 /bsps/include
parentserial/ns16550: Use standard register names (diff)
downloadrtems-a7cd4b737c1120382c4fae826c61306761ee0b23.tar.bz2
serial/ns16550: Precision clock synthesizer
Set the FIFO control register while DLAB == 1 in the line control register. At least on the QorIQ T4240 the driver still works with the re-ordered FIFO control register access.
Diffstat (limited to 'bsps/include')
-rw-r--r--bsps/include/libchip/ns16550.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/bsps/include/libchip/ns16550.h b/bsps/include/libchip/ns16550.h
index 4f1b98bf0b..f053c8767f 100644
--- a/bsps/include/libchip/ns16550.h
+++ b/bsps/include/libchip/ns16550.h
@@ -69,6 +69,7 @@ typedef struct {
uint32_t clock;
uint32_t initial_baud;
bool has_fractional_divider_register;
+ bool has_precision_clock_synthesizer;
uint8_t modem_control;
uint8_t line_control;
uint32_t baud_divisor;