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authorSebastian Huber <sebastian.huber@embedded-brains.de>2022-03-14 15:41:42 +0100
committerSebastian Huber <sebastian.huber@embedded-brains.de>2022-04-06 09:48:52 +0200
commit518330069df68878934e0407a1c9e01036681d68 (patch)
tree2b5576cf03e73a1780941cae7a9c0401d3e5625a /bsps/include
parentbsps: Add gicv3_sgi_ppi_is_pending() (diff)
downloadrtems-518330069df68878934e0407a1c9e01036681d68.tar.bz2
bsps: Add gicv3_trigger_sgi()
Diffstat (limited to 'bsps/include')
-rw-r--r--bsps/include/dev/irq/arm-gicv3.h21
1 files changed, 21 insertions, 0 deletions
diff --git a/bsps/include/dev/irq/arm-gicv3.h b/bsps/include/dev/irq/arm-gicv3.h
index 0583fded0a..cfc8cd3499 100644
--- a/bsps/include/dev/irq/arm-gicv3.h
+++ b/bsps/include/dev/irq/arm-gicv3.h
@@ -166,6 +166,27 @@ static inline bool gicv3_sgi_ppi_is_pending(
return (sgi_ppi->icspispendr[0] & (1U << vector)) != 0;
}
+static inline void gicv3_trigger_sgi(
+ rtems_vector_number vector,
+ uint32_t targets
+)
+{
+#ifndef ARM_MULTILIB_ARCH_V4
+ uint64_t mpidr;
+#else
+ uint32_t mpidr;
+#endif
+ mpidr = READ_SR(MPIDR);
+ uint64_t value = ICC_SGIR_AFFINITY2(MPIDR_AFFINITY2_GET(mpidr))
+ | ICC_SGIR_INTID(vector)
+ | ICC_SGIR_AFFINITY1(MPIDR_AFFINITY1_GET(mpidr))
+ | ICC_SGIR_CPU_TARGET_LIST(targets);
+#ifndef ARM_MULTILIB_ARCH_V4
+ value |= ICC_SGIR_AFFINITY3(MPIDR_AFFINITY3_GET(mpidr));
+#endif
+ WRITE64_SR(ICC_SGI1, value);
+}
+
#ifdef __cplusplus
}
#endif