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authorKinsey Moore <kinsey.moore@oarcorp.com>2024-03-01 15:39:27 -0600
committerJoel Sherrill <joel@rtems.org>2024-03-11 12:09:59 -0500
commit33379dcfc40ecebfe255aeb4256906641a9fbcb1 (patch)
treed3a44b01015aa3c25e0c280bbf19020504411bb7 /bsps/include
parentaarch64/zynqmp: Fix build item BSP family (diff)
downloadrtems-33379dcfc40ecebfe255aeb4256906641a9fbcb1.tar.bz2
bsps/shared/xnandpsu: Add opportunistic page cache
Add an opportunistic page cache to the xnandpsu driver since it does not implement partial page reads and common filesystem access patterns perform multiple reads from the same page. This has been seen to provide a 10x speedup to read speeds and a 2x speedup on first initialization when used with JFFS2.
Diffstat (limited to 'bsps/include')
-rw-r--r--bsps/include/dev/nand/xnandpsu.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/bsps/include/dev/nand/xnandpsu.h b/bsps/include/dev/nand/xnandpsu.h
index 5c87be08c2..ac9496a745 100644
--- a/bsps/include/dev/nand/xnandpsu.h
+++ b/bsps/include/dev/nand/xnandpsu.h
@@ -217,6 +217,12 @@ extern "C" {
#define XNANDPSU_NVDDR_CLK_5 ((u16)100U * (u16)1000U * (u16)1000U)
#define XNANDPSU_MAX_TIMING_MODE 5
+
+#ifdef __rtems__
+#define XNANDPSU_PAGE_CACHE_UNAVAILABLE -2
+#define XNANDPSU_PAGE_CACHE_NONE -1
+#endif
+
/**
* The XNandPsu_Config structure contains configuration information for NAND
* controller.
@@ -390,6 +396,9 @@ typedef struct {
XNandPsu_EccCfg EccCfg; /**< ECC configuration */
XNandPsu_Geometry Geometry; /**< Flash geometry */
XNandPsu_Features Features; /**< ONFI features */
+#ifdef __rtems__
+ int32_t PartialDataPageIndex; /**< Cached page index */
+#endif
#ifdef __ICCARM__
u8 PartialDataBuf[XNANDPSU_MAX_PAGE_SIZE]; /**< Partial read/write buffer */
#pragma pack(pop)