diff options
author | Chris Johns <chrisj@rtems.org> | 2017-12-23 18:18:56 +1100 |
---|---|---|
committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-01-25 08:45:26 +0100 |
commit | 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9 (patch) | |
tree | 44759efe9374f13200a97e96d91bd9a2b7e5ce2a /bsps/include/rtems/zilog/z8530.h | |
parent | MAINTAINERS: Add myself to Write After Approval. (diff) | |
download | rtems-2afb22b7e1ebcbe40373ff7e0efae7d207c655a9.tar.bz2 |
Remove make preinstall
A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.
This has at least seven problems:
* The make preinstall step itself needs time and disk space.
* Errors in header files show up in the build tree copy. This makes it
hard for editors to open the right file to fix the error.
* There is no clear relationship between source and build tree header
files. This makes an audit of the build process difficult.
* The visibility of all header files in the build tree makes it
difficult to enforce API barriers. For example it is discouraged to
use BSP-specifics in the cpukit.
* An introduction of a new build system is difficult.
* Include paths specified by the -B option are system headers. This
may suppress warnings.
* The parallel build had sporadic failures on some hosts.
This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.
The new cpukit include directories are:
* cpukit/include
* cpukit/score/cpu/@RTEMS_CPU@/include
* cpukit/libnetworking
The new BSP include directories are:
* bsps/include
* bsps/@RTEMS_CPU@/include
* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include
There are build tree include directories for generated files.
The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.
The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.
Update #3254.
Diffstat (limited to 'bsps/include/rtems/zilog/z8530.h')
-rw-r--r-- | bsps/include/rtems/zilog/z8530.h | 97 |
1 files changed, 97 insertions, 0 deletions
diff --git a/bsps/include/rtems/zilog/z8530.h b/bsps/include/rtems/zilog/z8530.h new file mode 100644 index 0000000000..161b9a022c --- /dev/null +++ b/bsps/include/rtems/zilog/z8530.h @@ -0,0 +1,97 @@ +/** + * @file + * + * @brief Information Related to a Zilog Z8530 SCC Chip + * + * This include file defines information related to a Zilog Z8530 + * SCC Chip. It is a IO mapped part. + */ + +/* + * COPYRIGHT (c) 1989-2011. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_ZILOG_Z8530_H +#define _RTEMS_ZILOG_Z8530_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* macros */ + +#define VOL8( ptr ) ((volatile uint8_t *)(ptr)) + +#define Z8x30_STATE0 ( z8530 ) \ + { char *garbage; \ + (garbage) = *(VOL8(z8530)) \ + } + +#define Z8x30_WRITE_CONTROL( z8530, reg, data ) \ + *(VOL8(z8530)) = (reg); \ + *(VOL8(z8530)) = (data) + +#define Z8x30_READ_CONTROL( z8530, reg, data ) \ + *(VOL8(z8530)) = (reg); \ + (data) = *(VOL8(z8530)) + +#define Z8x30_WRITE_DATA( z8530, data ) \ + *(VOL8(z8530)) = (data); + +#define Z8x30_READ_DATA( z8530, data ) \ + (data) = *(VOL8(z8530)); + + +/* RR_0 Bit Definitions */ + +#define RR_0_TX_BUFFER_EMPTY 0x04 +#define RR_0_RX_DATA_AVAILABLE 0x01 + +/* read registers */ + +#define RR_0 0x00 +#define RR_1 0x01 +#define RR_2 0x02 +#define RR_3 0x03 +#define RR_4 0x04 +#define RR_5 0x05 +#define RR_6 0x06 +#define RR_7 0x07 +#define RR_8 0x08 +#define RR_9 0x09 +#define RR_10 0x0A +#define RR_11 0x0B +#define RR_12 0x0C +#define RR_13 0x0D +#define RR_14 0x0E +#define RR_15 0x0F + +/* write registers */ + +#define WR_0 0x00 +#define WR_1 0x01 +#define WR_2 0x02 +#define WR_3 0x03 +#define WR_4 0x04 +#define WR_5 0x05 +#define WR_6 0x06 +#define WR_7 0x07 +#define WR_8 0x08 +#define WR_9 0x09 +#define WR_10 0x0A +#define WR_11 0x0B +#define WR_12 0x0C +#define WR_13 0x0D +#define WR_14 0x0E +#define WR_15 0x0F + +#ifdef __cplusplus +} +#endif + +#endif |