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| author | Kinsey Moore <kinsey.moore@oarcorp.com> | 2022-07-14 18:10:45 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2022-07-21 12:26:35 -0500 |
| commit | 10ef7087f62bb83b36e8d9fc98e89e8f81d33fb9 (patch) | |
| tree | 44c96108608c504b8c31b46da15394f9e1e55790 /bsps/include/bsp/fatal.h | |
| parent | Support _REENT_THREAD_LOCAL Newlib configuration (diff) | |
| download | rtems-10ef7087f62bb83b36e8d9fc98e89e8f81d33fb9.tar.bz2 | |
aarch64: Use page table level 0
This alters the AArch64 page table generation and mapping code and MMU
configuration to use page table level 0 in addition to levels 1, 2, and
3. This allows the mapping of up to 48 bits of memory space and is the
maximum that can be mapped without relying on additional processor
extensions. Mappings are restricted based on the number of physical
address bits that the CPU supports.
Diffstat (limited to '')
| -rw-r--r-- | bsps/include/bsp/fatal.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/bsps/include/bsp/fatal.h b/bsps/include/bsp/fatal.h index 4df5f26455..e37e47d7ed 100644 --- a/bsps/include/bsp/fatal.h +++ b/bsps/include/bsp/fatal.h @@ -72,6 +72,7 @@ typedef enum { BSP_FATAL_CONSOLE_INSTALL_0, BSP_FATAL_CONSOLE_INSTALL_1, BSP_FATAL_CONSOLE_REGISTER_DEV_2, + BSP_FATAL_MMU_ADDRESS_INVALID, /* ARM fatal codes */ BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_INSTALL = BSP_FATAL_CODE_BLOCK(1), |