From 10ef7087f62bb83b36e8d9fc98e89e8f81d33fb9 Mon Sep 17 00:00:00 2001 From: Kinsey Moore Date: Thu, 14 Jul 2022 18:10:45 -0500 Subject: aarch64: Use page table level 0 This alters the AArch64 page table generation and mapping code and MMU configuration to use page table level 0 in addition to levels 1, 2, and 3. This allows the mapping of up to 48 bits of memory space and is the maximum that can be mapped without relying on additional processor extensions. Mappings are restricted based on the number of physical address bits that the CPU supports. --- bsps/include/bsp/fatal.h | 1 + 1 file changed, 1 insertion(+) (limited to 'bsps/include/bsp/fatal.h') diff --git a/bsps/include/bsp/fatal.h b/bsps/include/bsp/fatal.h index 4df5f26455..e37e47d7ed 100644 --- a/bsps/include/bsp/fatal.h +++ b/bsps/include/bsp/fatal.h @@ -72,6 +72,7 @@ typedef enum { BSP_FATAL_CONSOLE_INSTALL_0, BSP_FATAL_CONSOLE_INSTALL_1, BSP_FATAL_CONSOLE_REGISTER_DEV_2, + BSP_FATAL_MMU_ADDRESS_INVALID, /* ARM fatal codes */ BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_INSTALL = BSP_FATAL_CODE_BLOCK(1), -- cgit v1.2.3