bsps: Move startup files to bsps

Adjust build support files to new directory layout.

This patch is a part of the BSP source reorganization.

Update #3285.

9 files changed, 1096 insertions, 0 deletions

diff --git a/bsps/bfin/TLL6527M/start/bsp_specs b/bsps/bfin/TLL6527M/start/bsp_specs
new file mode 100644
index 0000000000..87638cc027
--- /dev/null
+++ b/bsps/bfin/TLL6527M/start/bsp_specs
@@ -0,0 +1,9 @@
+%rename endfile old_endfile
+%rename startfile old_startfile
+
+*startfile:
+%{!qrtems: %(old_startfile)} \
+%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}}
+
+*endfile:
+%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s}
diff --git a/bsps/bfin/TLL6527M/start/bspstart.c b/bsps/bfin/TLL6527M/start/bspstart.c
new file mode 100644
index 0000000000..4c8302a7ba
--- /dev/null
+++ b/bsps/bfin/TLL6527M/start/bspstart.c
@@ -0,0 +1,152 @@
+/*  bspstart.c for TLL6527M
+ *
+ *  This routine does the bulk of the system initialization.
+ */
+
+/*
+ * COPYRIGHT (c) 2010 by ECE Northeastern University.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license
+ */
+
+#include <bsp.h>
+#include <bsp/bootcard.h>
+#include <cplb.h>
+#include <bsp/interrupt.h>
+#include <libcpu/ebiuRegs.h>
+#include <rtems/sysinit.h>
+
+const unsigned int dcplbs_table[16][2] = {  
+  { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },
+  { 0xFF900000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },/* L1 Data B */
+  { 0xFF800000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },/* L1 Data A */
+  { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },
+
+  { 0x20300000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 3 */
+  { 0x20200000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 2  */
+  { 0x20100000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 1 */
+  { 0x20000000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, /* Async Memory Bank 0 */
+
+  { 0x02400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
+  { 0x02000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
+  { 0x00C00000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
+  { 0x00800000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
+  { 0x00400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
+  { 0x00000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
+
+  { 0xffffffff, 0xffffffff }/* end of section - termination */
+};
+
+
+const unsigned int _icplbs_table[16][2] = { 
+  { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_I_PAGE_MGMT | CPLB_I_PAGE_MGMT | 0x4) },
+  /* L1 Code */
+  { 0xEF000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* AREA DE BOOT */
+  { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },
+
+  { 0x20300000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Memory Bank 3 */
+  { 0x20200000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Bank 2 (Secnd) */
+  { 0x20100000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Bank 1 (Prim B) */
+  { 0x20000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Bank 0 (Prim A) */
+
+  { 0x02400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
+  { 0x02000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
+  { 0x00C00000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
+  { 0x00800000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
+  { 0x00400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
+  { 0x00000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
+
+  { 0xffffffff, 0xffffffff }/* end of section - termination */
+};
+
+/*
+ * Init_PLL
+ *
+ * Routine to initialize the PLL. The TLL6527M uses a 25 Mhz XTAL.
+ */
+static void Init_PLL (void)
+{
+  unsigned short msel = 0;
+  unsigned short ssel = 0;
+
+  msel = (unsigned short)( (float)CCLK/(float)CLKIN );
+  ssel = (unsigned short)( (float)(CLKIN*msel)/(float)SCLK);
+  
+  asm("cli r0;");
+
+  *((uint32_t*)SIC_IWR) = 0x1;
+
+  /* Configure PLL registers */
+  *((uint16_t*)PLL_DIV) = ssel;
+  msel = msel<<9;
+  *((uint16_t*)PLL_CTL) = msel;
+
+  /* Commands to set PLL values */
+  asm("idle;");
+  asm("sti r0;");
+}
+
+/*
+ * Init_EBIU
+ *
+ * Configure extern memory
+ */
+static void Init_EBIU (void)
+{
+  /* Check if SDRAM is already enabled */
+  if ( 0 != (*(uint16_t *)EBIU_SDSTAT & EBIU_SDSTAT_SDRS) ){
+    asm("ssync;");
+    /* RDIV = (100MHz*64ms)/8192-(6+3)=0x406 cycles */
+    *(uint16_t *)EBIU_SDRRC  = 0x3F6; /* SHould have been 0x306*/
+    *(uint16_t *)EBIU_SDBCTL = EBIU_SDBCTL_EBCAW_10 | EBIU_SDBCTL_EBSZ_64M |
+        EBIU_SDBCTL_EBE;
+    *(uint32_t *)EBIU_SDGCTL = 0x8491998d;
+    asm("ssync;");
+  } else {
+    /* SDRAm is already programmed */
+  }
+}
+
+/*
+ * Init_Flags
+ *
+ * Enable LEDs port
+ */
+static void Init_Flags(void)
+{
+  *((uint16_t*)PORTH_FER)    = 0x0;
+  *((uint16_t*)PORTH_MUX)    = 0x0;
+  *((uint16_t*)PORTHIO_DIR)  = 0x1<<15;
+  *((uint16_t*)PORTHIO_SET)  = 0x1<<15;
+}
+
+RTEMS_SYSINIT_ITEM(
+  bfin_interrupt_init,
+  RTEMS_SYSINIT_BSP_PRE_DRIVERS,
+  RTEMS_SYSINIT_ORDER_MIDDLE
+);
+
+void bsp_start( void )
+{
+  int i;
+
+  /* BSP Hardware Initialization*/
+  Init_RTC();   /* Blackfin Real Time Clock initialization */
+  Init_PLL();   /* PLL initialization */
+  Init_EBIU();  /* EBIU initialization */
+  Init_Flags(); /* GPIO initialization */
+
+  /*
+   *  Allocate the memory for the RTEMS Work Space.  This can come from
+   *  a variety of places: hard coded address, malloc'ed from outside
+   *  RTEMS world (e.g. simulator or primitive memory manager), or (as
+   *  typically done by stock BSPs) by subtracting the required amount
+   *  of work space from the last physical address on the CPU board.
+   */
+  for (i=5;i<16;i++) {
+    set_vector((rtems_isr_entry)bfin_null_isr, i, 1);
+  }
+
+}
diff --git a/bsps/bfin/TLL6527M/start/linkcmds b/bsps/bfin/TLL6527M/start/linkcmds
new file mode 100644
index 0000000000..93d2a85d82
--- /dev/null
+++ b/bsps/bfin/TLL6527M/start/linkcmds
@@ -0,0 +1,176 @@
+OUTPUT_FORMAT("elf32-bfin", "elf32-bfin",
+            "elf32-bfin")
+
+OUTPUT_ARCH(bfin)
+ENTRY(__start)
+STARTUP(start.o)
+
+/*
+ * Declare some sizes.
+ */
+_RamBase    = DEFINED(_RamBase)   ? _RamBase : 0x0;
+_RamSize    = DEFINED(_RamSize)   ? _RamSize : 0x04000000;
+_HeapSize   = DEFINED(_HeapSize)  ? _HeapSize : 0x10000;
+_StackSize  = DEFINED(_StackSize) ? _StackSize : 0x10000;
+
+MEMORY
+{
+      sdram(rwx)      : ORIGIN = 0x00000100, LENGTH = 0x04000000
+      
+      l1dataA(rwx)    : ORIGIN = 0xff800000, LENGTH = 0x00004000
+      l1dataAC(rwx)   : ORIGIN = 0xff804000, LENGTH = 0x00004000
+      l1dataB(rwx)    : ORIGIN = 0xff900000, LENGTH = 0x00004000
+      l1dataBC(rwx)   : ORIGIN = 0xff904000, LENGTH = 0x00004000
+      
+      l1code(rwx)     : ORIGIN = 0xffa00000, LENGTH = 0x0000C000
+      l1codeC(rwx)    : ORIGIN = 0xffa10000, LENGTH = 0x00004000
+      scratchpad(rwx) : ORIGIN = 0xffb00000, LENGTH = 0x00001000
+}
+
+SECTIONS
+{
+
+    .init          : 
+    { 
+    	*(.l1code)
+        KEEP (*(.init))
+    } > sdram   /*=0*/
+
+    .text :
+    {
+         CREATE_OBJECT_SYMBOLS
+        *(.text)
+        *(.rodata*)
+        *(.gnu.linkonce.r*)
+        
+        /*
+         * Special FreeBSD sysctl sections.
+         */
+        . = ALIGN (16);
+        ___start_set_sysctl_set = .;
+        *(set_sysctl_*);
+        ___stop_set_sysctl_set = ABSOLUTE(.);
+        *(set_domain_*);
+        *(set_pseudo_*);
+
+         _etext = .;
+
+        ___CTOR_LIST__ = .;
+        LONG((___CTOR_END__ - ___CTOR_LIST__) / 4 - 2)
+        *(.ctors)
+        LONG(0)
+        ___CTOR_END__ = .;
+        ___DTOR_LIST__ = .;
+        LONG((___DTOR_END__ - ___DTOR_LIST__) / 4 - 2)
+        *(.dtors)
+        LONG(0)
+        ___DTOR_END__ = .;         
+    } > sdram
+
+    .tdata : {
+        __TLS_Data_begin = .;
+        *(.tdata .tdata.* .gnu.linkonce.td.*)
+        __TLS_Data_end = .;
+    } > sdram
+
+    .tbss : {
+        __TLS_BSS_begin = .;
+        *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+        __TLS_BSS_end = .;
+    } > sdram
+
+    __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin;
+    __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin;
+    __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin;
+    __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin;
+    __TLS_Size = __TLS_BSS_end - __TLS_Data_begin;
+    __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
+    
+    .fini :
+    {
+        KEEP (*(.fini))
+    } > sdram  /*=0*/ 
+    
+    .data :
+    {
+        *(.data)
+        KEEP (*(SORT(.rtemsrwset.*)))
+        *(.jcr)
+        *(.gnu.linkonce.d*)
+        CONSTRUCTORS
+         _edata = .;
+    } > sdram
+
+    .eh_frame : { *(.eh_frame) } > sdram
+    .data1   : { *(.data1) } > sdram
+    .eh_frame : { *(.eh_frame) } > sdram
+    .gcc_except_table : { *(.gcc_except_table*) } > sdram
+
+    .rodata :
+    {
+        *(.rodata)
+        *(.rodata.*)
+        KEEP (*(SORT(.rtemsroset.*)))
+        *(.gnu.linkonce.r*)
+    } > sdram
+
+    
+    .bss :
+    {
+         _bss_start = .;
+        _clear_start = .;
+        *(.bss)
+        *(.gnu.linkonce.b.*)
+        *(COMMON)
+        . = ALIGN (64);
+        _stack_init = .;
+        . += _StackSize;
+        _clear_end = .;
+        _WorkAreaBase = .;
+         _end = .;
+         __end = .;
+    } > sdram
+    
+/* Debugging stuff follows */
+
+  /* Stabs debugging sections.  */
+  .stab 0 : { *(.stab) } 
+  .stabstr 0 : { *(.stabstr) } 
+  .stab.excl 0 : { *(.stab.excl) } 
+  .stab.exclstr 0 : { *(.stab.exclstr) }
+  .stab.index 0 : { *(.stab.index) } 
+  .stab.indexstr 0 : { *(.stab.indexstr) } 
+  .comment 0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) } 
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) } 
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) } 
+  /*.stack 0x80000 : { _stack = .; *(.stack) }*/
+  /* These must appear regardless of  .  */   
+}
+
+__HeapSize = _HeapSize;
+__edata = _edata;
+__etext = _etext;
+
diff --git a/bsps/bfin/bf537Stamp/start/bsp_specs b/bsps/bfin/bf537Stamp/start/bsp_specs
new file mode 100644
index 0000000000..87638cc027
--- /dev/null
+++ b/bsps/bfin/bf537Stamp/start/bsp_specs
@@ -0,0 +1,9 @@
+%rename endfile old_endfile
+%rename startfile old_startfile
+
+*startfile:
+%{!qrtems: %(old_startfile)} \
+%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}}
+
+*endfile:
+%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s}
diff --git a/bsps/bfin/bf537Stamp/start/bspstart.c b/bsps/bfin/bf537Stamp/start/bspstart.c
new file mode 100644
index 0000000000..ffc2d950c7
--- /dev/null
+++ b/bsps/bfin/bf537Stamp/start/bspstart.c
@@ -0,0 +1,229 @@
+/*  bspstart.c for bf537Stamp
+ *
+ *  This routine does the bulk of the system initialisation.
+ */
+
+/*
+ *  Copyright (c) 2006 by Atos Automacao Industrial Ltda.
+ *             written by Alain Schaefer <alain.schaefer@easc.ch>
+ *                    and Antonio Giovanini <antonio@atos.com.br>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+
+#include <bsp.h>
+#include <bsp/bootcard.h>
+#include <libcpu/bf537.h>
+#include <libcpu/ebiuRegs.h>
+#include <libcpu/gpioRegs.h>
+#include <libcpu/mmu.h>
+#include <libcpu/mmuRegs.h>
+#include <libcpu/interrupt.h>
+#include <rtems/sysinit.h>
+
+static bfin_mmu_config_t mmuRegions = {
+    /* instruction */
+    {
+        {(void *) 0x00000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x00400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x00800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x00c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x01000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x01400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x01800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x01c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x02000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x02400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x02800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x02c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x03000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0x20000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE},
+        {(void *) 0xff800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_NOCACHE},
+        {(void *) 0xffc00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_NOCACHE}
+    },
+    /* data */
+    {
+        {(void *) 0x00000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x00400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x00800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x00c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x01000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x01400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x01800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x01c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x02000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x02400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x02800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x02c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x03000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0x20000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK},
+        {(void *) 0xff800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_NOCACHE},
+        {(void *) 0xffc00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_NOCACHE}
+    }
+};
+
+static void initPLL(void);
+static void initEBIU(void);
+static void initGPIO(void);
+
+RTEMS_SYSINIT_ITEM(
+  bfin_interrupt_init,
+  RTEMS_SYSINIT_BSP_PRE_DRIVERS,
+  RTEMS_SYSINIT_ORDER_MIDDLE
+);
+
+void bsp_start(void)
+{
+  /* BSP Hardware Initialization*/
+
+  *(uint32_t volatile *) DMEM_CONTROL |= DMEM_CONTROL_PORT_PREF0;
+  *(uint32_t volatile *) DMEM_CONTROL &= ~DMEM_CONTROL_PORT_PREF1;
+  bfin_mmu_init(&mmuRegions);
+  rtems_cache_enable_instruction();
+  rtems_cache_enable_data();
+
+  Init_RTC();   /* Blackfin Real Time Clock initialization */
+
+  initPLL();   /* PLL initialization */
+  initEBIU();  /* EBIU initialization */
+  initGPIO();  /* GPIO initialization */
+}
+
+ /*
+  * initPLL
+  *
+  * Routine to initialize the PLL. The BF537 Stamp uses a 27 Mhz XTAL. BISON
+  * See "../bf537Stamp/include/bsp.h" for more information.
+  */
+
+static void initPLL(void) {
+
+#ifdef BISON
+  unsigned int n;
+
+  /* Configure PLL registers */
+  *((uint16_t*)PLL_LOCKCNT) = 0x1000;
+  *((uint16_t*)PLL_DIV) = PLL_CSEL|PLL_SSEL;
+  *((uint16_t*)PLL_CTL) = PLL_MSEL|PLL_DF;
+
+  /* Commands to set PLL values */
+  __asm__ ("cli r0;");
+  __asm__ ("idle;");
+  __asm__ ("sti r0;");
+
+  /* Delay for PLL stabilization */
+  for (n=0; n<200; n++) {}
+#endif
+
+}
+
+ /*
+  * initEBIU
+  *
+  * Configure extern memory
+  */
+
+static void initEBIU(void) {
+
+  /* by default the processor has priority over dma channels for access to
+     external memory.  this has been seen to result in dma unerruns on
+     ethernet transmit; it seems likely it could cause dma overruns on
+     ethernet receive as well.  setting the following bit gives the dma
+     channels priority over the cpu, fixing that problem.  unfortunately
+     we don't have finer grain control than that; all dma channels now
+     have priority over the cpu. */
+  *(uint16_t volatile *) EBIU_AMGCTL |= EBIU_AMGCTL_CDPRIO;
+
+#ifdef BISON
+  /* Configure FLASH */
+  *((uint32_t*)EBIU_AMBCTL0)  = 0x7bb07bb0L;
+  *((uint32_t*)EBIU_AMBCTL1)  = 0x7bb07bb0L;
+  *((uint16_t*)EBIU_AMGCTL)   = 0x000f;
+
+  /* Configure SDRAM
+  *((uint32_t*)EBIU_SDGCTL) = 0x0091998d;
+  *((uint16_t*)EBIU_SDBCTL) = 0x0013;
+  *((uint16_t*)EBIU_SDRRC)  = 0x0817;
+  */
+#endif
+}
+
+ /*
+  * initGPIO
+  *
+  * Enable LEDs port
+  */
+static void initGPIO(void) {
+#if (!BFIN_ON_SKYEYE)
+  *(uint16_t volatile *) PORT_MUX = 0;
+
+  /* port f bits 0, 1: uart0 tx, rx */
+  /*        bits 2 - 5: buttons */
+  /*        bits 6 - 11: leds */
+  *(uint16_t volatile *) PORTF_FER = 0x0003;
+  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_OFFSET) = 0x0000;
+  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_INEN_OFFSET) = 0x003c;
+  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_POLAR_OFFSET) = 0x0000;
+  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_EDGE_OFFSET) = 0x0000;
+  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_BOTH_OFFSET) = 0x0000;
+  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_MASKA_OFFSET) = 0x0000;
+  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_MASKB_OFFSET) = 0x0000;
+  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_DIR_OFFSET) = 0x0fc0;
+
+  *(uint16_t volatile *) PORTG_FER = 0x0000;
+  *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_OFFSET) = 0x0000;
+  *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_INEN_OFFSET) = 0x0000;
+  *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_POLAR_OFFSET) = 0x0000;
+  *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_EDGE_OFFSET) = 0x0000;
+  *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_BOTH_OFFSET) = 0x0000;
+  *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_MASKA_OFFSET) = 0x0000;
+  *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_MASKB_OFFSET) = 0x0000;
+  *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_DIR_OFFSET) = 0x0000;
+
+  /* port h bits 0 - 15: ethernet */
+  *(uint16_t volatile *) PORTH_FER = 0xffff;
+  *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_OFFSET) = 0x0000;
+  *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_INEN_OFFSET) = 0x0000;
+  *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_POLAR_OFFSET) = 0x0000;
+  *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_EDGE_OFFSET) = 0x0000;
+  *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_BOTH_OFFSET) = 0x0000;
+  *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_MASKA_OFFSET) = 0x0000;
+  *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_MASKB_OFFSET) = 0x0000;
+  *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_DIR_OFFSET) = 0x0000;
+#endif
+}
+
+/*
+ * Helper Function to use the EzKits LEDS.
+ * Can be used by the Application.
+ */
+void setLEDs(uint8_t value) {
+
+  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_CLEAR_OFFSET) =
+      (uint16_t) (~value & 0x3f) << 6;
+  *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_SET_OFFSET) =
+      (uint16_t) (value & 0x3f) << 6;
+}
+
+/*
+ * Helper Function to use the EzKits LEDS
+ */
+uint8_t getLEDs(void) {
+  uint16_t r;
+
+  r = *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_OFFSET);
+  return (uint8_t) ((r >> 6) & 0x3f);
+}
+
+uint8_t getButtons(void) {
+  uint16_t r;
+
+  r = *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_OFFSET);
+
+  return (uint8_t) ((r >> 2) & 0x0f);
+}
+
+
diff --git a/bsps/bfin/bf537Stamp/start/linkcmds b/bsps/bfin/bf537Stamp/start/linkcmds
new file mode 100644
index 0000000000..47888ff798
--- /dev/null
+++ b/bsps/bfin/bf537Stamp/start/linkcmds
@@ -0,0 +1,184 @@
+OUTPUT_FORMAT("elf32-bfin", "elf32-bfin",
+            "elf32-bfin")
+
+OUTPUT_ARCH(bfin)
+ENTRY(__start)
+STARTUP(start.o)
+
+/*
+ * Declare some sizes.
+ */
+_RamBase = DEFINED(_RamBase) ? _RamBase : 0x0;
+/* bf537stamp has 64MB ram, but dynamic mmu tables have not yet been
+   implemented.  there are not enough static entries to support 64MB
+   along with banks for io and flash, so waste some RAM at the end
+   to free up mmu entries. */
+_RamSize = DEFINED(_RamSize) ? _RamSize : 0x03400000;
+_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0;
+_StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
+
+MEMORY
+{
+      sdram(rwx)    : ORIGIN = 0x00001000, LENGTH = 0x03fff000
+/*
+      l1code(rwx)   : ORIGIN = 0xffa08000, LENGTH = 0x00008000
+      l1data(rwx)   : ORIGIN = 0xff804000, LENGTH = 0x00004000
+*/
+}
+
+SECTIONS
+{
+
+/*
+    .l1code        : 
+    { 
+*/
+        /*jump.o (.text)*/
+/*
+    } > l1code
+*/
+
+    .init          : 
+    { 
+        *(.start)
+        KEEP (*(.init))
+    } > sdram   /*=0*/
+
+    .text :
+    {
+         CREATE_OBJECT_SYMBOLS
+        *(.text)
+        *(.rodata*)
+        *(.gnu.linkonce.r*)
+        
+        /*
+         * Special FreeBSD sysctl sections.
+         */
+        . = ALIGN (16);
+        ___start_set_sysctl_set = .;
+        *(set_sysctl_*);
+        ___stop_set_sysctl_set = ABSOLUTE(.);
+        *(set_domain_*);
+        *(set_pseudo_*);
+
+         _etext = .;
+
+        ___CTOR_LIST__ = .;
+        LONG((___CTOR_END__ - ___CTOR_LIST__) / 4 - 2)
+        *(.ctors)
+        LONG(0)
+        ___CTOR_END__ = .;
+        ___DTOR_LIST__ = .;
+        LONG((___DTOR_END__ - ___DTOR_LIST__) / 4 - 2)
+        *(.dtors)
+        LONG(0)
+        ___DTOR_END__ = .;         
+    } > sdram
+
+    .tdata : {
+        __TLS_Data_begin = .;
+        *(.tdata .tdata.* .gnu.linkonce.td.*)
+        __TLS_Data_end = .;
+    } > sdram
+
+    .tbss : {
+        __TLS_BSS_begin = .;
+        *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+        __TLS_BSS_end = .;
+    } > sdram
+
+    __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin;
+    __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin;
+    __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin;
+    __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin;
+    __TLS_Size = __TLS_BSS_end - __TLS_Data_begin;
+    __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
+    
+    .fini :
+    {
+        KEEP (*(.fini))
+    } > sdram  /*=0*/ 
+    
+    .data :
+    {
+        *(.data)
+        KEEP (*(SORT(.rtemsrwset.*)))
+        *(.jcr)
+        *(.gnu.linkonce.d*)
+        CONSTRUCTORS
+         _edata = .;
+    } > sdram
+
+    .eh_frame : { *(.eh_frame) } > sdram
+    .data1   : { *(.data1) } > sdram
+    .eh_frame : { *(.eh_frame) } > sdram
+    .gcc_except_table : { *(.gcc_except_table*) } > sdram
+
+    .rodata :
+    {
+        *(.rodata)
+        *(.rodata.*)
+        KEEP (*(SORT(.rtemsroset.*)))
+        *(.gnu.linkonce.r*)
+    } > sdram
+
+    
+    .bss :
+    {
+         _bss_start = .;
+        _clear_start = .;
+        *(.bss)
+        *(.gnu.linkonce.b.*)
+        *(COMMON)
+        . = ALIGN (64);
+        _stack_init = .;
+        . += _StackSize;
+        _clear_end = .;
+        _WorkAreaBase = .;
+         _end = .;
+         __end = .;
+    } > sdram
+    
+/* Debugging stuff follows */
+
+  /* Stabs debugging sections.  */
+  .stab 0 : { *(.stab) } 
+  .stabstr 0 : { *(.stabstr) } 
+  .stab.excl 0 : { *(.stab.excl) } 
+  .stab.exclstr 0 : { *(.stab.exclstr) }
+  .stab.index 0 : { *(.stab.index) } 
+  .stab.indexstr 0 : { *(.stab.indexstr) } 
+  .comment 0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) } 
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) } 
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) } 
+  /*.stack 0x80000 : { _stack = .; *(.stack) }*/
+  /* These must appear regardless of  .  */   
+}
+
+__RamBase = _RamBase;
+__RamSize = _RamSize;
+__edata = _edata;
+__etext = _etext;
diff --git a/bsps/bfin/eZKit533/start/bsp_specs b/bsps/bfin/eZKit533/start/bsp_specs
new file mode 100644
index 0000000000..87638cc027
--- /dev/null
+++ b/bsps/bfin/eZKit533/start/bsp_specs
@@ -0,0 +1,9 @@
+%rename endfile old_endfile
+%rename startfile old_startfile
+
+*startfile:
+%{!qrtems: %(old_startfile)} \
+%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}}
+
+*endfile:
+%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s}
diff --git a/bsps/bfin/eZKit533/start/bspstart.c b/bsps/bfin/eZKit533/start/bspstart.c
new file mode 100644
index 0000000000..3579dd7766
--- /dev/null
+++ b/bsps/bfin/eZKit533/start/bspstart.c
@@ -0,0 +1,156 @@
+/*  bspstart.c for eZKit533
+ *
+ *  This routine does the bulk of the system initialisation.
+ */
+
+/*
+ *  Copyright (c) 2006 by Atos Automacao Industrial Ltda.
+ *             written by Alain Schaefer <alain.schaefer@easc.ch>
+ *                    and Antonio Giovanini <antonio@atos.com.br>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp.h>
+#include <bsp/bootcard.h>
+#include <cplb.h>
+#include <libcpu/interrupt.h>
+#include <rtems/sysinit.h>
+
+const unsigned int dcplbs_table[16][2] = {
+  { 0xFFA00000,   (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },
+  { 0xFF900000,   (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) }, /* L1 Data B */
+  { 0xFF800000,   (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) }, /* L1 Data A */
+  { 0xFFB00000,   (PAGE_SIZE_1MB | CPLB_DNOCACHE) },
+  { 0x20300000,   (PAGE_SIZE_1MB | CPLB_DNOCACHE) },      /* Async Memory Bank 3 */
+  { 0x20200000,   (PAGE_SIZE_1MB | CPLB_DNOCACHE) },      /* Async Memory Bank 2 (Secnd)  */
+  { 0x20100000,   (PAGE_SIZE_1MB | CPLB_DNOCACHE) },      /* Async Memory Bank 1 (Prim B) */
+  { 0x20000000,   (PAGE_SIZE_1MB | CPLB_DNOCACHE) },      /* Async Memory Bank 0 (Prim A) */
+
+  { 0x02400000,   (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
+  { 0x02000000,   (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
+  { 0x00C00000,   (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
+  { 0x00800000,   (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
+  { 0x00400000,   (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
+  { 0x00000000,   (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
+  { 0xffffffff, 0xffffffff }                 /* end of section - termination */
+
+};
+
+
+const unsigned int _icplbs_table[16][2] = {
+  { 0xFFA00000,   (PAGE_SIZE_1MB | CPLB_I_PAGE_MGMT | CPLB_I_PAGE_MGMT | 0x4) },  /* L1 Code */
+  { 0xEF000000,   (PAGE_SIZE_1MB | CPLB_INOCACHE) },      /* AREA DE BOOT */
+  { 0xFFB00000,   (PAGE_SIZE_1MB | CPLB_INOCACHE) },
+  { 0x20300000,   (PAGE_SIZE_1MB | CPLB_INOCACHE) },      /* Async Memory Bank 3 */
+  { 0x20200000,   (PAGE_SIZE_1MB | CPLB_INOCACHE) },      /* Async Memory Bank 2 (Secnd) */
+  { 0x20100000,   (PAGE_SIZE_1MB | CPLB_INOCACHE) },      /* Async Memory Bank 1 (Prim B) */
+  { 0x20000000,   (PAGE_SIZE_1MB | CPLB_INOCACHE) },      /* Async Memory Bank 0 (Prim A) */
+
+  { 0x02400000,   (PAGE_SIZE_4MB | CPLB_INOCACHE) },
+  { 0x02000000,   (PAGE_SIZE_4MB | CPLB_INOCACHE) },
+  { 0x00C00000,   (PAGE_SIZE_4MB | CPLB_INOCACHE) },
+  { 0x00800000,   (PAGE_SIZE_4MB | CPLB_INOCACHE) },
+  { 0x00400000,   (PAGE_SIZE_4MB | CPLB_INOCACHE) },
+  { 0x00000000,   (PAGE_SIZE_4MB | CPLB_INOCACHE) },
+  { 0xffffffff, 0xffffffff }               /* end of section - termination */
+
+};
+
+/*
+ * Init_PLL
+ *
+ * Routine to initialize the PLL. The Ezkit uses a 27 Mhz XTAL.
+ * See "../eZKit533/include/bsp.h" for more information.
+ */
+static void Init_PLL (void)
+{
+  unsigned int n;
+
+  /* Configure PLL registers */
+  *((uint16_t*)PLL_LOCKCNT) = 0x1000;
+  *((uint16_t*)PLL_DIV) = PLL_CSEL|PLL_SSEL;
+  *((uint16_t*)PLL_CTL) = PLL_MSEL|PLL_DF;
+
+  /* Commands to set PLL values */
+  __asm__ ("cli r0;");
+  __asm__ ("idle;");
+  __asm__ ("sti r0;");
+
+  /* Delay for PLL stabilization */
+  for (n=0; n<200; n++) {}
+}
+
+/*
+ * Init_EBIU
+ *
+ * Configure extern memory
+ */
+static void Init_EBIU (void)
+{
+  /* Configure FLASH */
+  *((uint32_t*)EBIU_AMBCTL0)  = 0x7bb07bb0L;
+  *((uint32_t*)EBIU_AMBCTL1)  = 0x7bb07bb0L;
+  *((uint16_t*)EBIU_AMGCTL)   = 0x000f;
+
+  /* Configure SDRAM
+  *((uint32_t*)EBIU_SDGCTL) = 0x0091998d;
+  *((uint16_t*)EBIU_SDBCTL) = 0x0013;
+  *((uint16_t*)EBIU_SDRRC)  = 0x0817;
+  */
+}
+
+/*
+ * Init_Flags
+ *
+ * Enable LEDs port
+ */
+static void Init_Flags(void)
+{
+  *((uint16_t*)FIO_INEN)    = 0x0100;
+  *((uint16_t*)FIO_DIR)     = 0x0000;
+  *((uint16_t*)FIO_EDGE)    = 0x0100;
+  *((uint16_t*)FIO_MASKA_D) = 0x0100;
+
+  *((uint8_t*)FlashA_PortB_Dir)  = 0x3f;
+  *((uint8_t*)FlashA_PortB_Data) = 0x00;
+}
+
+RTEMS_SYSINIT_ITEM(
+  bfin_interrupt_init,
+  RTEMS_SYSINIT_BSP_PRE_DRIVERS,
+  RTEMS_SYSINIT_ORDER_MIDDLE
+);
+
+void bsp_start( void )
+{
+  /* BSP Hardware Initialization*/
+  Init_RTC();   /* Blackfin Real Time Clock initialization */
+  Init_PLL();   /* PLL initialization */
+  Init_EBIU();  /* EBIU initialization */
+  Init_Flags(); /* GPIO initialization */
+
+  int i=0;
+  for (i=5;i<16;i++) {
+    set_vector((rtems_isr_entry)bfin_null_isr, i, 1);
+  }
+}
+
+/*
+ * Helper Function to use the EzKits LEDS.
+ * Can be used by the Application.
+ */
+void setLED (uint8_t value)
+{
+  *((uint8_t*)FlashA_PortB_Data) = value;
+}
+
+/*
+ * Helper Function to use the EzKits LEDS
+ */
+uint8_t getLED (void)
+{
+  return *((uint8_t*)FlashA_PortB_Data);
+}
diff --git a/bsps/bfin/eZKit533/start/linkcmds b/bsps/bfin/eZKit533/start/linkcmds
new file mode 100644
index 0000000000..e66a599e1f
--- /dev/null
+++ b/bsps/bfin/eZKit533/start/linkcmds
@@ -0,0 +1,172 @@
+OUTPUT_FORMAT("elf32-bfin", "elf32-bfin",
+            "elf32-bfin")
+
+OUTPUT_ARCH(bfin)
+ENTRY(__start)
+STARTUP(start.o)
+
+/*
+ * Declare some sizes.
+ */
+_RamBase = DEFINED(_RamBase) ? _RamBase : 0x0;
+_RamSize = DEFINED(_RamSize) ? _RamSize : 0x01000000;
+_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0;
+_StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
+
+MEMORY
+{
+      sdram(rwx)    : ORIGIN = 0x00001000, LENGTH = 0x01000000
+      l1code(rwx)   : ORIGIN = 0xffa08000, LENGTH = 0x00008000
+      l1data(rwx)   : ORIGIN = 0xff804000, LENGTH = 0x00004000
+}
+
+SECTIONS
+{
+
+    .l1code        : 
+    { 
+        /*jump.o (.text)*/
+    } > l1code
+
+    .init          : 
+    { 
+        KEEP (*(.init))
+    } > sdram   /*=0*/
+
+    .text :
+    {
+         CREATE_OBJECT_SYMBOLS
+        *(.text)
+        *(.rodata*)
+        *(.gnu.linkonce.r*)
+        
+        /*
+         * Special FreeBSD sysctl sections.
+         */
+        . = ALIGN (16);
+        ___start_set_sysctl_set = .;
+        *(set_sysctl_*);
+        ___stop_set_sysctl_set = ABSOLUTE(.);
+        *(set_domain_*);
+        *(set_pseudo_*);
+
+         _etext = .;
+
+        ___CTOR_LIST__ = .;
+        LONG((___CTOR_END__ - ___CTOR_LIST__) / 4 - 2)
+        *(.ctors)
+        LONG(0)
+        ___CTOR_END__ = .;
+        ___DTOR_LIST__ = .;
+        LONG((___DTOR_END__ - ___DTOR_LIST__) / 4 - 2)
+        *(.dtors)
+        LONG(0)
+        ___DTOR_END__ = .;         
+    } > sdram
+
+    .tdata : {
+        __TLS_Data_begin = .;
+        *(.tdata .tdata.* .gnu.linkonce.td.*)
+        __TLS_Data_end = .;
+    } > sdram
+
+    .tbss : {
+        __TLS_BSS_begin = .;
+        *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+        __TLS_BSS_end = .;
+    } > sdram
+
+    __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin;
+    __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin;
+    __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin;
+    __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin;
+    __TLS_Size = __TLS_BSS_end - __TLS_Data_begin;
+    __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
+    
+    .fini :
+    {
+        KEEP (*(.fini))
+    } > sdram  /*=0*/ 
+    
+    .data :
+    {
+        *(.data)
+        KEEP (*(SORT(.rtemsrwset.*)))
+        *(.jcr)
+        *(.gnu.linkonce.d*)
+        CONSTRUCTORS
+         _edata = .;
+    } > sdram
+
+    .eh_frame : { *(.eh_frame) } > sdram
+    .data1   : { *(.data1) } > sdram
+    .eh_frame : { *(.eh_frame) } > sdram
+    .gcc_except_table : { *(.gcc_except_table*) } > sdram
+
+    .rodata :
+    {
+        *(.rodata)
+        *(.rodata.*)
+        KEEP (*(SORT(.rtemsroset.*)))
+        *(.gnu.linkonce.r*)
+    } > sdram
+
+    
+    .bss :
+    {
+         _bss_start = .;
+        _clear_start = .;
+        *(.bss)
+        *(.gnu.linkonce.b.*)
+        *(COMMON)
+        . = ALIGN (64);
+        _stack_init = .;
+        . += _StackSize;
+        _clear_end = .;
+        _WorkAreaBase = .;
+         _end = .;
+         __end = .;
+    } > sdram
+    
+/* Debugging stuff follows */
+
+  /* Stabs debugging sections.  */
+  .stab 0 : { *(.stab) } 
+  .stabstr 0 : { *(.stabstr) } 
+  .stab.excl 0 : { *(.stab.excl) } 
+  .stab.exclstr 0 : { *(.stab.exclstr) }
+  .stab.index 0 : { *(.stab.index) } 
+  .stab.indexstr 0 : { *(.stab.indexstr) } 
+  .comment 0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) } 
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) } 
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) } 
+  /*.stack 0x80000 : { _stack = .; *(.stack) }*/
+  /* These must appear regardless of  .  */   
+}
+
+__HeapSize = _HeapSize;
+__edata = _edata;
+__etext = _etext;