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authorTyler Miller <tyler.miller@airbusus.com>2023-12-21 15:16:48 +0100
committerSebastian Huber <sebastian.huber@embedded-brains.de>2024-01-15 10:33:39 +0100
commitf7530be75c64bbe7818fdffe0ccc536ca425954c (patch)
tree0ce78bf8efb9c6e241ccf973bf6de8852cf555fd /bsps/arm
parentbsp/tms570: Remove reset source handling (diff)
downloadrtems-f7530be75c64bbe7818fdffe0ccc536ca425954c.tar.bz2
bsp/tms570: Honor DBGRST for TMS570LC4357
Update #4982.
Diffstat (limited to 'bsps/arm')
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h10
-rw-r--r--bsps/arm/tms570/start/bspstarthooks-hwinit.c12
2 files changed, 22 insertions, 0 deletions
diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h b/bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h
index 2407aeac8c..d5583a1cca 100644
--- a/bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h
+++ b/bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h
@@ -629,6 +629,16 @@ typedef struct{
/* field: WDRST - Watchdog reset flag. */
#define TMS570_SYS1_SYSESR_WDRST BSP_BIT32(13)
+#if TMS570_VARIANT == 4357
+
+/* field: DBGRST - Debug reset flag. */
+#define TMS570_SYS1_SYSESR_DBGRST BSP_BIT32(11)
+
+/* field: ICSTRST - Interconnect reset flag. */
+#define TMS570_SYS1_SYSESR_ICSTRST BSP_BIT32(7)
+
+#endif
+
/* field: CPURST - CPU reset flag. This bit is set when the CPU is reset. */
#define TMS570_SYS1_SYSESR_CPURST BSP_BIT32(5)
diff --git a/bsps/arm/tms570/start/bspstarthooks-hwinit.c b/bsps/arm/tms570/start/bspstarthooks-hwinit.c
index f17c3bf555..4b3fe2fbbf 100644
--- a/bsps/arm/tms570/start/bspstarthooks-hwinit.c
+++ b/bsps/arm/tms570/start/bspstarthooks-hwinit.c
@@ -101,8 +101,20 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void )
/*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
/*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
+#if TMS570_VARIANT == 4357
+ /*
+ * During code-loading/debug-resets SR[2][4] may get set (indicates double
+ * ECC error in internal RAM) ignore for now as its resolved with ESM
+ * init/reset below.
+ */
+ if ((TMS570_SYS1.SYSESR & TMS570_SYS1_SYSESR_DBGRST) == 0) {
+ for (;; ) {
+ } /* Wait */
+ }
+#else
for (;; ) {
} /* Wait */
+#endif
}
/* Initialize System - Clock, Flash settings with Efuse self check */