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authorKinsey Moore <kinsey.moore@oarcorp.com>2020-10-26 10:26:49 -0500
committerJoel Sherrill <joel@rtems.org>2020-12-02 18:51:40 -0600
commitf0859573f90b539e2a37857b129323c3d6211512 (patch)
tree02d9c0f6355ad697563c5b7b89dc791b6e585f1d /bsps/arm
parentdosfs: Fix Doxygen group placement (diff)
downloadrtems-f0859573f90b539e2a37857b129323c3d6211512.tar.bz2
bsps: Move zynq-uart to bsps/shared
This moves the zynq-uart driver from bsps/arm/shared to bsps/shared to accomodate use by AArch64 BSPs.
Diffstat (limited to 'bsps/arm')
-rw-r--r--bsps/arm/headers.am2
-rw-r--r--bsps/arm/include/bsp/zynq-uart-regs.h163
-rw-r--r--bsps/arm/include/bsp/zynq-uart.h78
-rw-r--r--bsps/arm/shared/serial/zynq-uart-polled.c184
-rw-r--r--bsps/arm/shared/serial/zynq-uart.c177
-rw-r--r--bsps/arm/xilinx-zynq/console/console-config.c2
-rw-r--r--bsps/arm/xilinx-zynq/console/console-init.c2
-rw-r--r--bsps/arm/xilinx-zynq/console/debug-console.c2
-rw-r--r--bsps/arm/xilinx-zynq/include/bsp.h2
-rw-r--r--bsps/arm/xilinx-zynq/start/bspreset.c2
-rw-r--r--bsps/arm/xilinx-zynqmp/console/console-config.c2
11 files changed, 6 insertions, 610 deletions
diff --git a/bsps/arm/headers.am b/bsps/arm/headers.am
index bff9a16fc8..a4d6dfa09e 100644
--- a/bsps/arm/headers.am
+++ b/bsps/arm/headers.am
@@ -31,8 +31,6 @@ include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/lpc-i2s.h
include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/lpc-lcd.h
include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/lpc-timer.h
include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/start.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/zynq-uart-regs.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/zynq-uart.h
include_libcpudir = $(includedir)/libcpu
include_libcpu_HEADERS =
diff --git a/bsps/arm/include/bsp/zynq-uart-regs.h b/bsps/arm/include/bsp/zynq-uart-regs.h
deleted file mode 100644
index 8b6e7d513b..0000000000
--- a/bsps/arm/include/bsp/zynq-uart-regs.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/**
- * @file
- * @ingroup zynq_uart_regs
- * @brief UART register definitions.
- */
-
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (C) 2013 embedded brains GmbH
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
- * @defgroup zynq_uart_regs UART Register Definitions
- * @ingroup zynq_uart
- * @brief UART Register Definitions
- * @{
- */
-
-#ifndef LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H
-#define LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H
-
-#include <bsp/utility.h>
-
-#define ZYNQ_UART_FIFO_DEPTH 64
-
-typedef struct zynq_uart {
- uint32_t control;
-#define ZYNQ_UART_CONTROL_STPBRK BSP_BIT32(8)
-#define ZYNQ_UART_CONTROL_STTBRK BSP_BIT32(7)
-#define ZYNQ_UART_CONTROL_RSTTO BSP_BIT32(6)
-#define ZYNQ_UART_CONTROL_TXDIS BSP_BIT32(5)
-#define ZYNQ_UART_CONTROL_TXEN BSP_BIT32(4)
-#define ZYNQ_UART_CONTROL_RXDIS BSP_BIT32(3)
-#define ZYNQ_UART_CONTROL_RXEN BSP_BIT32(2)
-#define ZYNQ_UART_CONTROL_TXRES BSP_BIT32(1)
-#define ZYNQ_UART_CONTROL_RXRES BSP_BIT32(0)
- uint32_t mode;
-#define ZYNQ_UART_MODE_CHMODE(val) BSP_FLD32(val, 8, 9)
-#define ZYNQ_UART_MODE_CHMODE_GET(reg) BSP_FLD32GET(reg, 8, 9)
-#define ZYNQ_UART_MODE_CHMODE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9)
-#define ZYNQ_UART_MODE_CHMODE_NORMAL 0x00U
-#define ZYNQ_UART_MODE_CHMODE_AUTO_ECHO 0x01U
-#define ZYNQ_UART_MODE_CHMODE_LOCAL_LOOPBACK 0x02U
-#define ZYNQ_UART_MODE_CHMODE_REMOTE_LOOPBACK 0x03U
-#define ZYNQ_UART_MODE_NBSTOP(val) BSP_FLD32(val, 6, 7)
-#define ZYNQ_UART_MODE_NBSTOP_GET(reg) BSP_FLD32GET(reg, 6, 7)
-#define ZYNQ_UART_MODE_NBSTOP_SET(reg, val) BSP_FLD32SET(reg, val, 6, 7)
-#define ZYNQ_UART_MODE_NBSTOP_STOP_1 0x00U
-#define ZYNQ_UART_MODE_NBSTOP_STOP_1_5 0x01U
-#define ZYNQ_UART_MODE_NBSTOP_STOP_2 0x02U
-#define ZYNQ_UART_MODE_PAR(val) BSP_FLD32(val, 3, 5)
-#define ZYNQ_UART_MODE_PAR_GET(reg) BSP_FLD32GET(reg, 3, 5)
-#define ZYNQ_UART_MODE_PAR_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
-#define ZYNQ_UART_MODE_PAR_EVEN 0x00U
-#define ZYNQ_UART_MODE_PAR_ODD 0x01U
-#define ZYNQ_UART_MODE_PAR_SPACE 0x02U
-#define ZYNQ_UART_MODE_PAR_MARK 0x03U
-#define ZYNQ_UART_MODE_PAR_NONE 0x04U
-#define ZYNQ_UART_MODE_CHRL(val) BSP_FLD32(val, 1, 2)
-#define ZYNQ_UART_MODE_CHRL_GET(reg) BSP_FLD32GET(reg, 1, 2)
-#define ZYNQ_UART_MODE_CHRL_SET(reg, val) BSP_FLD32SET(reg, val, 1, 2)
-#define ZYNQ_UART_MODE_CHRL_8 0x00U
-#define ZYNQ_UART_MODE_CHRL_7 0x02U
-#define ZYNQ_UART_MODE_CHRL_6 0x03U
-#define ZYNQ_UART_MODE_CLKS BSP_BIT32(0)
- uint32_t irq_en;
- uint32_t irq_dis;
- uint32_t irq_mask;
- uint32_t irq_sts;
-#define ZYNQ_UART_TOVR BSP_BIT32(12)
-#define ZYNQ_UART_TNFUL BSP_BIT32(11)
-#define ZYNQ_UART_TTRIG BSP_BIT32(10)
-#define ZYNQ_UART_DMSI BSP_BIT32(9)
-#define ZYNQ_UART_TIMEOUT BSP_BIT32(8)
-#define ZYNQ_UART_PARE BSP_BIT32(7)
-#define ZYNQ_UART_FRAME BSP_BIT32(6)
-#define ZYNQ_UART_ROVR BSP_BIT32(5)
-#define ZYNQ_UART_TFUL BSP_BIT32(4)
-#define ZYNQ_UART_TEMPTY BSP_BIT32(3)
-#define ZYNQ_UART_RFUL BSP_BIT32(2)
-#define ZYNQ_UART_REMPTY BSP_BIT32(1)
-#define ZYNQ_UART_RTRIG BSP_BIT32(0)
- uint32_t baud_rate_gen;
-#define ZYNQ_UART_BAUD_RATE_GEN_CD(val) BSP_FLD32(val, 0, 15)
-#define ZYNQ_UART_BAUD_RATE_GEN_CD_GET(reg) BSP_FLD32GET(reg, 0, 15)
-#define ZYNQ_UART_BAUD_RATE_GEN_CD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
- uint32_t rx_timeout;
-#define ZYNQ_UART_RX_TIMEOUT_RTO(val) BSP_FLD32(val, 0, 7)
-#define ZYNQ_UART_RX_TIMEOUT_RTO_GET(reg) BSP_FLD32GET(reg, 0, 7)
-#define ZYNQ_UART_RX_TIMEOUT_RTO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
- uint32_t rx_fifo_trg_lvl;
-#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG(val) BSP_FLD32(val, 0, 5)
-#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5)
-#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
- uint32_t modem_ctrl;
-#define ZYNQ_UART_MODEM_CTRL_FCM BSP_BIT32(5)
-#define ZYNQ_UART_MODEM_CTRL_RTS BSP_BIT32(1)
-#define ZYNQ_UART_MODEM_CTRL_DTR BSP_BIT32(0)
- uint32_t modem_sts;
-#define ZYNQ_UART_MODEM_STS_FCMS BSP_BIT32(8)
-#define ZYNQ_UART_MODEM_STS_DCD BSP_BIT32(7)
-#define ZYNQ_UART_MODEM_STS_RI BSP_BIT32(6)
-#define ZYNQ_UART_MODEM_STS_DSR BSP_BIT32(5)
-#define ZYNQ_UART_MODEM_STS_CTS BSP_BIT32(4)
-#define ZYNQ_UART_MODEM_STS_DDCD BSP_BIT32(3)
-#define ZYNQ_UART_MODEM_STS_TERI BSP_BIT32(2)
-#define ZYNQ_UART_MODEM_STS_DDSR BSP_BIT32(1)
-#define ZYNQ_UART_MODEM_STS_DCTS BSP_BIT32(0)
- uint32_t channel_sts;
-#define ZYNQ_UART_CHANNEL_STS_TNFUL BSP_BIT32(14)
-#define ZYNQ_UART_CHANNEL_STS_TTRIG BSP_BIT32(13)
-#define ZYNQ_UART_CHANNEL_STS_FDELT BSP_BIT32(12)
-#define ZYNQ_UART_CHANNEL_STS_TACTIVE BSP_BIT32(11)
-#define ZYNQ_UART_CHANNEL_STS_RACTIVE BSP_BIT32(10)
-#define ZYNQ_UART_CHANNEL_STS_TFUL BSP_BIT32(4)
-#define ZYNQ_UART_CHANNEL_STS_TEMPTY BSP_BIT32(3)
-#define ZYNQ_UART_CHANNEL_STS_RFUL BSP_BIT32(2)
-#define ZYNQ_UART_CHANNEL_STS_REMPTY BSP_BIT32(1)
-#define ZYNQ_UART_CHANNEL_STS_RTRIG BSP_BIT32(0)
- uint32_t tx_rx_fifo;
-#define ZYNQ_UART_TX_RX_FIFO_FIFO(val) BSP_FLD32(val, 0, 7)
-#define ZYNQ_UART_TX_RX_FIFO_FIFO_GET(reg) BSP_FLD32GET(reg, 0, 7)
-#define ZYNQ_UART_TX_RX_FIFO_FIFO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
- uint32_t baud_rate_div;
-#define ZYNQ_UART_BAUD_RATE_DIV_BDIV(val) BSP_FLD32(val, 0, 7)
-#define ZYNQ_UART_BAUD_RATE_DIV_BDIV_GET(reg) BSP_FLD32GET(reg, 0, 7)
-#define ZYNQ_UART_BAUD_RATE_DIV_BDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
- uint32_t flow_delay;
-#define ZYNQ_UART_FLOW_DELAY_FDEL(val) BSP_FLD32(val, 0, 5)
-#define ZYNQ_UART_FLOW_DELAY_FDEL_GET(reg) BSP_FLD32GET(reg, 0, 5)
-#define ZYNQ_UART_FLOW_DELAY_FDEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
- uint32_t reserved_3c[2];
- uint32_t tx_fifo_trg_lvl;
-#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG(val) BSP_FLD32(val, 0, 5)
-#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5)
-#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
-} zynq_uart;
-
-/** @} */
-
-#endif /* LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H */
diff --git a/bsps/arm/include/bsp/zynq-uart.h b/bsps/arm/include/bsp/zynq-uart.h
deleted file mode 100644
index 20c3c9b653..0000000000
--- a/bsps/arm/include/bsp/zynq-uart.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/**
- * @file
- * @ingroup zynq_uart
- * @brief UART support.
- */
-
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (C) 2013, XXX embedded brains GmbH
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef LIBBSP_ARM_XILINX_ZYNQ_UART_H
-#define LIBBSP_ARM_XILINX_ZYNQ_UART_H
-
-#include <rtems/termiostypes.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/**
- * @defgroup zynq_uart UART Support
- * @ingroup RTEMSBSPsARMZynq
- * @brief UART Support
- */
-
-typedef struct {
- rtems_termios_device_context base;
- volatile struct zynq_uart *regs;
- bool transmitting;
- rtems_vector_number irq;
-} zynq_uart_context;
-
-extern const rtems_termios_device_handler zynq_uart_handler;
-
-#define ZYNQ_UART_DEFAULT_BAUD 115200
-
-void zynq_uart_initialize(rtems_termios_device_context *base);
-
-int zynq_uart_read_polled(rtems_termios_device_context *base);
-
-void zynq_uart_write_polled(
- rtems_termios_device_context *base,
- char c
-);
-
-/**
- * Flush TX FIFO and wait until it is empty. Used in bsp_reset.
- */
-void zynq_uart_reset_tx_flush(zynq_uart_context *ctx);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* LIBBSP_ARM_XILINX_ZYNQ_UART_H */
diff --git a/bsps/arm/shared/serial/zynq-uart-polled.c b/bsps/arm/shared/serial/zynq-uart-polled.c
deleted file mode 100644
index e6f478ee07..0000000000
--- a/bsps/arm/shared/serial/zynq-uart-polled.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (C) 2013, 2017 embedded brains GmbH
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <bsp/zynq-uart.h>
-#include <bsp/zynq-uart-regs.h>
-
-#include <bspopts.h>
-
-/*
- * Make weak and let the user override.
- */
-uint32_t zynq_uart_input_clock(void) __attribute__ ((weak));
-
-uint32_t zynq_uart_input_clock(void)
-{
- return ZYNQ_CLOCK_UART;
-}
-
-static int zynq_cal_baud_rate(uint32_t baudrate,
- uint32_t* brgr,
- uint32_t* bauddiv,
- uint32_t modereg)
-{
- uint32_t brgr_value; /* Calculated value for baud rate generator */
- uint32_t calcbaudrate; /* Calculated baud rate */
- uint32_t bauderror; /* Diff between calculated and requested baud rate */
- uint32_t best_error = 0xFFFFFFFF;
- uint32_t percenterror;
- uint32_t bdiv;
- uint32_t inputclk = zynq_uart_input_clock();
-
- /*
- * Make sure the baud rate is not impossilby large.
- * Fastest possible baud rate is Input Clock / 2.
- */
- if ((baudrate * 2) > inputclk) {
- return -1;
- }
- /*
- * Check whether the input clock is divided by 8
- */
- if(modereg & ZYNQ_UART_MODE_CLKS) {
- inputclk = inputclk / 8;
- }
-
- /*
- * Determine the Baud divider. It can be 4to 254.
- * Loop through all possible combinations
- */
- for (bdiv = 4; bdiv < 255; bdiv++) {
-
- /*
- * Calculate the value for BRGR register
- */
- brgr_value = inputclk / (baudrate * (bdiv + 1));
-
- /*
- * Calculate the baud rate from the BRGR value
- */
- calcbaudrate = inputclk/ (brgr_value * (bdiv + 1));
-
- /*
- * Avoid unsigned integer underflow
- */
- if (baudrate > calcbaudrate) {
- bauderror = baudrate - calcbaudrate;
- }
- else {
- bauderror = calcbaudrate - baudrate;
- }
-
- /*
- * Find the calculated baud rate closest to requested baud rate.
- */
- if (best_error > bauderror) {
- *brgr = brgr_value;
- *bauddiv = bdiv;
- best_error = bauderror;
- }
- }
-
- /*
- * Make sure the best error is not too large.
- */
- percenterror = (best_error * 100) / baudrate;
-#define XUARTPS_MAX_BAUD_ERROR_RATE 3 /* max % error allowed */
- if (XUARTPS_MAX_BAUD_ERROR_RATE < percenterror) {
- return -1;
- }
-
- return 0;
-}
-
-void zynq_uart_initialize(rtems_termios_device_context *base)
-{
- zynq_uart_context *ctx = (zynq_uart_context *) base;
- volatile zynq_uart *regs = ctx->regs;
- uint32_t brgr = 0x3e;
- uint32_t bauddiv = 0x6;
-
- zynq_uart_reset_tx_flush(ctx);
-
- zynq_cal_baud_rate(ZYNQ_UART_DEFAULT_BAUD, &brgr, &bauddiv, regs->mode);
-
- regs->control &= ~(ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN);
- regs->control = ZYNQ_UART_CONTROL_RXDIS
- | ZYNQ_UART_CONTROL_TXDIS
- | ZYNQ_UART_CONTROL_RXRES
- | ZYNQ_UART_CONTROL_TXRES;
- regs->mode = ZYNQ_UART_MODE_CHMODE(ZYNQ_UART_MODE_CHMODE_NORMAL)
- | ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_NONE)
- | ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_8);
- regs->baud_rate_gen = ZYNQ_UART_BAUD_RATE_GEN_CD(brgr);
- regs->baud_rate_div = ZYNQ_UART_BAUD_RATE_DIV_BDIV(bauddiv);
- regs->rx_fifo_trg_lvl = ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG(0);
- regs->rx_timeout = ZYNQ_UART_RX_TIMEOUT_RTO(0);
- regs->control = ZYNQ_UART_CONTROL_RXEN
- | ZYNQ_UART_CONTROL_TXEN
- | ZYNQ_UART_CONTROL_RSTTO;
-}
-
-int zynq_uart_read_polled(rtems_termios_device_context *base)
-{
- zynq_uart_context *ctx = (zynq_uart_context *) base;
- volatile zynq_uart *regs = ctx->regs;
-
- if ((regs->channel_sts & ZYNQ_UART_CHANNEL_STS_REMPTY) != 0) {
- return -1;
- } else {
- return ZYNQ_UART_TX_RX_FIFO_FIFO_GET(regs->tx_rx_fifo);
- }
-}
-
-void zynq_uart_write_polled(
- rtems_termios_device_context *base,
- char c
-)
-{
- zynq_uart_context *ctx = (zynq_uart_context *) base;
- volatile zynq_uart *regs = ctx->regs;
-
- while ((regs->channel_sts & ZYNQ_UART_CHANNEL_STS_TFUL) != 0) {
- /* Wait */
- }
-
- regs->tx_rx_fifo = ZYNQ_UART_TX_RX_FIFO_FIFO(c);
-}
-
-void zynq_uart_reset_tx_flush(zynq_uart_context *ctx)
-{
- volatile zynq_uart *regs = ctx->regs;
- int c = 4;
-
- while (c-- > 0)
- zynq_uart_write_polled(&ctx->base, '\r');
-
- while ((regs->channel_sts & ZYNQ_UART_CHANNEL_STS_TEMPTY) == 0) {
- /* Wait */
- }
-}
diff --git a/bsps/arm/shared/serial/zynq-uart.c b/bsps/arm/shared/serial/zynq-uart.c
deleted file mode 100644
index fc670441b8..0000000000
--- a/bsps/arm/shared/serial/zynq-uart.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (C) 2013, 2017 embedded brains GmbH
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <bsp/zynq-uart.h>
-#include <bsp/zynq-uart-regs.h>
-#include <bsp/irq.h>
-
-#include <bspopts.h>
-
-#ifdef ZYNQ_CONSOLE_USE_INTERRUPTS
-static void zynq_uart_interrupt(void *arg)
-{
- rtems_termios_tty *tty = arg;
- zynq_uart_context *ctx = rtems_termios_get_device_context(tty);
- volatile zynq_uart *regs = ctx->regs;
- uint32_t channel_sts;
-
- if ((regs->irq_sts & (ZYNQ_UART_TIMEOUT | ZYNQ_UART_RTRIG)) != 0) {
- regs->irq_sts = ZYNQ_UART_TIMEOUT | ZYNQ_UART_RTRIG;
-
- do {
- char c = (char) ZYNQ_UART_TX_RX_FIFO_FIFO_GET(regs->tx_rx_fifo);
-
- rtems_termios_enqueue_raw_characters(tty, &c, 1);
-
- channel_sts = regs->channel_sts;
- } while ((channel_sts & ZYNQ_UART_CHANNEL_STS_REMPTY) == 0);
- } else {
- channel_sts = regs->channel_sts;
- }
-
- if (ctx->transmitting && (channel_sts & ZYNQ_UART_CHANNEL_STS_TEMPTY) != 0) {
- rtems_termios_dequeue_characters(tty, 1);
- }
-}
-#endif
-
-static bool zynq_uart_first_open(
- rtems_termios_tty *tty,
- rtems_termios_device_context *base,
- struct termios *term,
- rtems_libio_open_close_args_t *args
-)
-{
-#ifdef ZYNQ_CONSOLE_USE_INTERRUPTS
- zynq_uart_context *ctx = (zynq_uart_context *) base;
- volatile zynq_uart *regs = ctx->regs;
- rtems_status_code sc;
-#endif
-
- rtems_termios_set_initial_baud(tty, ZYNQ_UART_DEFAULT_BAUD);
- zynq_uart_initialize(base);
-
-#ifdef ZYNQ_CONSOLE_USE_INTERRUPTS
- regs->rx_timeout = 32;
- regs->rx_fifo_trg_lvl = ZYNQ_UART_FIFO_DEPTH / 2;
- regs->irq_dis = 0xffffffff;
- regs->irq_sts = 0xffffffff;
- regs->irq_en = ZYNQ_UART_RTRIG | ZYNQ_UART_TIMEOUT;
- sc = rtems_interrupt_handler_install(
- ctx->irq,
- "UART",
- RTEMS_INTERRUPT_SHARED,
- zynq_uart_interrupt,
- tty
- );
- if (sc != RTEMS_SUCCESSFUL) {
- return false;
- }
-#endif
-
- return true;
-}
-
-#ifdef ZYNQ_CONSOLE_USE_INTERRUPTS
-static void zynq_uart_last_close(
- rtems_termios_tty *tty,
- rtems_termios_device_context *base,
- rtems_libio_open_close_args_t *args
-)
-{
- zynq_uart_context *ctx = (zynq_uart_context *) base;
-
- rtems_interrupt_handler_remove(ctx->irq, zynq_uart_interrupt, tty);
-}
-#endif
-
-static void zynq_uart_write_support(
- rtems_termios_device_context *base,
- const char *buf,
- size_t len
-)
-{
-#ifdef ZYNQ_CONSOLE_USE_INTERRUPTS
- zynq_uart_context *ctx = (zynq_uart_context *) base;
- volatile zynq_uart *regs = ctx->regs;
-
- if (len > 0) {
- ctx->transmitting = true;
- regs->irq_sts = ZYNQ_UART_TEMPTY;
- regs->irq_en = ZYNQ_UART_TEMPTY;
- regs->tx_rx_fifo = ZYNQ_UART_TX_RX_FIFO_FIFO(buf[0]);
- } else {
- ctx->transmitting = false;
- regs->irq_dis = ZYNQ_UART_TEMPTY;
- }
-#else
- ssize_t i;
-
- for (i = 0; i < len; ++i) {
- zynq_uart_write_polled(base, buf[i]);
- }
-#endif
-}
-
-static bool zynq_uart_set_attributes(
- rtems_termios_device_context *context,
- const struct termios *term
-)
-{
-#if 0
- volatile zynq_uart *regs = zynq_uart_get_regs(minor);
- uint32_t brgr = 0;
- uint32_t bauddiv = 0;
- int rc;
-
- rc = zynq_cal_baud_rate(115200, &brgr, &bauddiv, regs->mode);
- if (rc != 0)
- return rc;
-
- regs->control &= ~(ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN);
- regs->baud_rate_gen = ZYNQ_UART_BAUD_RATE_GEN_CD(brgr);
- regs->baud_rate_div = ZYNQ_UART_BAUD_RATE_DIV_BDIV(bauddiv);
- regs->control |= ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN;
-
- return true;
-#else
- return false;
-#endif
-}
-
-const rtems_termios_device_handler zynq_uart_handler = {
- .first_open = zynq_uart_first_open,
- .set_attributes = zynq_uart_set_attributes,
- .write = zynq_uart_write_support,
-#ifdef ZYNQ_CONSOLE_USE_INTERRUPTS
- .last_close = zynq_uart_last_close,
- .mode = TERMIOS_IRQ_DRIVEN
-#else
- .poll_read = zynq_uart_read_polled,
- .mode = TERMIOS_POLLED
-#endif
-};
diff --git a/bsps/arm/xilinx-zynq/console/console-config.c b/bsps/arm/xilinx-zynq/console/console-config.c
index 7e28716bbe..0581247a2d 100644
--- a/bsps/arm/xilinx-zynq/console/console-config.c
+++ b/bsps/arm/xilinx-zynq/console/console-config.c
@@ -26,7 +26,7 @@
*/
#include <bsp/irq.h>
-#include <bsp/zynq-uart.h>
+#include <dev/serial/zynq-uart.h>
zynq_uart_context zynq_uart_instances[2] = {
{
diff --git a/bsps/arm/xilinx-zynq/console/console-init.c b/bsps/arm/xilinx-zynq/console/console-init.c
index 72ba27006c..a3659e3906 100644
--- a/bsps/arm/xilinx-zynq/console/console-init.c
+++ b/bsps/arm/xilinx-zynq/console/console-init.c
@@ -28,7 +28,7 @@
#include <rtems/console.h>
#include <bsp.h>
-#include <bsp/zynq-uart.h>
+#include <dev/serial/zynq-uart.h>
rtems_status_code console_initialize(
rtems_device_major_number major,
diff --git a/bsps/arm/xilinx-zynq/console/debug-console.c b/bsps/arm/xilinx-zynq/console/debug-console.c
index 809fd6830d..0e9b756f30 100644
--- a/bsps/arm/xilinx-zynq/console/debug-console.c
+++ b/bsps/arm/xilinx-zynq/console/debug-console.c
@@ -29,7 +29,7 @@
#include <rtems/sysinit.h>
#include <bsp.h>
-#include <bsp/zynq-uart.h>
+#include <dev/serial/zynq-uart.h>
#include <bspopts.h>
diff --git a/bsps/arm/xilinx-zynq/include/bsp.h b/bsps/arm/xilinx-zynq/include/bsp.h
index 6c2759ce50..fde8d03130 100644
--- a/bsps/arm/xilinx-zynq/include/bsp.h
+++ b/bsps/arm/xilinx-zynq/include/bsp.h
@@ -54,7 +54,7 @@
#include <bsp/default-initial-extension.h>
#include <bsp/start.h>
-#include <bsp/zynq-uart.h>
+#include <dev/serial/zynq-uart.h>
#ifdef __cplusplus
extern "C" {
diff --git a/bsps/arm/xilinx-zynq/start/bspreset.c b/bsps/arm/xilinx-zynq/start/bspreset.c
index e0c81ca2ef..3e797a137e 100644
--- a/bsps/arm/xilinx-zynq/start/bspreset.c
+++ b/bsps/arm/xilinx-zynq/start/bspreset.c
@@ -27,7 +27,7 @@
#include <bsp.h>
#include <bsp/bootcard.h>
-#include <bsp/zynq-uart.h>
+#include <dev/serial/zynq-uart.h>
void bsp_reset(void)
{
diff --git a/bsps/arm/xilinx-zynqmp/console/console-config.c b/bsps/arm/xilinx-zynqmp/console/console-config.c
index a525f9c565..fb0b003c83 100644
--- a/bsps/arm/xilinx-zynqmp/console/console-config.c
+++ b/bsps/arm/xilinx-zynqmp/console/console-config.c
@@ -35,7 +35,7 @@
#include <rtems/sysinit.h>
#include <bsp/irq.h>
-#include <bsp/zynq-uart.h>
+#include <dev/serial/zynq-uart.h>
#include <bspopts.h>