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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-04-25 15:06:08 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-04-26 07:17:57 +0200 |
| commit | eb36d1198cdf9dc1e2f776ef6e1e38755f6d13c5 (patch) | |
| tree | 14177ad7a58c06a3c537d1e55dae7bc369a1a4b9 /bsps/arm | |
| parent | bsps: Remove unmaintained times files (diff) | |
| download | rtems-eb36d1198cdf9dc1e2f776ef6e1e38755f6d13c5.tar.bz2 | |
bsps: Move documentation, etc. files to bsps
This patch is a part of the BSP source reorganization.
Update #3285.
Diffstat (limited to 'bsps/arm')
31 files changed, 1485 insertions, 0 deletions
diff --git a/bsps/arm/altera-cyclone-v/README b/bsps/arm/altera-cyclone-v/README new file mode 100644 index 0000000000..658fe77255 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/README @@ -0,0 +1,44 @@ +Overview +-------- +Evaluation board for this BSP: +- Cyclone V SoC FPGA Development Kit +- DK-DEV-5CSXC6N/ES-0L + +RTC +--- +The evaluation board contains a DS1339C RTC connected to I2C0. To use it you +have to set the following options: + + #define CONFIGURE_APPLICATION_NEEDS_RTC_DRIVER + #define CONFIGURE_BSP_PREREQUISITE_DRIVERS I2C_DRIVER_TABLE_ENTRY + +Additional there has to be one free file descriptor to access the i2c. Set the +CONFIGURE_LIBIO_MAXIMUM_FILE_DESCRIPTORS accordingly. + +Network +------- +The default PHY address can be overwritten by the application. To do this, the +drv_ctrl pointer of the rtems_bsdnet_ifconfig structure should point to a +dwmac_ifconfig_drv_ctrl object with the appropriate settings before the +rtems_bsdnet_initialize_network() is called. E.g.: + + #include <libchip/dwmac.h> + #include <bsp.h> + + static dwmac_ifconfig_drv_ctrl drv_ctrl = { + .phy_addr = 1 + }; + + ... + + static struct rtems_bsdnet_ifconfig some_ifconfig = { + .name = RTEMS_BSP_NETWORK_DRIVER_NAME, + .attach = RTEMS_BSP_NETWORK_DRIVER_ATTACH, + .drv_ctrl = &drv_ctrl + }; + + ... + + rtems_bsdnet_initialize_network(); + +If drv_ctrl is the NULL pointer, default values will be used instead. diff --git a/bsps/arm/atsam/README b/bsps/arm/atsam/README new file mode 100644 index 0000000000..2ebaa726c8 --- /dev/null +++ b/bsps/arm/atsam/README @@ -0,0 +1,92 @@ +Board support package for the Atmel SAM V71/V70/E70/S70 chip platform. + +The BSP is customized to a particular board/chip variant by means of configure +command line options. + +Use --enable-chip=XYZ to select the chip variant where XYZ is one of same70j19, +same70j20, same70j21, same70n19, same70n20, same70n21, same70q19, same70q20, +same70q21, sams70j19, sams70j20, sams70j21, sams70n19, sams70n20, sams70n21, +sams70q19, sams70q20, sams70q21, samv71j19, samv71j20, samv71j21, samv71n19, +samv71n20, samv71n21, samv71q19, samv71q20 and samv71q21. By default the BSP +uses the ATSAMV71Q21 chip. Not all variants are tested. + +Use --enable-sdram=XYZ to select the SDRAM variant where XYZ is one of +is42s16100e-7bli and is42s16320f-7bl. Not all variants are tested with all +controller and speed combinations. + +Use BOARD_MAINOSC=XYZ to set the main oscillator frequency in Hz (default +12MHz). + +Use ATSAM_MCK=XYZ to set the MCK frequency that should be used. The default case +(123000000) enables operation of an external SDRAM on the SAMv71 Explained +evaluation kit. Some other configurations (e.g. 150MHz) would be too fast on +that board. + +Your application can also overwrite the clock settings. If you have a +bootloader with one setting in your internal flash and an application with +another setting in your external SDRAM, you should also use the +ATSAM_CHANGE_CLOCK_FROM_SRAM=1 option. To overwrite the clock settings, define +the following structures in your application: + +-------- +const struct atsam_clock_config atsam_clock_config = { + .pllar_init = my_custom_pllar_value, + .mckr_init = my_custom_mckr_value, + .mck_freq = my_resulting_mck_frequency +}; + +const struct BOARD_Sdram_Config BOARD_Sdram_Config = { + .sdramc_tr = my_custom_sdramc_tr_value, + .sdramc_cr = my_custom_sdramc_cr_value, + .sdramc_mdr = my_custom_sdramc_mdr_value, + .sdramc_cfr1 = my_custom_sdramc_cfr1_value +}; +-------- + +Use ATSAM_SLOWCLOCK_USE_XTAL=0 to disable the usage of the external 32kHz +oscillator for the slow clock. This is useful for example for the SAM E70 +Xplained kit. + +Use ATSAM_CONSOLE_BAUD=XYZ to set the initial baud for console devices (default +115200). + +Use ATSAM_CONSOLE_DEVICE_TYPE=XYZ to set the device type for /dev/console, use +0 for USART and 1 for UART (default USART). + +Use ATSAM_CONSOLE_DEVICE_INDEX=XYZ to set the device index for /dev/console +(default 1, e.g. USART1). + +Use ATSAM_CONSOLE_USE_INTERRUPTS=XYZ to set the use interrupt driven mode for +console devices (used by default). + +Use ATSAM_MEMORY_TCM_SIZE=XYZ to set the size of tightly coupled memories (TCM) +in bytes (default 0x00000000). + +Use ATSAM_MEMORY_INTFLASH_SIZE=XYZ to set the size of internal flash in bytes +(default is derived from chip variant). + +Use ATSAM_MEMORY_INTSRAM_SIZE=XYZ to set the size of internal SRAM in bytes +(default is derived from chip variant). + +Use ATSAM_MEMORY_SDRAM_SIZE=XYZ to set the size of external SDRAM in bytes +(default 0x00200000). + +Use ATSAM_MEMORY_QSPIFLASH_SIZE=XYZ to set the size of QSPI flash in bytes +(default 0x00200000). + +The pins may be configured by the application at link-time. See +<bsp/pin-config.h>. + +The clock driver uses the ARMv7-M Systick. + +The console driver supports the USART and UART devices. + +The default linker command file places the code into the internal flash. Use +"LDFLAGS += -qnolinkcmds -T linkcmds.sdram" to place the code into the external +SDRAM. Use "LDFLAGS += -qnolinkcmds -T linkcmds.intsram" to place the code +into the internal SRAM. + +The fast text section uses the ITCM. The fast data section uses the DTCM. + +Data and instruction cache are enabled during system start. The RTEMS cache +manager is supported with exception of the freeze functions. diff --git a/bsps/arm/beagle/README b/bsps/arm/beagle/README new file mode 100644 index 0000000000..e558287408 --- /dev/null +++ b/bsps/arm/beagle/README @@ -0,0 +1,118 @@ +BSP for beagleboard xm, beaglebone (original aka white), and beaglebone black. + +original beagleboard isn't tested. + +wiki: http://www.rtems.org/wiki/index.php/Beagleboard + +1. *** CONFIGURING ************ + +bsp-specific build options in the environment at build time: +CONSOLE_POLLED=1 use polled i/o for console, required to run testsuite +CONSOLE_BAUD=... override default console baud rate + +BSPs recognized are: +beagleboardorig original beagleboard +beagleboardxm beagleboard xm +beaglebonewhite original beaglebone +beagleboneblack beaglebone black + +Currently the only distinction in the BSP are between the beagleboards and +the beaglebones, but the 4 names are specified in case hardware-specific +distinctions are made in the future, so this can be done without changing the +usage. + + +2. *** BUILDING ************ + +To build BSPs for the beaglebone white and beagleboard xm, starting from +a directory in which you have this source tree in rtems-src: + +$ mkdir b-beagle +$ cd b-beagle +$ ../rtems-src/configure --target=arm-rtems4.11 --enable-rtemsbsp="beaglebonewhite beagleboardxm" +$ make all + +This should give you .exes somewhere. + +Then you need 'mkimage' to transform a .exe file to a u-boot image +file. first make a flat binary: + +$ arm-rtems4.11-objcopy $exe -O binary $exe.bin +$ gzip -9 $exe.bin +$ mkimage -A arm -O rtems -T kernel -a 0x80000000 -e 0x80000000 -n RTEMS -d $exe.bin.gz rtems-app.img + +All beagles have memory starting at 0x80000000 so the load & run syntax is the same. + +3. *** BOOTING ************ + +Then, boot the beaglebone with u-boot on an SD card and load rtems-app.img +from u-boot. Interrupt the u-boot boot to get a prompt. + +Set up a tftp server and a network connection for netbooting. And to +copy rtems-app.img to the tftp dir. Otherwise copy the .img to the FAT +partition on the SD card and make uboot load & run that. + +4. *** BEAGLEBONES ************ + +(tested on both beaglebones) + +Beaglebone original (white) or beaglebone black netbooting: + +uboot# setenv ipaddr 192.168.12.20 +uboot# setenv serverip 192.168.12.10 +uboot# echo starting from TFTP +uboot# tftp 0x80800000 rtems-app.img +uboot# dcache off ; icache off +uboot# bootm 0x80800000 + +Beaglebone original (white) or beaglebone black from a FAT partition: + +uboot# fatload mmc :1 0x80800000 ticker.img +uboot# dcache off ; icache off +uboot# bootm 0x80800000 + +4. *** BEAGLEBOARD ************ + +(tested on xm) + +For the beagleboard the necessary commands are a bit different because +of the ethernet over usb: + +uboot# setenv serverip 192.168.12.10 +uboot# setenv ipaddr 192.168.12.62 +uboot# setenv usbnet_devaddr e8:03:9a:24:f9:10 +uboot# setenv usbethaddr e8:03:9a:24:f9:11 +uboot# usb start +uboot# echo starting from TFTP +uboot# tftp 0x80800000 rtems-app.img +uboot# dcache off ; icache off +uboot# bootm 0x80800000 + +4. *** SD CARD **************** + +There is a script here that automatically writes an SD card for any of +the beagle targets. + +Let's write one for the Beaglebone Black. Assuming your source tree is +at $HOME/development/rtems/rtems-src and your bsp is built and linked +with examples and installed at $HOME/development/rtems/4.11. + + % cd $HOME/development/rtems/rtems-src/c/src/lib/libbsp/arm/beagle/simscripts + % sh sdcard.sh $HOME/development/rtems/4.11 $HOME/development/rtems/b-beagle/arm-rtems4.11/c/beagleboneblack/testsuites/samples/hello/hello.exe + +The script should give you a whole bunch of output, ending in: + + Result is in bone_hello.exe-sdcard.img. + +There you go. dd that to an SD card and boot! + +The script needs to know whether it's for a Beagleboard xM or one of the +Beaglebones. This is to know which uboot to use. It will detect this +from the path the executable is in (in the above example, it contains +'beagleboneblack'), so you have to specify the full path. + + +Good luck & enjoy! + +Ben Gras +beng@shrike-systems.com diff --git a/bsps/arm/beagle/README.JTAG b/bsps/arm/beagle/README.JTAG new file mode 100644 index 0000000000..8d30590b54 --- /dev/null +++ b/bsps/arm/beagle/README.JTAG @@ -0,0 +1,20 @@ +To run RTEMS from scratch (without any other bootcode) on the beagles, +you can comfortably load the executables over JTAG using gdb. This is +necessarily target-specific however. + +1. BBXM + + - For access to JTAG using openocd, see simscripts/bbxm.cfg. + - openocd then offers access to gdb using simscripts/gdbinit.bbxm. + - start openocd using bbxm.cfg + - copy your .exe to a new dir and that gdbinit file as .gdbinit in the same dir + - go there and start gdb: + $ arm-rtems4.11-gdb hello.exe + - gdb will invoke the BBXM hardware initialization in the bbxm.cfg + and load the ELF over JTAG. type 'c' (for continue) to run it. + - breakpoints, C statement and single-instruction stepping work. + +2. beaglebone white + +This has been tested with openocd and works but not in as much detail as for +the BBXM yet (i.e. loading an executable from scratch). diff --git a/bsps/arm/beagle/TESTING b/bsps/arm/beagle/TESTING new file mode 100644 index 0000000000..2fea12b714 --- /dev/null +++ b/bsps/arm/beagle/TESTING @@ -0,0 +1,20 @@ +To build and run the tests for this BSP, use the RTEMS tester. +The necessary software can be built with the RTEMS source builder. + +To build the BSP for testing: + - set CONSOLE_POLLED=1 in the configure environment, some tests + assume console i/o is polled + - add --enable-tests to the configure line + +1. Qemu + +Linaro Qemu can emulate the beagleboard xm and so run all regression +tests in software. Build the bbxm.bset from the RTEMS source builder and +you will get qemu linaro that can run them. There is a beagleboardxm_qemu +bsp in the RTEMS tester to invoke it with every test. + +2. bbxm hardware + +This requires JTAG, see README.JTAG. Use the beagleboardxm bsp in the +RTEMS tester. It starts gdb to connect to openocd to reset the target +and load the RTEMS executable for each test iteration. diff --git a/bsps/arm/beagle/pwm/README b/bsps/arm/beagle/pwm/README new file mode 100644 index 0000000000..d41f5ca668 --- /dev/null +++ b/bsps/arm/beagle/pwm/README @@ -0,0 +1,197 @@ +Pulse Width Modulation subsystem includes EPWM, ECAP , EQEP. There are +different instances available for each one. For PWM there are three +different individual EPWM module 0 , 1 and 2. So wherever pwmss word is +used that affects whole PWM sub system such as EPWM, ECAP and EQEP. This code +has only implementation Non high resolution PWM module. APIs for high +resolution PWM has been yet to develop. + +For Each EPWM instance, has two PWM channels, e.g. EPWM0 has two channel +EPWM0A and EPWM0B. If you configure two PWM outputs(e.g. EPWM0A , EPWM0B) +in the same device, then they *must* be configured with the same frequency. +Changing frequency on one channel (e.g EPWMxA) will automatically change +frequency on another channel(e.g. EPWMxB). However, it is possible to set +different pulse-width/duty cycle to different channel at a time. So always +set the frequency first and then pulse-width/duty cycle. + +For more you can refer : +http://www.ofitselfso.com/BBBCSIO/Source/PWMPortEnum.cs.html + +Pulse Width Modulation uses the system frequency of Beagle Bone Black. + +System frequency = SYSCLKOUT, that is, CPU clock. TBCLK = SYSCLKOUT(By Default) +SYCLKOUT = 100 MHz + +Please visit following link to check why SYSCLKDIV = 100MHz: +https://groups.google.com/forum/#!topic/beagleboard/Ed2J9Txe_E4 +(Refer Technical Reference Manual (TRM) Table 15-41 as well) + +To generate different frequencies with the help of PWM module , SYSCLKOUT +need to be scaled down, which will act as TBCLK and TBCLK will be base clock +for the pwm subsystem. + +TBCLK = SYSCLKOUT/(HSPCLKDIV * CLKDIV) + + |----------------| + | clock | + SYSCLKOUT---> | |---> TBCLK + | prescale | + |----------------| + ^ ^ + | | + TBCTL[CLKDIV]----- ------TBCTL[HSPCLKDIV] + + +CLKDIV and HSPCLKDIV bits are part of the TBCTL register (Refer TRM). +CLKDIV - These bits determine part of the time-base clock prescale value. +Please use the following values of CLKDIV to scale down sysclk respectively. +0h (R/W) = /1 +1h (R/W) = /2 +2h (R/W) = /4 +3h (R/W) = /8 +4h (R/W) = /16 +5h (R/W) = /32 +6h (R/W) = /64 +7h (R/W) = /128 + +These bits determine part of the time-base clock prescale value. +Please use following value of HSPCLKDIV to scale down sysclk respectively +0h (R/W) = /1 +1h (R/W) = /2 +2h (R/W) = /4 +3h (R/W) = /6 +4h (R/W) = /8 +5h (R/W) = /10 +6h (R/W) = /12 +7h (R/W) = /14 + +For example, if you set CLKDIV = 3h and HSPCLKDIV= 2h Then +SYSCLKOUT will be divided by (1/8)(1/4). It means SYSCLKOUT/32 + +How to generate frequency ? + +freq = 1/Period + +TBPRD register is responsible to generate the frequency. These bits determine +the period of the time-base counter. + +By default TBCLK = SYSCLKOUT = 100 MHz + +Here by default period is 1/100MHz = 10 nsec + +Following example shows value to be loaded into TBPRD + +e.g. TBPRD = 1 = 1 count + count x Period = 1 x 1ns = 1ns + freq = 1/Period = 1 / 1ns = 100 MHz + +For duty cycle CMPA and CMPB are the responsible registers. + +To generate single with 50% Duty cycle & 100MHz freq. + + CMPA = count x Duty Cycle + = TBPRD x Duty Cycle + = 1 x 50/100 + = 0.2 + +The value in the active CMPA register is continuously compared to +the time-base counter (TBCNT). When the values are equal, the +counter-compare module generates a "time-base counter equal to +counter compare A" event. This event is sent to the action-qualifier +where it is qualified and converted it into one or more actions. +These actions can be applied to either the EPWMxA or the +EPWMxB output depending on the configuration of the AQCTLA and +AQCTLB registers. + +List of pins for that can be used for different PWM instance : + + ------------------------------------------------ + | EPWM2 | EPWM1 | EPWM0 | + ------------------------------------------------ + | BBB_P8_13_2B | BBB_P8_34_1B | BBB_P9_21_0B | + | BBB_P8_19_2A | BBB_P8_36_1A | BBB_P9_22_0A | + | BBB_P8_45_2A | BBB_P9_14_1A | BBB_P9_29_0B | + | BBB_P8_46_2B | BBB_P9_16_1B | BBB_P9_31_0A | + ------------------------------------------------ +BBB_P8_13_2B represents P8 Header , pin number 13 , 2nd PWM instance and B channel. + +Following sample program can be used to generate 7 Hz frequency. + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <rtems/test.h> +#include <bsp.h> +#include <bsp/gpio.h> +#include <stdio.h> +#include <stdlib.h> +#include <bsp/bbb-pwm.h> + +const char rtems_test_name[] = "Testing PWM driver"; +rtems_printer rtems_test_printer; + +static void inline delay_sec(int sec) +{ + rtems_task_wake_after(sec*rtems_clock_get_ticks_per_second()); +} + +rtems_task Init(rtems_task_argument argument); + +rtems_task Init( + rtems_task_argument ignored +) +{ + rtems_test_begin(); + printf("Starting PWM Testing"); + + /*Initialize GPIO pins in BBB*/ + rtems_gpio_initialize(); + + /* Set P9 Header , 21 Pin number , PWM B channel and 0 PWM instance to generate frequency*/ + beagle_epwm_pinmux_setup(BBB_P9_21_0B,BBB_PWMSS0); + +/** Initialize clock for PWM sub system + * Turn on time base clock for PWM o instance + */ + beagle_pwm_init(BBB_PWMSS0); + + float PWM_HZ = 7.0f ; /* 7 Hz */ + float duty_A = 20.0f ; /* 20% Duty cycle for PWM 0_A output */ + const float duty_B = 50.0f ; /* 50% Duty cycle for PWM 0_B output*/ + + /*Note: Always check whether pwmss clocks are enabled or not before configuring PWM*/ + bool is_running = beagle_pwmss_is_running(BBB_PWMSS2); + + if(is_running) { + + /*To analyse the two different duty cycle Output should be observed at P8_45 and P8_46 pin number */ + beagle_pwm_configure(BBB_PWMSS0, PWM_HZ ,duty_A , duty_B); + printf("PWM enable for 10s ....\n"); + + /*Set Up counter and enable pwm module */ + beagle_pwm_enable(BBB_PWMSS0); + delay_sec(10); + + /*freeze the counter and disable pwm module*/ + beagle_epwm_disable(BBB_PWMSS0); + } +} + +/* NOTICE: the clock driver is enabled */ +#define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER +#define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER + +#define CONFIGURE_MAXIMUM_TASKS 1 +#define CONFIGURE_USE_DEVFS_AS_BASE_FILESYSTEM + +#define CONFIGURE_MAXIMUM_SEMAPHORES 1 + +#define CONFIGURE_RTEMS_INIT_TASKS_TABLE + +#define CONFIGURE_EXTRA_TASK_STACKS (2 * RTEMS_MINIMUM_STACK_SIZE) + +#define CONFIGURE_INITIAL_EXTENSIONS RTEMS_TEST_INITIAL_EXTENSION + +#define CONFIGURE_INIT +#include <rtems/confdefs.h> + diff --git a/bsps/arm/beagle/simscripts/bbxm.cfg b/bsps/arm/beagle/simscripts/bbxm.cfg new file mode 100644 index 0000000000..a5fe36cd01 --- /dev/null +++ b/bsps/arm/beagle/simscripts/bbxm.cfg @@ -0,0 +1,174 @@ +# Start with: openocd -f interface/ftdi/flyswatter.cfg -f bbxm.cfg -c 'reset init' +# or with: openocd -f interface/ftdi/flyswatter2.cfg -f bbxm.cfg -c 'reset init' +source [find board/ti_beagleboard_xm.cfg] + +# +# Use the MLO file from uboot to initialise the board. +# +proc beagleboard_xm_mlo { file } { + global _CHIPNAME + adapter_khz 10 + catch { mww phys 0x48307250 0x00000004 } + reset init + icepick_c_wreset $_CHIPNAME.jrc + halt + dm37x.cpu arm core_state arm + puts "Beagleboard xM MLO: $file" + load_image $file 0x402005f8 bin + resume 0x40200800 + sleep 500 + halt +} + +proc beagleboard_xm_init {} { + global _CHIPNAME + adapter_khz 10 + catch { mww phys 0x48307250 0x00000004 } + reset init + icepick_c_wreset $_CHIPNAME.jrc + halt + dm37x.cpu arm core_state arm + + mwh 0x6e00007c 0x000000ff ;# omap-gpmc + mwh 0x6e00007c 0x00000090 ;# omap-gpmc + mwh 0x6e000080 0x00000000 ;# omap-gpmc + mwh 0x6e00007c 0x00000000 ;# omap-gpmc + mwh 0x6e000080 0x00000000 ;# omap-gpmc + mwh 0x6e000080 0x00000000 ;# omap-gpmc + mwh 0x6e000080 0x00000000 ;# omap-gpmc + mwh 0x6e000080 0x00000000 ;# omap-gpmc + mwh 0x6e000080 0x00000000 ;# omap-gpmc + mwh 0x6e00007c 0x00000030 ;# omap-gpmc + mww 0x48004c00 0x00000020 ;# omap3_cm + mww 0x48004c10 0x00000020 ;# omap3_cm + mww 0x48314048 0x0000aaaa ;# omap3_mpu_wdt + mww 0x48314048 0x00005555 ;# omap3_mpu_wdt + mww 0x6c000048 0xffffffff ;# omap3_sms + mww 0x48004c40 0x00000013 ;# omap3_cm + mww 0x48004c10 0x00000025 ;# omap3_cm + mww 0x48004c00 0x00000021 ;# omap3_cm + mww 0x48306d40 0x00000003 ;# omap3_prm + mww 0x48307270 0x00000083 ;# omap3_prm + mww 0x48307270 0x00000080 ;# omap3_prm + mww 0x48004904 0x00000015 ;# omap3_cm + mww 0x48004d00 0x00110016 ;# omap3_cm + mww 0x48005140 0x10020a50 ;# omap3_cm + mww 0x48004d40 0x08000040 ;# omap3_cm + mww 0x48004d40 0x09900040 ;# omap3_cm + mww 0x48004d40 0x09900c40 ;# omap3_cm + mww 0x48004d40 0x09900c00 ;# omap3_cm + mww 0x48004a40 0x00001305 ;# omap3_cm + mww 0x48004a40 0x00001125 ;# omap3_cm + mww 0x48004a40 0x00001109 ;# omap3_cm + mww 0x48004a40 0x0000110a ;# omap3_cm + mww 0x48004b40 0x00000005 ;# omap3_cm + mww 0x48004c40 0x00000015 ;# omap3_cm + mww 0x48004d00 0x00110006 ;# omap3_cm + mww 0x48004d00 0x00110007 ;# omap3_cm + mww 0x48004d00 0x00110007 ;# omap3_cm + mww 0x48005140 0x03020a50 ;# omap3_cm + mww 0x48004f40 0x00000004 ;# omap3_cm + mww 0x48004e40 0x00000409 ;# omap3_cm + mww 0x48004e40 0x00001009 ;# omap3_cm + mww 0x48004d48 0x00000009 ;# omap3_cm + mww 0x48004d44 0x02436000 ;# omap3_cm + mww 0x48004d44 0x0243600c ;# omap3_cm + mww 0x48004a40 0x0000110a ;# omap3_cm + mww 0x48004d00 0x00170007 ;# omap3_cm + mww 0x48004d04 0x00000011 ;# omap3_cm + mww 0x48004d50 0x00000001 ;# omap3_cm + mww 0x48004d4c 0x00007800 ;# omap3_cm + mww 0x48004d4c 0x0000780c ;# omap3_cm + mww 0x48004d00 0x00170037 ;# omap3_cm + mww 0x48004d04 0x00000017 ;# omap3_cm + mww 0x48004004 0x00000011 ;# omap3_cm + mww 0x48004044 0x00000001 ;# omap3_cm + mww 0x48004040 0x00081400 ;# omap3_cm + mww 0x48004040 0x00081400 ;# omap3_cm + mww 0x48004004 0x00000017 ;# omap3_cm + mww 0x48004944 0x00000001 ;# omap3_cm + mww 0x48004940 0x000a5800 ;# omap3_cm + mww 0x48004940 0x000a580c ;# omap3_cm + mww 0x48004904 0x00000017 ;# omap3_cm + mww 0x48005040 0x000000ff ;# omap3_cm + mww 0x48004c40 0x00000015 ;# omap3_cm + mww 0x48005040 0x000000ff ;# omap3_cm + mww 0x48005010 0x00000008 ;# omap3_cm + mww 0x48005000 0x00000008 ;# omap3_cm + mww 0x48004a00 0x00002000 ;# omap3_cm + mww 0x48004a10 0x00002042 ;# omap3_cm + mww 0x48005000 0x00000808 ;# omap3_cm + mww 0x48005010 0x00000808 ;# omap3_cm + mww 0x48004a00 0x0003a000 ;# omap3_cm + mww 0x48004a10 0x0003a042 ;# omap3_cm + mww 0x48004c10 0x00000025 ;# omap3_cm + mww 0x48004000 0x00000001 ;# omap3_cm + mww 0x48004a00 0x03fffe29 ;# omap3_cm + mww 0x48004a10 0x3ffffffb ;# omap3_cm + mww 0x48004a14 0x0000001f ;# omap3_cm + mww 0x48004c00 0x000000e9 ;# omap3_cm + mww 0x48004c10 0x0000003f ;# omap3_cm + mww 0x48004e00 0x00000005 ;# omap3_cm + mww 0x48004e10 0x00000001 ;# omap3_cm + mww 0x48004f00 0x00000001 ;# omap3_cm + mww 0x48004f10 0x00000001 ;# omap3_cm + mww 0x48005000 0x0003ffff ;# omap3_cm + mww 0x48005010 0x0003ffff ;# omap3_cm + mww 0x48005410 0x00000001 ;# omap3_cm + mww 0x48005400 0x00000003 ;# omap3_cm + mww 0x48004a18 0x00000004 ;# omap3_cm + mww 0x48004a08 0x00000004 ;# omap3_cm + mww 0x6e000060 0x00001800 ;# omap-gpmc + mww 0x6e000064 0x00141400 ;# omap-gpmc + mww 0x6e000068 0x00141400 ;# omap-gpmc + mww 0x6e00006c 0x0f010f01 ;# omap-gpmc + mww 0x6e000070 0x010c1414 ;# omap-gpmc + mww 0x6e000074 0x1f0f0a80 ;# omap-gpmc + mww 0x6e000078 0x00000870 ;# omap-gpmc + mwb 0x6e00007c 0x000000ff ;# omap-gpmc + mwb 0x6e00007c 0x00000070 ;# omap-gpmc + mwb 0x6e00007c 0x00000090 ;# omap-gpmc + mwb 0x6e000080 0x00000000 ;# omap-gpmc + mww 0x6d000010 0x00000002 ;# omap.sdrc + mww 0x6d000010 0x00000000 ;# omap.sdrc + mww 0x6d000044 0x00000100 ;# omap.sdrc + mww 0x6d000070 0x04000081 ;# omap.sdrc + mww 0x6d000060 0x0000000a ;# omap.sdrc + mww 0x6d000080 0x04590099 ;# omap.sdrc + mww 0x6d00009c 0xc29dc4c6 ;# omap.sdrc + mww 0x6d0000a0 0x00022322 ;# omap.sdrc + mww 0x6d0000a4 0x0004e201 ;# omap.sdrc + mww 0x6d0000a8 0x00000000 ;# omap.sdrc + mww 0x6d0000a8 0x00000001 ;# omap.sdrc + mww 0x6d0000a8 0x00000002 ;# omap.sdrc + mww 0x6d0000a8 0x00000002 ;# omap.sdrc + mww 0x6d000084 0x00000032 ;# omap.sdrc + mww 0x6d000040 0x00000004 ;# omap.sdrc + mww 0x6d0000b0 0x04590099 ;# omap.sdrc + mww 0x6d0000c4 0xc29dc4c6 ;# omap.sdrc + mww 0x6d0000c8 0x00022322 ;# omap.sdrc + mww 0x6d0000d4 0x0004e201 ;# omap.sdrc + mww 0x6d0000d8 0x00000000 ;# omap.sdrc + mww 0x6d0000d8 0x00000001 ;# omap.sdrc + mww 0x6d0000d8 0x00000002 ;# omap.sdrc + mww 0x6d0000d8 0x00000002 ;# omap.sdrc + mww 0x6d0000b4 0x00000032 ;# omap.sdrc + mww 0x6d0000b0 0x00000000 ;# omap.sdrc + mww 0x6e00001c 0x00000000 ;# omap-gpmc + mww 0x6e000040 0x00000000 ;# omap-gpmc + mww 0x6e000050 0x00000000 ;# omap-gpmc + mww 0x6e000078 0x00000000 ;# omap-gpmc + mww 0x6e000078 0x00000000 ;# omap-gpmc + mww 0x6e000060 0x00001800 ;# omap-gpmc + mww 0x6e000064 0x00141400 ;# omap-gpmc + mww 0x6e000068 0x00141400 ;# omap-gpmc + mww 0x6e00006c 0x0f010f01 ;# omap-gpmc + mww 0x6e000070 0x010c1414 ;# omap-gpmc + mww 0x6e000074 0x1f0f0a80 ;# omap-gpmc + mww 0x6e000078 0x00000870 ;# omap-gpmc + mww 0x48004a00 0x437ffe00 ;# omap3_cm + mww 0x48004a10 0x637ffed2 ;# omap3_cm + puts "Beagleboard xM initialised" +} + +init diff --git a/bsps/arm/beagle/simscripts/gdbinit.bbxm b/bsps/arm/beagle/simscripts/gdbinit.bbxm new file mode 100644 index 0000000000..32ae9dd9ad --- /dev/null +++ b/bsps/arm/beagle/simscripts/gdbinit.bbxm @@ -0,0 +1,16 @@ +target remote localhost:3333 +mon reset halt +mon beagleboard_xm_init +load + +b _ARMV4_Exception_undef_default +b _ARMV4_Exception_swi_default +b _ARMV4_Exception_pref_abort_default +b _ARMV4_Exception_data_abort_default +b _ARMV4_Exception_reserved_default +b _ARMV4_Exception_irq_default +b _ARMV4_Exception_fiq_default + +b rtems_fatal +b rtems_fatal_error_occurred +b _exit diff --git a/bsps/arm/beagle/simscripts/qemu-beagleboard.in b/bsps/arm/beagle/simscripts/qemu-beagleboard.in new file mode 100644 index 0000000000..47c3bf489d --- /dev/null +++ b/bsps/arm/beagle/simscripts/qemu-beagleboard.in @@ -0,0 +1,63 @@ +# +# ARM/BeagleBoard Qemu Support +# + +bspUsesGDBSimulator="no" +# bspGeneratesGDBCommands="yes" +# bspSupportsGDBServerMode="yes" +runBSP=NOT_OVERRIDDEN +if [ ! -r ${runBSP} ] ; then + runBSP=qemu-system-arm +fi +bspNeedsDos2Unix="yes" +bspGeneratesDeviceTree="yes" +bspInputDevice=qemu-gumstix.cmds +bspTreeFile=qemu-gumstix.cmds +bspRedirectInput=yes + +runARGS() +{ +# qemu-system-arm -M connex -m 289 -nographic -monitor null -pflash connex-flash.img <cmds >log + + UBOOT=${HOME}/qemu/u-boot-connex-400-r1604.bin + FLASH=connex-flash.img + ( dd of=${FLASH} bs=128k count=128 if=/dev/zero ; + dd of=${FLASH} bs=128k conv=notrunc if=${UBOOT} ; + dd of=${FLASH} bs=1k conv=notrunc seek=4096 if=${1} ) >/dev/null 2>&1 + + if [ ${coverage} = yes ] ; then + rm -f trace ${1}.tra + COVERAGE_ARG="-trace ${1}.tra" + fi + + echo "-M connex -m 289 -nographic -monitor null \ + -pflash ${FLASH} ${COVERAGE_ARG}" +} + +checkBSPFaults() +{ + return 0 +} + +bspLimit() +{ + testname=$1 + case ${testname} in + *stackchk*)limit=5 ;; + *fatal*) limit=1 ;; + *minimum*) limit=1 ;; + *psxtime*) limit=180 ;; + *) limit=60 ;; + esac + echo ${limit} +} + +### Generate the commands we boot with +bspGenerateDeviceTree() +{ +cat >qemu-gumstix.cmds <<EOF + +bootelf 0x400000 + +EOF +} diff --git a/bsps/arm/beagle/simscripts/sdcard.sh b/bsps/arm/beagle/simscripts/sdcard.sh new file mode 100644 index 0000000000..83e3807cc7 --- /dev/null +++ b/bsps/arm/beagle/simscripts/sdcard.sh @@ -0,0 +1,84 @@ +# we store all generated files here. +TMPDIR=tmp_sdcard_dir.$$ + +FATIMG=$TMPDIR/bbxm_boot_fat.img +SIZE=65536 +OFFSET=2048 +FATSIZE=`expr $SIZE - $OFFSET` +UENV=uEnv.txt + +rm -rf $TMPDIR +mkdir -p $TMPDIR + +if [ $# -ne 2 ] +then echo "Usage: $0 <RTEMS prefix> <RTEMS executable>" + exit 1 +fi + +PREFIX=$1 + +if [ ! -d "$PREFIX" ] +then echo "This script needs the RTEMS tools bindir as the first argument." + exit 1 +fi + +executable=$2 + +case "$2" in + *beagleboard*) + ubootcfg=omap3_beagle + imgtype=bb + ;; + *beaglebone*) + ubootcfg=am335x_evm + imgtype=bone + ;; + *) + echo "Can't guess which uboot to use - please specify full path to executable." + exit 1 + ;; +esac + +app=rtems-app.img + +if [ ! -f "$executable" ] +then echo "Expecting RTEMS executable as arg; $executable not found." + exit 1 +fi + +set -e + +IMG=${imgtype}_`basename $2`-sdcard.img + +# Make an empty image +dd if=/dev/zero of=$IMG bs=512 seek=`expr $SIZE - 1` count=1 +dd if=/dev/zero of=$FATIMG bs=512 seek=`expr $FATSIZE - 1` count=1 + +# Make an ms-dos FS on it +$PREFIX/bin/newfs_msdos -r 1 -m 0xf8 -c 4 -F16 -h 64 -u 32 -S 512 -s $FATSIZE -o 0 ./$FATIMG + +# Prepare the executable. +base=`basename $executable` +$PREFIX/bin/arm-rtems4.12-objcopy $executable -O binary $TMPDIR/$base.bin +gzip -9 $TMPDIR/$base.bin +$PREFIX/bin/mkimage -A arm -O rtems -T kernel -a 0x80000000 -e 0x80000000 -n RTEMS -d $TMPDIR/$base.bin.gz $TMPDIR/$app +echo "setenv bootdelay 5 +uenvcmd=run boot +boot=fatload mmc 0 0x80800000 $app ; bootm 0x80800000" >$TMPDIR/$UENV + +# Copy the uboot and app image onto the FAT image +$PREFIX/bin/mcopy -bsp -i $FATIMG $PREFIX/uboot/$ubootcfg/MLO ::MLO +$PREFIX/bin/mcopy -bsp -i $FATIMG $PREFIX/uboot/$ubootcfg/u-boot.img ::u-boot.img +$PREFIX/bin/mcopy -bsp -i $FATIMG $TMPDIR/$app ::$app +$PREFIX/bin/mcopy -bsp -i $FATIMG $TMPDIR/$UENV ::$UENV + +# Just a single FAT partition (type C) that uses all of the image +$PREFIX/bin/partition -m $IMG $OFFSET c:${FATSIZE}\* + +# Put the FAT image into the SD image +dd if=$FATIMG of=$IMG seek=$OFFSET + +# cleanup +rm -rf $TMPDIR + +echo "Result is in $IMG." diff --git a/bsps/arm/csb336/README b/bsps/arm/csb336/README new file mode 100644 index 0000000000..ac66c2ae7a --- /dev/null +++ b/bsps/arm/csb336/README @@ -0,0 +1,3 @@ +This is the BSP for Cogent Computer System's CSB336, a single board +computer using the Motorola MC9328MXL CPU. + diff --git a/bsps/arm/csb337/README b/bsps/arm/csb337/README new file mode 100644 index 0000000000..19a7bcbe24 --- /dev/null +++ b/bsps/arm/csb337/README @@ -0,0 +1,11 @@ +This is the BSP for Cogent Computer System's CSB337 and updated +for CSB637, single board computers using the Atmel AT91RM9200 CPU. +The differences in the board are very slight but important: + + CSB337 CSB637 +======== ======== +16Mb RAM 64Mb RAM +?? + +Please check README.kit637_v6 for more explanation about the Cogent's +Development Kit that uses the CSB637 single board computer. diff --git a/bsps/arm/csb337/README.kit637_v6 b/bsps/arm/csb337/README.kit637_v6 new file mode 100644 index 0000000000..23a3cb759c --- /dev/null +++ b/bsps/arm/csb337/README.kit637_v6 @@ -0,0 +1,26 @@ +# Fernando Nicodemos <fgnicodemos@terra.com.br> +# from NCB - Sistemas Embarcados Ltda. (Brazil) +# + +This is the BSP for Cogent Computer System's KIT637_V6. It implements an +updated version of the CSB337 board with a number of optional peripherals. + +This KIT is implemented by CSB637 single board computer using the +Atmel AT91RM9200 CPU and the CSB937 target main board. It uses an +Optrex LCD (T-51750AA, 640x480) and Touchscreen (not supported in this +BSP). The IDE and USB (host and device) interfaces are also not supported. +The SD and Compact Flash cards drivers are still under development. + +The differences in the CSB637 single board computer are very slight but +important: + + CSB337 CSB637 + ========== ========== +Clock speed 184MHz 184MHz +External memory 16MB SDRAM 64MB SDRAM +Flash memory 8MB Strata 8/16MB Strata (8MB used by default) +Video buffer 1MB 8MB +Video driver S1D13706 S1D13506 +PHY Layer LXT971ALC BCM5221 + +?? Some GPIO or interrupts moved around. diff --git a/bsps/arm/edb7312/README b/bsps/arm/edb7312/README new file mode 100644 index 0000000000..ce524fcda6 --- /dev/null +++ b/bsps/arm/edb7312/README @@ -0,0 +1 @@ +This board is from Cogent. diff --git a/bsps/arm/gumstix/README b/bsps/arm/gumstix/README new file mode 100644 index 0000000000..41a74c7daf --- /dev/null +++ b/bsps/arm/gumstix/README @@ -0,0 +1,2 @@ +This is the BSP for GUMSTIX which has a PXA255 CPU. + diff --git a/bsps/arm/lm3s69xx/0001-target-arm-Fixed-ARMv7-M-SHPR-access.patch b/bsps/arm/lm3s69xx/0001-target-arm-Fixed-ARMv7-M-SHPR-access.patch new file mode 100644 index 0000000000..32aafdbce9 --- /dev/null +++ b/bsps/arm/lm3s69xx/0001-target-arm-Fixed-ARMv7-M-SHPR-access.patch @@ -0,0 +1,104 @@ +From 0c8e700376cec0c7b5a70f999b5e286efc321423 Mon Sep 17 00:00:00 2001 +From: Sebastian Huber <sebastian.huber@embedded-brains.de> +Date: Fri, 16 Dec 2011 19:46:40 +0100 +Subject: [PATCH 1/4] target-arm: Fixed ARMv7-M SHPR access + +According to "ARMv7-M Architecture Reference Manual" issue D section +"B3.2.10 System Handler Prioriy Register 1, SHPR1", "B3.2.11 System +Handler Prioriy Register 2, SHPR2", and "B3.2.12 System Handler Prioriy +Register 3, SHPR3". + +Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> +--- + hw/arm_gic.c | 16 ++++++++++++++-- + hw/armv7m_nvic.c | 19 ------------------- + 2 files changed, 14 insertions(+), 21 deletions(-) + +diff --git a/hw/arm_gic.c b/hw/arm_gic.c +index 9b52119..5139d95 100644 +--- a/hw/arm_gic.c ++++ b/hw/arm_gic.c +@@ -356,6 +356,11 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset) + if (GIC_TEST_TRIGGER(irq + i)) + res |= (2 << (i * 2)); + } ++#else ++ } else if (0xd18 <= offset && offset < 0xd24) { ++ /* System Handler Priority. */ ++ irq = offset - 0xd14; ++ res = GIC_GET_PRIORITY(irq, cpu); + #endif + } else if (offset < 0xfe0) { + goto bad_reg; +@@ -387,7 +392,8 @@ static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset) + gic_state *s = (gic_state *)opaque; + uint32_t addr; + addr = offset; +- if (addr < 0x100 || addr > 0xd00) ++ if (addr < 0x100 || (addr > 0xd00 && addr != 0xd18 && addr != 0xd1c ++ && addr != 0xd20)) + return nvic_readl(s, addr); + #endif + val = gic_dist_readw(opaque, offset); +@@ -528,6 +534,11 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset, + GIC_CLEAR_TRIGGER(irq + i); + } + } ++#else ++ } else if (0xd18 <= offset && offset < 0xd24) { ++ /* System Handler Priority. */ ++ irq = offset - 0xd14; ++ s->priority1[irq][0] = value & 0xff; + #endif + } else { + /* 0xf00 is only handled for 32-bit writes. */ +@@ -553,7 +564,8 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset, + #ifdef NVIC + uint32_t addr; + addr = offset; +- if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) { ++ if (addr < 0x100 || (addr > 0xd00 && addr != 0xd18 && addr != 0xd1c ++ && addr != 0xd20 && addr != 0xf00)) { + nvic_writel(s, addr, value); + return; + } +diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c +index bf8c3c5..65b575e 100644 +--- a/hw/armv7m_nvic.c ++++ b/hw/armv7m_nvic.c +@@ -195,14 +195,6 @@ static uint32_t nvic_readl(void *opaque, uint32_t offset) + case 0xd14: /* Configuration Control. */ + /* TODO: Implement Configuration Control bits. */ + return 0; +- case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority. */ +- irq = offset - 0xd14; +- val = 0; +- val |= s->gic.priority1[irq++][0]; +- val |= s->gic.priority1[irq++][0] << 8; +- val |= s->gic.priority1[irq++][0] << 16; +- val |= s->gic.priority1[irq][0] << 24; +- return val; + case 0xd24: /* System Handler Status. */ + val = 0; + if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0); +@@ -335,17 +327,6 @@ static void nvic_writel(void *opaque, uint32_t offset, uint32_t value) + case 0xd14: /* Configuration Control. */ + /* TODO: Implement control registers. */ + goto bad_reg; +- case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority. */ +- { +- int irq; +- irq = offset - 0xd14; +- s->gic.priority1[irq++][0] = value & 0xff; +- s->gic.priority1[irq++][0] = (value >> 8) & 0xff; +- s->gic.priority1[irq++][0] = (value >> 16) & 0xff; +- s->gic.priority1[irq][0] = (value >> 24) & 0xff; +- gic_update(&s->gic); +- } +- break; + case 0xd24: /* System Handler Control. */ + /* TODO: Real hardware allows you to set/clear the active bits + under some circumstances. We don't implement this. */ +-- +1.7.1 + diff --git a/bsps/arm/lm3s69xx/0002-target-arm-Disable-priority_mask-feature.patch b/bsps/arm/lm3s69xx/0002-target-arm-Disable-priority_mask-feature.patch new file mode 100644 index 0000000000..28041546d4 --- /dev/null +++ b/bsps/arm/lm3s69xx/0002-target-arm-Disable-priority_mask-feature.patch @@ -0,0 +1,31 @@ +From 5f562d098d84e12d4688272dcf68a2d0318721a7 Mon Sep 17 00:00:00 2001 +From: Sebastian Huber <sebastian.huber@embedded-brains.de> +Date: Fri, 16 Dec 2011 20:00:59 +0100 +Subject: [PATCH 2/4] target-arm: Disable priority_mask feature + +This is unused for the ARMv7-M NVIC. + +Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> +--- + hw/arm_gic.c | 4 ++++ + 1 files changed, 4 insertions(+), 0 deletions(-) + +diff --git a/hw/arm_gic.c b/hw/arm_gic.c +index 5139d95..cafcc81 100644 +--- a/hw/arm_gic.c ++++ b/hw/arm_gic.c +@@ -707,7 +707,11 @@ static void gic_reset(gic_state *s) + int i; + memset(s->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state)); + for (i = 0 ; i < NUM_CPU(s); i++) { ++#ifdef NVIC ++ s->priority_mask[i] = 0x100; ++#else + s->priority_mask[i] = 0xf0; ++#endif + s->current_pending[i] = 1023; + s->running_irq[i] = 1023; + s->running_priority[i] = 0x100; +-- +1.7.1 + diff --git a/bsps/arm/lm3s69xx/0003-target-arm-Evil-hack-for-BASEPRI-and-BASEPRI_MAX.patch b/bsps/arm/lm3s69xx/0003-target-arm-Evil-hack-for-BASEPRI-and-BASEPRI_MAX.patch new file mode 100644 index 0000000000..54ec6983d2 --- /dev/null +++ b/bsps/arm/lm3s69xx/0003-target-arm-Evil-hack-for-BASEPRI-and-BASEPRI_MAX.patch @@ -0,0 +1,63 @@ +From 78e85bb79c02b14170c3f39d9bb9cccd4d625890 Mon Sep 17 00:00:00 2001 +From: Sebastian Huber <sebastian.huber@embedded-brains.de> +Date: Fri, 16 Dec 2011 20:12:29 +0100 +Subject: [PATCH 3/4] target-arm: Evil hack for BASEPRI and BASEPRI_MAX + +This is only a quick and dirty fix to get the ARMv7-M BASEPRI and +BASEPRI_MAX feature working. + +Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> +--- + cpu-exec.c | 4 ++-- + target-arm/helper.c | 12 +++++------- + 2 files changed, 7 insertions(+), 9 deletions(-) + +diff --git a/cpu-exec.c b/cpu-exec.c +index a9fa608..6ca9aab 100644 +--- a/cpu-exec.c ++++ b/cpu-exec.c +@@ -408,8 +408,8 @@ int cpu_exec(CPUState *env) + We avoid this by disabling interrupts when + pc contains a magic address. */ + if (interrupt_request & CPU_INTERRUPT_HARD +- && ((IS_M(env) && env->regs[15] < 0xfffffff0) +- || !(env->uncached_cpsr & CPSR_I))) { ++ && !(env->uncached_cpsr & CPSR_I) ++ && (!IS_M(env) || env->regs[15] < 0xfffffff0)) { + env->exception_index = EXCP_IRQ; + do_interrupt(env); + next_tb = 0; +diff --git a/target-arm/helper.c b/target-arm/helper.c +index 65f4fbf..be2e6db 100644 +--- a/target-arm/helper.c ++++ b/target-arm/helper.c +@@ -2163,7 +2163,7 @@ uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg) + return (env->uncached_cpsr & CPSR_I) != 0; + case 17: /* BASEPRI */ + case 18: /* BASEPRI_MAX */ +- return env->v7m.basepri; ++ return (env->uncached_cpsr & CPSR_I) != 0; + case 19: /* FAULTMASK */ + return (env->uncached_cpsr & CPSR_F) != 0; + case 20: /* CONTROL */ +@@ -2218,13 +2218,11 @@ void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val) + env->uncached_cpsr &= ~CPSR_I; + break; + case 17: /* BASEPRI */ +- env->v7m.basepri = val & 0xff; +- break; + case 18: /* BASEPRI_MAX */ +- val &= 0xff; +- if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0)) +- env->v7m.basepri = val; +- break; ++ if (val) ++ env->uncached_cpsr |= CPSR_I; ++ else ++ env->uncached_cpsr &= ~CPSR_I; + case 19: /* FAULTMASK */ + if (val & 1) + env->uncached_cpsr |= CPSR_F; +-- +1.7.1 + diff --git a/bsps/arm/lm3s69xx/0004-target-arm-Evil-hack-to-increase-the-RAM-size.patch b/bsps/arm/lm3s69xx/0004-target-arm-Evil-hack-to-increase-the-RAM-size.patch new file mode 100644 index 0000000000..0669a9a238 --- /dev/null +++ b/bsps/arm/lm3s69xx/0004-target-arm-Evil-hack-to-increase-the-RAM-size.patch @@ -0,0 +1,32 @@ +From e06edd436a336e5db5188eb7ffac594138fc825a Mon Sep 17 00:00:00 2001 +From: Sebastian Huber <sebastian.huber@embedded-brains.de> +Date: Fri, 16 Dec 2011 20:19:45 +0100 +Subject: [PATCH 4/4] target-arm: Evil hack to increase the RAM size + +This increases the RAM of the Stellaris LM3S6965 in a brute force way. +It would be nice to be able to override the default RAM size with +command line options. The default RAM size is to small to run complex +test suites. + +Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> +--- + hw/stellaris.c | 3 ++- + 1 files changed, 2 insertions(+), 1 deletions(-) + +diff --git a/hw/stellaris.c b/hw/stellaris.c +index ce62a98..dd7b7d7 100644 +--- a/hw/stellaris.c ++++ b/hw/stellaris.c +@@ -1219,7 +1219,8 @@ static stellaris_board_info stellaris_boards[] = { + { "LM3S6965EVB", + 0x10010002, + 0x1073402e, +- 0x00ff007f, /* dc0 */ ++ /* FIXME */ ++ 0xffffffff, /* dc0 */ + 0x001133ff, + 0x030f5317, + 0x0f0f87ff, +-- +1.7.1 + diff --git a/bsps/arm/lm3s69xx/0005-target-arm-Fix-system_clock_scale-initial-value.patch b/bsps/arm/lm3s69xx/0005-target-arm-Fix-system_clock_scale-initial-value.patch new file mode 100644 index 0000000000..d1c89886af --- /dev/null +++ b/bsps/arm/lm3s69xx/0005-target-arm-Fix-system_clock_scale-initial-value.patch @@ -0,0 +1,29 @@ +From bb7192082be2be0acfda61cd46d2b2c3677f8337 Mon Sep 17 00:00:00 2001 +From: Sebastian Huber <sebastian.huber@embedded-brains.de> +Date: Sat, 24 Mar 2012 19:58:44 +0100 +Subject: [PATCH] target-arm: Fix system_clock_scale initial value + +This variable should be initilized somewhere. This default value avoids +a division by zero. + +Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> +--- + hw/armv7m_nvic.c | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c +index 65b575e..b3a1b3d 100644 +--- a/hw/armv7m_nvic.c ++++ b/hw/armv7m_nvic.c +@@ -51,7 +51,7 @@ typedef struct { + #define SYSTICK_CLKSOURCE (1 << 2) + #define SYSTICK_COUNTFLAG (1 << 16) + +-int system_clock_scale; ++int system_clock_scale = SYSTICK_SCALE; + + /* Conversion factor from qemu timer to SysTick frequencies. */ + static inline int64_t systick_scale(nvic_state *s) +-- +1.7.1 + diff --git a/bsps/arm/lm3s69xx/README b/bsps/arm/lm3s69xx/README new file mode 100644 index 0000000000..c280b19253 --- /dev/null +++ b/bsps/arm/lm3s69xx/README @@ -0,0 +1,8 @@ +Tested only on Qemu simulator with git (git://git.qemu.org/qemu.git) version +1.0.50. + +You have to apply the patches contained in this directory. + +Command line: + +qemu-system-arm -S -s -net none -nographic -M lm3s6965evb -kernel hello.bin diff --git a/bsps/arm/lpc176x/README b/bsps/arm/lpc176x/README new file mode 100644 index 0000000000..d57e52fd93 --- /dev/null +++ b/bsps/arm/lpc176x/README @@ -0,0 +1,11 @@ +Development Board: Base Board from Embedded Artists + +http://www.embeddedartists.com/products/lpcxpresso/mbed.php + +Drivers: + + o Console + o Clock + o Timer + o GPIO + o Watchdog diff --git a/bsps/arm/lpc24xx/README b/bsps/arm/lpc24xx/README new file mode 100644 index 0000000000..47cc16150d --- /dev/null +++ b/bsps/arm/lpc24xx/README @@ -0,0 +1,52 @@ +Development Board: QVGA Base Board from Embedded Artists + +http://www.embeddedartists.com/products/uclinux/oem_lpc2478.php + +Drivers: + + o Console + o Clock + o RTC + o SSP (SPI mode) + o Network + o I2C + +Howto setup QVGA Base Board? + + o Unpack board. + o Connect board via USB to your PC. + o Verify that demo application runs. + o Disconnect board. + o Change jumpers to enable ISP. + o Connect board. + o Load U-Boot image 'u-boot_v1.1.6_lpc2468oem_v1_8_16bit.hex' + (available from the EA support page) into the flash (flash tool + FlashMagic is availabe from NXP). + o Change jumbers back to disable ISP. + o Use a terminal program to change the U-Boot settings via the console. + o U-Boot settings: + set ethaddr '00:1a:f1:X:X:X' + set serverip 'X.X.X.X' + set ipaddr 'X.X.X.X' + set rtems 'tftp a1000000 lpc2478.img;bootm' + set bootcmd 'echo Booting RTEMS ...;run rtems' + saveenv + +Howto make a U-Boot image? + +mkimage -A arm -O rtems -T kernel -C gzip \ + -a a0000000 -e a0000040 -n "RTEMS Application" -d app.bin.gz app.img + +Application Board: NCS (Nurse Control Station) + + Board: NextGenNCS + Processor: NXP LPC2478 or LPC2470 + SDRAM: 8MByte, 16 bit wide + Ext. Flash: 1MByte, 16 bit wide + Console: UART, 115200 Baud + Network: 100Base-T + +Application Board: TLI800 + TLI800 is a network node using four serial ports produced by Thorn + Security Limited. It is used by Tyco Fire & Integrated Solutions for a + fire control network. diff --git a/bsps/arm/lpc32xx/README b/bsps/arm/lpc32xx/README new file mode 100644 index 0000000000..465e23c39d --- /dev/null +++ b/bsps/arm/lpc32xx/README @@ -0,0 +1,6 @@ +Development board is phyCORE-LPC3250 RDK. Basic initialization via stage 1 +bootloader or U-Boot will be assumed. Drivers: + + o Standard UART 3, 4, 5, 6 (Console = 5, 115200N1) + o Clock uses TIMER 0 + o Ethernet diff --git a/bsps/arm/raspberrypi/README b/bsps/arm/raspberrypi/README new file mode 100644 index 0000000000..d0c32a748d --- /dev/null +++ b/bsps/arm/raspberrypi/README @@ -0,0 +1,65 @@ +BSP for the Raspberry Pi ARM board +This is a basic port that should work on either Model A or Model B. + +It currently supports the following devices: + o Console using the PL011 UART0 + The console driver only works with polled mode right now, + the interrupt code is there, but it does not work yet. + The console driver is currently hardcoded at 115k 8N1 + o Clock uses the internal ARM timer + The Raspberry Pi can be overclocked through the config.txt file, this + would affect the duration of the clock tick. + o Benchmark timer reads the lower 32 bit GPU timer register + +To run an RTEMS binary, it must be stripped and loaded on the SD card along with +the following files: + bootcode.bin + config.txt + loader.bin + start.elf + kernel.img ( the RTEMS binary, you can change the name in config.txt ) + +These files can be obtained from a Linux installation image, or from here: +https://github.com/raspberrypi/firmware + +I used an old 256MB SD card to boot RTEMS. +Much more information about the SD card file and bootloader can be found here: +http://elinux.org/RPi_Hub +http://www.raspberrypi.org + +The linker script is set up for 128MB, so it can be used with a GPU/ARM split +of 128/128. +The bootloader that is used on the SD card determines the split of RAM between the +ARM and the GPU. It might make sense to adjust the GPU/ARM memory split to give +more memory to RTEMS, especially on a 512MB board. + +To do: + It would be nice to get support in the BSP for the following: + o SD card + o USB and USB 10/100 network chip on Model B + o SPI + o GPIO + o ARM MMU + o Graphics console + o Sound + +Credits and links: + + There is a wealth of code and information to reference on the raspberrypi.org bare metal forums: + http://www.raspberrypi.org/phpBB3/viewforum.php?f=72 + + I found information about how to program the timers, interrupts, and UART 0 + from the examples provided by: + + David Welch: + https://github.com/dwelch67/raspberrypi + The readme file at his github repository has valuable information about connecting a UART cable, JTAG etc. + + Steve Bate: + http://www.stevebate.net/chibios-rpi/GettingStarted.html + Steve provided a port of the Chibios RTOS to the raspberry Pi + + James Walmsley: + http://www.raspberrypi.org/phpBB3/viewtopic.php?f=72&t=22423 + James ported FreeRTOS to the raspberry Pi. + diff --git a/bsps/arm/realview-pbx-a9/README b/bsps/arm/realview-pbx-a9/README new file mode 100644 index 0000000000..a4e6ac17f8 --- /dev/null +++ b/bsps/arm/realview-pbx-a9/README @@ -0,0 +1,15 @@ +Tested only on Qemu. + +git clone git://git.qemu.org/qemu.git qemu +cd qemu +git co a1bff71c56f2d1048244c829b63797940dd4ba0e +mkdir build +cd build +../configure --prefix=/opt/qemu --interp-prefix=/opt/qemu +make +make install +export PATH="$PATH:/opt/qemu/bin" + +qemu-system-arm -S -s -no-reboot -net none -nographic -M realview-pbx-a9 -m 256M -kernel ticker.exe + +qemu-system-arm -S -s -no-reboot -net none -nographic -smp 2 -icount auto -M realview-pbx-a9 -m 256M -kernel ticker.exe diff --git a/bsps/arm/rtl22xx/README b/bsps/arm/rtl22xx/README new file mode 100644 index 0000000000..ef8997f179 --- /dev/null +++ b/bsps/arm/rtl22xx/README @@ -0,0 +1,23 @@ +RTEMS BSP for Philips's ARM processor + +This BSP is designed for the following Philips' ARM microprocessors: + ++ LPC2210 ++ LPC2212 ++ LPC2214 ++ LPC2290 ++ LPC2294 + +Some LPC21xx ARM should also be able to use this BSP. + +Philphs's LPC22xx ARM processor has an ARM7TDMI-S core, and can +run at 60MHz. It has an external memory bus, and peripherals like +UART, I2C, SPI, ADC and etc. Some of them have on chip flash (256k) +and CAN. The board used to develop the BSP is compatible with +LPC-E2214/LPC-E2294 boards from http://www.olimex.com. The board has +a 512K SRAM (256K used to store the .text for debugging purposes) +and two serial ports. + +The license and distribution terms for this file may be found in +the file LICENSE in this distribution or at +http://www.rtems.org/license/LICENSE diff --git a/bsps/arm/smdk2410/README b/bsps/arm/smdk2410/README new file mode 100644 index 0000000000..6fc143a516 --- /dev/null +++ b/bsps/arm/smdk2410/README @@ -0,0 +1,9 @@ +SMDK2410 is a standard evaluation board for samsung s3c2410 ARM9 CPU + +This BSP was first developed by xiajiashan <ximenchuixue4016@sina.com>, +based on gp32 Apr/2007. +ZhiMing, Zhang <paopaoerzhang@gmail.com> fix timer defect and run +it on skeye. Ray, Xu merged this bsp with gp32 on Apr/2008 + +This BSP can be run on the Skyeye simulator. + diff --git a/bsps/arm/stm32f4/README b/bsps/arm/stm32f4/README new file mode 100644 index 0000000000..234f710a5f --- /dev/null +++ b/bsps/arm/stm32f4/README @@ -0,0 +1,5 @@ +Tested with STM32F4-Discovery evaluation board. + +For debugging on Linux use: + +https://github.com/texane/stlink diff --git a/bsps/arm/tms570/README b/bsps/arm/tms570/README new file mode 100644 index 0000000000..2a0bd4c8e4 --- /dev/null +++ b/bsps/arm/tms570/README @@ -0,0 +1,148 @@ +Development Board: TMS570LS31x Hercules Development Kit from TI + +http://www.ti.com/tool/tmds570ls31hdk + +Overview +-------- + +Drivers: + + o Console + o Clock + o Ethernet - external lwIP fork repository + +BSP variants: + tms570ls3137_hdk_intram - place code and data into internal SRAM + tms570ls3137_hdk_sdram - place code into external SDRAM and data to SRAM + tms570ls3137_hdk_with_loader - reserve 256kB at Flash start for loader + and place RTEMS application from address + 0x00040000 + tms570ls3137_hdk - variant for stand-alone RTEMS application stored + and running directly from flash. This variant + requires initialization of hardware to be integrated + into RTEMS. RTEMS has to be configured with + TMS570_USE_HWINIT_STARTUP=1 + and initialization code has to be included in the sources. + +Tool-chain used for development +------------------------------- + + arm-rtems4.12-gcc (GCC) 6.1.1 20160526 + Newlib 2.4.0.20160527 + Binutils 2.26.20160125 + + CFLAGS="-O2 -pipe" LDFLAGS=-s \ + ../../../src/gcc-6.1/configure --target=arm-rtems4.12 --prefix=/usr \ + --enable-languages=c,c++ \ + --disable-libstdcxx-pch \ + --with-gnu-ld \ + --with-gnu-as \ + --enable-threads \ + --enable-target-optspace \ + --with-system-zlib \ + --verbose \ + --disable-nls --without-included-gettext \ + --disable-win32-registry \ + --with-newlib \ + --enable-plugin \ + --enable-newlib-io-c99-formats \ + --enable-version-specific-runtime-libs \ + --enable-newlib-iconv \ + --disable-lto \ + --disable-lto \ + --enable-libgomp \ + --enable-newlib-iconv \ + --enable-newlib-iconv-encodings="iso_8859_1,utf_8" \ + +All patches required for Cortex-R and big-endian ARM support are already +integrated in GCC the mainline. + +RTEMS build configuration used for testing of self contained +applications to run directly from Flash + + ../../../src/rtems/configure --target=arm-rtems4.12 --prefix=/opt/rtems4.12 \ + --enable-rtems-inlines --disable-multiprocessing --enable-cxx \ + --enable-rdbg --enable-maintainer-mode --enable-tests=samples \ + --disable-networking --enable-posix --enable-itron --disable-ada \ + --disable-expada --disable-multilib --disable-docs \ + --enable-rtemsbsp="tms570ls3137_hdk" \ + --enable-rtems-debug \ + TMS570_USE_HWINIT_STARTUP=1 + +Execution +--------- + +Application build by above process can be directly programmed +into Flash and run. + +For test and debug purposes, TI's HalCoGen generated application +is used to set up the board and then the RTEMS application +image is loaded using OpenOCD to internal EEC SRAM or external SDRAM. +This prevents wear of Flash which has limited guaranteed +erase cycles count. + +The following features are implemented in the BSP only partially: + + + Initial CPU and peripheral initialization + + Cores Self-test + +Setup application code is available there: + https://github.com/hornmich/tms570ls3137-hdk-sdram + +TMDS570LS31HDK setup to use SDRAM to load and debug RTEMS applications +----------------------------------------------------------------------- + + o Program SDRAM_SCI_configuration-program or another boot loader + (for example ETHERNET XCP is developed) + o write BSP application either to sdram or intram and jump to RTEMS start code + +ETHERNET +-------- + +For ETHERNET, the lwIP port for TMS570LS3137 has been developed +at Industrial Informatics Group of Czech Technical University +in Prague and development versions are available on SourceForge. + +The RTEMS and TMS570 support is included in uLAN project lwIP +repository for now + + https://sourceforge.net/p/ulan/lwip-omk/ + +But other place should be found when RTEMS lwIP +integration with read, write, close etc. functions +is implemented in future. + +Adapt BSP for another TMS570 based hardware +------------------------------------------- + +When TMS570_USE_HWINIT_STARTUP=1 then quite complete +initialization and selft-test code is included in TMS570 +BSP build. The support included in hwinit subdirectory +provides version of bsp_start_hook_0 and bsp_start_hook_1 +which proceeds many self-tests functions, clocks, PLLs +peripherals and other subsystems configuration. + +Complete pin multiplexer initialization according +to the list of individual pins functions is included. +Pins function definition can be found and altered +in a file + + rtems/c/src/lib/libbsp/arm/tms570/hwinit/init_pinmux.c + +Complete "database" of all possible pin functions for +TMS570LS3137 chip is provided in a file + + rtems/c/src/lib/libbsp/arm/tms570/include/tms570ls3137zwt-pins.h + +If another package or chip is considered then tools found +in next repository can be used or extended to generate header +files and pins "database" + + https://github.com/AoLaD/rtems-tms570-utils + +Links to additional information +------------------------------- + +Additional information about the BSP and board can be found at + https://devel.rtems.org/wiki/TBR/BSP/Tms570 + +Additional information about the CPU can be found at + http://www.ti.com/product/tms570ls3137 diff --git a/bsps/arm/xilinx-zynq/README b/bsps/arm/xilinx-zynq/README new file mode 100644 index 0000000000..eef9159926 --- /dev/null +++ b/bsps/arm/xilinx-zynq/README @@ -0,0 +1,13 @@ +Tested only on Qemu. + +git clone git://git.qemu.org/qemu.git qemu +cd qemu +git checkout 1b0d3845b454eaaac0b2064c78926ca4d739a080 +mkdir build +cd build +../configure --prefix=/opt/qemu --interp-prefix=/opt/qemu +make +make install +export PATH="$PATH:/opt/qemu/bin" + +qemu-system-arm -no-reboot -serial null -serial mon:stdio -net none -nographic -M xilinx-zynq-a9 -m 256M -kernel ticker.exe |