Rework initialization and interrupt stack support

Statically initialize the interrupt stack area
(_Configuration_Interrupt_stack_area_begin,
_Configuration_Interrupt_stack_area_end, and
_Configuration_Interrupt_stack_size) via <rtems/confdefs.h>.  Place the
interrupt stack area in a special section ".rtemsstack.interrupt".  Let
BSPs define the optimal placement of this section in their linker
command files (e.g. in a fast on-chip memory).

This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and
CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the
low level initialization code has all information available via global
symbols.

This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define
superfluous, since the interrupt stacks are allocated by confdefs.h for
all architectures.  There is no need for BSP-specific linker command
file magic (except the section placement), see previous ARM linker
command file as a bad example.

Remove _CPU_Install_interrupt_stack().  Initialize the hardware
interrupt stack in _CPU_Initialize() if necessary (e.g.
m68k_install_interrupt_stack()).

The optional _CPU_Interrupt_stack_setup() is still useful to customize
the registration of the interrupt stack area in the per-CPU information.

The initialization stack can reuse the interrupt stack, since

  * interrupts are disabled during the sequential system initialization,
    and

  * the boot_card() function does not return.

This stack resuse saves memory.

Changes per architecture:

arm:

  * Mostly replace the linker symbol based configuration of stacks with
    the standard <rtems/confdefs.h> configuration via
    CONFIGURE_INTERRUPT_STACK_SIZE.  The size of the FIQ, ABT and UND
    mode stack is still defined via linker symbols.  These modes are
    rarely used in applications and the default values provided by the
    BSP should be sufficient in most cases.

  * Remove the bsp_processor_count linker symbol hack used for the SMP
    support. This is possible since the interrupt stack area is now
    allocated by the linker and not allocated from the heap.  This makes
    some configure.ac stuff obsolete.  Remove the now superfluous BSP
    variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp.

bfin:

  * Remove unused magic linker command file allocation of initialization
    stack.  Maybe a previous linker command file copy and paste problem?
    In the start.S the initialization stack is set to a hard coded value.

lm32, m32c, mips, nios2, riscv, sh, v850:

  * Remove magic linker command file allocation of initialization stack.
    Reuse interrupt stack for initialization stack.

m68k:

  * Remove magic linker command file allocation of initialization stack.
    Reuse interrupt stack for initialization stack.

powerpc:

  * Remove magic linker command file allocation of initialization stack.
    Reuse interrupt stack for initialization stack.

  * Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt
    stack on BSPs using the shared linkcmds.base (replacement for
    REGION_RWEXTRA).

sparc:

  * Remove the hard coded initialization stack.  Use the interrupt stack
    for the initialization stack on the boot processor.  This saves
    16KiB of RAM.

Update #3459.

18 files changed, 265 insertions, 471 deletions

diff --git a/bsps/arm/altera-cyclone-v/config/altcycv_devkit_smp.cfg b/bsps/arm/altera-cyclone-v/config/altcycv_devkit_smp.cfg
deleted file mode 100644
index ed54edfedd..0000000000
--- a/bsps/arm/altera-cyclone-v/config/altcycv_devkit_smp.cfg
+++ /dev/null
@@ -1 +0,0 @@
-include $(RTEMS_ROOT)/make/custom/altcycv.inc
diff --git a/bsps/arm/altera-cyclone-v/start/linkcmds.altcycv_devkit_smp b/bsps/arm/altera-cyclone-v/start/linkcmds.altcycv_devkit_smp
deleted file mode 100644
index 2da086579f..0000000000
--- a/bsps/arm/altera-cyclone-v/start/linkcmds.altcycv_devkit_smp
+++ /dev/null
@@ -1,3 +0,0 @@
-bsp_processor_count = DEFINED (bsp_processor_count) ? bsp_processor_count : 2;
-
-INCLUDE linkcmds.altcycv_devkit
diff --git a/bsps/arm/csb336/start/start.S b/bsps/arm/csb336/start/start.S
index ce452f52a2..2ef4cb71fa 100644
--- a/bsps/arm/csb336/start/start.S
+++ b/bsps/arm/csb336/start/start.S
@@ -8,20 +8,8 @@
  * http://www.rtems.org/license/LICENSE.
  */
 
-#include <bsp/linker-symbols.h>
-
-/* Some standard definitions...*/
-.equ PSR_MODE_USR,       0x10
-.equ PSR_MODE_FIQ,       0x11
-.equ PSR_MODE_IRQ,       0x12
-.equ PSR_MODE_SVC,       0x13
-.equ PSR_MODE_ABT,       0x17
-.equ PSR_MODE_UNDEF,     0x1B
-.equ PSR_MODE_SYS,       0x1F
-
-.equ PSR_I,              0x80
-.equ PSR_F,              0x40
-.equ PSR_T,              0x20
+#include <rtems/asm.h>
+#include <rtems/score/cpu.h>
 
 .section .bsp_start_text,"ax"
          .code 32
@@ -36,60 +24,56 @@ _start:
         /*
          * Since I don't plan to return to the bootloader,
          * I don't have to save the registers.
-         *
-         * I'll just set the CPSR for SVC mode, interrupts
-         * off, and ARM instructions.
          */
-        mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)
-        msr     cpsr, r0
-
-        /* zero the bss */
-        ldr     r1, =bsp_section_bss_end
-        ldr     r0, =bsp_section_bss_begin
-
-_bss_init:
-        mov     r2, #0
-        cmp     r0, r1
-        strlot  r2, [r0], #4
-        blo     _bss_init        /* loop while r0 < r1 */
-
 
-        /* --- Initialize stack pointer registers */
-        /* Enter IRQ mode and set up the IRQ stack pointer */
-        mov     r0, #(PSR_MODE_IRQ | PSR_I | PSR_F)     /* No interrupts */
-        msr     cpsr, r0
-        ldr     r1, =bsp_stack_irq_size
-        ldr     sp, =bsp_stack_irq_begin
-        add     sp, sp, r1
+        /* Set end of interrupt stack area */
+        ldr     r7, =_Configuration_Interrupt_stack_area_end
 
         /* Enter FIQ mode and set up the FIQ stack pointer */
-        mov     r0, #(PSR_MODE_FIQ | PSR_I | PSR_F)     /* No interrupts */
+        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
         msr     cpsr, r0
         ldr     r1, =bsp_stack_fiq_size
-        ldr     sp, =bsp_stack_fiq_begin
-        add     sp, sp, r1
+        mov     sp, r7
+        sub     r7, r7, r1
 
         /* Enter ABT mode and set up the ABT stack pointer */
-        mov     r0, #(PSR_MODE_ABT | PSR_I | PSR_F)     /* No interrupts */
+        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
         msr     cpsr, r0
         ldr     r1, =bsp_stack_abt_size
-        ldr     sp, =bsp_stack_abt_begin
-        add     sp, sp, r1
+        mov     sp, r7
+        sub     r7, r7, r1
 
-        /* Enter UNDEF mode and set up the UNDEF stack pointer */
-        mov     r0, #(PSR_MODE_UNDEF | PSR_I | PSR_F)     /* No interrupts */
+        /* Enter UND mode and set up the UND stack pointer */
+        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
         msr     cpsr, r0
         ldr     r1, =bsp_stack_und_size
-        ldr     sp, =bsp_stack_und_begin
-        add     sp, sp, r1
+        mov     sp, r7
+        sub     r7, r7, r1
 
-        /* Set up the SVC stack pointer last and stay in SVC mode */
-        mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)     /* No interrupts */
+        /* Enter IRQ mode and set up the IRQ stack pointer */
+        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
+        msr     cpsr, r0
+        mov     sp, r7
+
+        /*
+         * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
+         * (interrupts are disabled).
+         */
+        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
         msr     cpsr, r0
-        ldr     r1, =bsp_stack_svc_size
-        ldr     sp, =bsp_stack_svc_begin
-        add     sp, sp, r1
-        sub     sp, sp, #0x64
+        mov     sp, r7
+
+        /* Stay in SVC mode */
+
+        /* zero the bss */
+        ldr     r1, =bsp_section_bss_end
+        ldr     r0, =bsp_section_bss_begin
+
+_bss_init:
+        mov     r2, #0
+        cmp     r0, r1
+        strlot  r2, [r0], #4
+        blo     _bss_init        /* loop while r0 < r1 */
 
         /*
          * Initialize the MMU. After we return, the MMU is enabled,
diff --git a/bsps/arm/csb337/start/start.S b/bsps/arm/csb337/start/start.S
index f88cf41d78..a755864d0d 100644
--- a/bsps/arm/csb337/start/start.S
+++ b/bsps/arm/csb337/start/start.S
@@ -8,20 +8,8 @@
  *  http://www.rtems.org/license/LICENSE.
 */
 
-#include <bsp/linker-symbols.h>
-
-/* Some standard definitions...*/
-.equ PSR_MODE_USR,       0x10
-.equ PSR_MODE_FIQ,       0x11
-.equ PSR_MODE_IRQ,       0x12
-.equ PSR_MODE_SVC,       0x13
-.equ PSR_MODE_ABT,       0x17
-.equ PSR_MODE_UNDEF,     0x1B
-.equ PSR_MODE_SYS,       0x1F
-
-.equ PSR_I,              0x80
-.equ PSR_F,              0x40
-.equ PSR_T,              0x20
+#include <rtems/asm.h>
+#include <rtems/score/cpu.h>
 
 .text
 .globl  _start
@@ -29,53 +17,56 @@ _start:
         /*
          * Since I don't plan to return to the bootloader,
          * I don't have to save the registers.
-         *
-         * I'll just set the CPSR for SVC mode, interrupts
-         * off, and ARM instructions.
          */
-        mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)
-        msr     cpsr, r0
 
-        /* zero the bss */
-        ldr     r1, =bsp_section_bss_end
-        ldr     r0, =bsp_section_bss_begin
-
-_bss_init:
-        mov     r2, #0
-        cmp     r0, r1
-        strlot  r2, [r0], #4
-        blo     _bss_init        /* loop while r0 < r1 */
-
-
-        /* --- Initialize stack pointer registers */
-        /* Enter IRQ mode and set up the IRQ stack pointer */
-        mov     r0, #(PSR_MODE_IRQ | PSR_I | PSR_F)     /* No interrupts */
-        msr     cpsr, r0
-        ldr     r1, =bsp_stack_irq_size
-        ldr     sp, =bsp_stack_irq_begin
-        add     sp, sp, r1
+        /* Set end of interrupt stack area */
+        ldr     r7, =_Configuration_Interrupt_stack_area_end
 
         /* Enter FIQ mode and set up the FIQ stack pointer */
-        mov     r0, #(PSR_MODE_FIQ | PSR_I | PSR_F)     /* No interrupts */
+        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
         msr     cpsr, r0
         ldr     r1, =bsp_stack_fiq_size
-        ldr     sp, =bsp_stack_fiq_begin
-        add     sp, sp, r1
+        mov     sp, r7
+        sub     r7, r7, r1
 
         /* Enter ABT mode and set up the ABT stack pointer */
-        mov     r0, #(PSR_MODE_ABT | PSR_I | PSR_F)     /* No interrupts */
+        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
         msr     cpsr, r0
         ldr     r1, =bsp_stack_abt_size
-        ldr     sp, =bsp_stack_abt_begin
-        add     sp, sp, r1
+        mov     sp, r7
+        sub     r7, r7, r1
+
+        /* Enter UND mode and set up the UND stack pointer */
+        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
+        msr     cpsr, r0
+        ldr     r1, =bsp_stack_und_size
+        mov     sp, r7
+        sub     r7, r7, r1
 
-        /* Set up the SVC stack pointer last and stay in SVC mode */
-        mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)     /* No interrupts */
+        /* Enter IRQ mode and set up the IRQ stack pointer */
+        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
         msr     cpsr, r0
-        ldr     r1, =bsp_stack_svc_size
-        ldr     sp, =bsp_stack_svc_begin
-        add     sp, sp, r1
-        sub     sp, sp, #0x64
+        mov     sp, r7
+
+        /*
+         * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
+         * (interrupts are disabled).
+         */
+        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
+        msr     cpsr, r0
+        mov     sp, r7
+
+        /* Stay in SVC mode */
+
+        /* zero the bss */
+        ldr     r1, =bsp_section_bss_end
+        ldr     r0, =bsp_section_bss_begin
+
+_bss_init:
+        mov     r2, #0
+        cmp     r0, r1
+        strlot  r2, [r0], #4
+        blo     _bss_init        /* loop while r0 < r1 */
 
         /*
          * Initialize the MMU. After we return, the MMU is enabled,
diff --git a/bsps/arm/edb7312/start/start.S b/bsps/arm/edb7312/start/start.S
index e03707bfcf..5806d41ce4 100644
--- a/bsps/arm/edb7312/start/start.S
+++ b/bsps/arm/edb7312/start/start.S
@@ -12,21 +12,8 @@
  *  http://www.rtems.org/license/LICENSE.
 */
 
-#include <bsp/linker-symbols.h>
-
-/* Some standard definitions...*/
-
-.equ Mode_USR,        	     0x10
-.equ Mode_FIQ,        	     0x11
-.equ Mode_IRQ,        	     0x12
-.equ Mode_SVC,        	     0x13
-.equ Mode_ABT,        	     0x17
-.equ Mode_ABORT,             0x17
-.equ Mode_UNDEF,      	     0x1B
-.equ Mode_SYS,        	     0x1F /*only available on ARM Arch. v4*/
-
-.equ I_Bit,           	     0x80
-.equ F_Bit,           	     0x40
+#include <rtems/asm.h>
+#include <rtems/score/cpu.h>
 
 .section ".bsp_start_text", "ax"
 .arm
@@ -72,8 +59,44 @@ handler_addr_fiq:
 
 	.globl	_start
 _start:
-	/* store the sp */
-	mov	r12, sp
+        /* Set end of interrupt stack area */
+        ldr     r7, =_Configuration_Interrupt_stack_area_end
+
+        /* Enter FIQ mode and set up the FIQ stack pointer */
+        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
+        msr     cpsr, r0
+        ldr     r1, =bsp_stack_fiq_size
+        mov     sp, r7
+        sub     r7, r7, r1
+
+        /* Enter ABT mode and set up the ABT stack pointer */
+        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
+        msr     cpsr, r0
+        ldr     r1, =bsp_stack_abt_size
+        mov     sp, r7
+        sub     r7, r7, r1
+
+        /* Enter UND mode and set up the UND stack pointer */
+        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
+        msr     cpsr, r0
+        ldr     r1, =bsp_stack_und_size
+        mov     sp, r7
+        sub     r7, r7, r1
+
+        /* Enter IRQ mode and set up the IRQ stack pointer */
+        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
+        msr     cpsr, r0
+        mov     sp, r7
+
+        /*
+         * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
+         * (interrupts are disabled).
+         */
+        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
+        msr     cpsr, r0
+        mov     sp, r7
+
+        /* Stay in SVC mode */
 /*
  * Here is the code to initialize the low-level BSP environment
  * (Chip Select, PLL, ....?)
@@ -89,48 +112,7 @@ zi_init:
         STRLOT   r2, [r0], #4
         BLO     zi_init
 
-/* --- Initialise stack pointer registers */
-
-/* Enter IRQ mode and set up the IRQ stack pointer */
-    MOV     r0, #Mode_IRQ | I_Bit | F_Bit     /* No interrupts */
-    MSR     cpsr, r0
-    ldr	    r1, =bsp_stack_irq_size
-    LDR     sp, =bsp_stack_irq_begin
-    add	    sp, sp, r1
-    sub     sp, sp, #0x64
-
-/* Enter FIQ mode and set up the FIQ stack pointer */
-    MOV     r0, #Mode_FIQ | I_Bit | F_Bit     /* No interrupts */
-    MSR     cpsr, r0
-    ldr	    r1, =bsp_stack_fiq_size
-    LDR     sp, =bsp_stack_fiq_begin
-    add	    sp, sp, r1
-    sub     sp, sp, #0x64
-
-/* Enter ABT mode and set up the ABT stack pointer */
-    MOV     r0, #Mode_ABT | I_Bit | F_Bit     /* No interrupts */
-    MSR     cpsr, r0
-    ldr	    r1, =bsp_stack_abt_size
-    LDR     sp, =bsp_stack_abt_begin
-    add	    sp, sp, r1
-    sub     sp, sp, #0x64
-
-/* Set up the SVC stack pointer last and stay in SVC mode */
-    MOV     r0, #Mode_SVC | I_Bit | F_Bit     /* No interrupts */
-    MSR     cpsr, r0
-    ldr	    r1, =bsp_stack_svc_size
-    LDR     sp, =bsp_stack_svc_begin
-    add	    sp, sp, r1
-    sub     sp, sp, #0x64
-
-	/* save the original registers */
-	stmdb	sp!, {r4-r12, lr}
-
 /* --- Now we enter the C code */
 
 	mov     r0, #0
 	bl	boot_card
-
-	ldmia	sp!, {r4-r12, lr}
-	mov	sp, r12
-	mov	pc, lr
diff --git a/bsps/arm/gumstix/start/start.S b/bsps/arm/gumstix/start/start.S
index dccc99993e..7c71bdacf1 100644
--- a/bsps/arm/gumstix/start/start.S
+++ b/bsps/arm/gumstix/start/start.S
@@ -7,20 +7,8 @@
  *  http://www.rtems.org/license/LICENSE.
  */
 
-#include <bsp/linker-symbols.h>
-
-/* Some standard definitions...*/
-.equ PSR_MODE_USR,       0x10
-.equ PSR_MODE_FIQ,       0x11
-.equ PSR_MODE_IRQ,       0x12
-.equ PSR_MODE_SVC,       0x13
-.equ PSR_MODE_ABT,       0x17
-.equ PSR_MODE_UNDEF,     0x1B
-.equ PSR_MODE_SYS,       0x1F
-
-.equ PSR_I,              0x80
-.equ PSR_F,              0x40
-.equ PSR_T,              0x20
+#include <rtems/asm.h>
+#include <rtems/score/cpu.h>
 
 .text
 .globl  _start
@@ -28,53 +16,56 @@ _start:
         /*
          * Since I don't plan to return to the bootloader,
          * I don't have to save the registers.
-         *
-         * I'll just set the CPSR for SVC mode, interrupts
-         * off, and ARM instructions.
          */
-        mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)
-        msr     cpsr, r0
 
-
-        /* zero the bss */
-        ldr     r1, =bsp_section_bss_end
-        ldr     r0, =bsp_section_bss_begin
-
-_bss_init:
-        mov     r2, #0
-        cmp     r0, r1
-        strlot  r2, [r0], #4
-        blo     _bss_init        /* loop while r0 < r1 */
-
-        /* --- Initialize stack pointer registers */
-        /* Enter IRQ mode and set up the IRQ stack pointer */
-        mov     r0, #(PSR_MODE_IRQ | PSR_I | PSR_F)     /* No interrupts */
-        msr     cpsr, r0
-        ldr     r1, =bsp_stack_irq_size
-        ldr     sp, =bsp_stack_irq_begin
-        add     sp, sp, r1
+        /* Set end of interrupt stack area */
+        ldr     r7, =_Configuration_Interrupt_stack_area_end
 
         /* Enter FIQ mode and set up the FIQ stack pointer */
-        mov     r0, #(PSR_MODE_FIQ | PSR_I | PSR_F)     /* No interrupts */
+        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
         msr     cpsr, r0
         ldr     r1, =bsp_stack_fiq_size
-        ldr     sp, =bsp_stack_fiq_begin
-        add     sp, sp, r1
+        mov     sp, r7
+        sub     r7, r7, r1
 
         /* Enter ABT mode and set up the ABT stack pointer */
-        mov     r0, #(PSR_MODE_ABT | PSR_I | PSR_F)     /* No interrupts */
+        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
         msr     cpsr, r0
         ldr     r1, =bsp_stack_abt_size
-        ldr     sp, =bsp_stack_abt_begin
-        add     sp, sp, r1
+        mov     sp, r7
+        sub     r7, r7, r1
 
-        /* Set up the SVC stack pointer last and stay in SVC mode */
-        mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)     /* No interrupts */
+        /* Enter UND mode and set up the UND stack pointer */
+        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
         msr     cpsr, r0
         ldr     r1, =bsp_stack_und_size
-        ldr     sp, =bsp_stack_und_begin
-        add     sp, sp, r1
-        sub     sp, sp, #0x64
+        mov     sp, r7
+        sub     r7, r7, r1
+
+        /* Enter IRQ mode and set up the IRQ stack pointer */
+        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
+        msr     cpsr, r0
+        mov     sp, r7
+
+        /*
+         * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
+         * (interrupts are disabled).
+         */
+        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
+        msr     cpsr, r0
+        mov     sp, r7
+
+        /* Stay in SVC mode */
+
+        /* zero the bss */
+        ldr     r1, =bsp_section_bss_end
+        ldr     r0, =bsp_section_bss_begin
+
+_bss_init:
+        mov     r2, #0
+        cmp     r0, r1
+        strlot  r2, [r0], #4
+        blo     _bss_init        /* loop while r0 < r1 */
 
         /*
          * Initialize the MMU. After we return, the MMU is enabled,
diff --git a/bsps/arm/imx/start/linkcmds.imx7 b/bsps/arm/imx/start/linkcmds.imx7
index 750e1def1d..0d9fe48bf9 100644
--- a/bsps/arm/imx/start/linkcmds.imx7
+++ b/bsps/arm/imx/start/linkcmds.imx7
@@ -22,9 +22,6 @@ REGION_ALIAS ("REGION_STACK", RAM);
 REGION_ALIAS ("REGION_NOCACHE", NOCACHE);
 REGION_ALIAS ("REGION_NOCACHE_LOAD", NOCACHE);
 
-bsp_processor_count = DEFINED (bsp_processor_count) ? bsp_processor_count : 2;
-
-bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 4096;
 bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024;
 
 bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M;
diff --git a/bsps/arm/include/bsp/linker-symbols.h b/bsps/arm/include/bsp/linker-symbols.h
index 1a996f51f2..135c85f215 100644
--- a/bsps/arm/include/bsp/linker-symbols.h
+++ b/bsps/arm/include/bsp/linker-symbols.h
@@ -43,30 +43,11 @@ extern "C" {
   #define LINKER_SYMBOL(sym) .extern sym
 #endif
 
-LINKER_SYMBOL(bsp_stack_irq_begin)
-LINKER_SYMBOL(bsp_stack_irq_end)
-LINKER_SYMBOL(bsp_stack_irq_size)
-
-LINKER_SYMBOL(bsp_stack_fiq_begin)
-LINKER_SYMBOL(bsp_stack_fiq_end)
-LINKER_SYMBOL(bsp_stack_irq_size)
-
-LINKER_SYMBOL(bsp_stack_abt_begin)
-LINKER_SYMBOL(bsp_stack_abt_end)
+LINKER_SYMBOL(bsp_stack_fiq_size)
 LINKER_SYMBOL(bsp_stack_abt_size)
-
-LINKER_SYMBOL(bsp_stack_und_begin)
-LINKER_SYMBOL(bsp_stack_und_end)
 LINKER_SYMBOL(bsp_stack_und_size)
-
-LINKER_SYMBOL(bsp_stack_hyp_begin)
-LINKER_SYMBOL(bsp_stack_hyp_end)
 LINKER_SYMBOL(bsp_stack_hyp_size)
 
-LINKER_SYMBOL(bsp_stack_svc_begin)
-LINKER_SYMBOL(bsp_stack_svc_end)
-LINKER_SYMBOL(bsp_stack_svc_size)
-
 LINKER_SYMBOL(bsp_section_start_begin)
 LINKER_SYMBOL(bsp_section_start_end)
 LINKER_SYMBOL(bsp_section_start_size)
@@ -156,8 +137,6 @@ LINKER_SYMBOL(bsp_translation_table_end)
 #define BSP_NOCACHENOLOAD_SUBSECTION(subsection) \
   __attribute__((section(".bsp_noload_nocache." # subsection)))
 
-LINKER_SYMBOL(bsp_processor_count)
-
 /** @} */
 
 #ifdef __cplusplus
diff --git a/bsps/arm/raspberrypi/start/bspsmp.c b/bsps/arm/raspberrypi/start/bspsmp.c
index c3e5451442..44f7a1d376 100644
--- a/bsps/arm/raspberrypi/start/bspsmp.c
+++ b/bsps/arm/raspberrypi/start/bspsmp.c
@@ -57,12 +57,7 @@ bool _CPU_SMP_Start_processor( uint32_t cpu_index )
 
 uint32_t _CPU_SMP_Initialize(void)
 {
-  uint32_t cpu_count = (uint32_t)bsp_processor_count;
-
-  if ( cpu_count > 4 )
-    cpu_count = 4;
-
-  return cpu_count;
+  return 4;
 }
 
 void _CPU_SMP_Finalize_initialization( uint32_t cpu_count )
diff --git a/bsps/arm/raspberrypi/start/linkcmds.in b/bsps/arm/raspberrypi/start/linkcmds
index 829716c11c..58423abecb 100644
--- a/bsps/arm/raspberrypi/start/linkcmds.in
+++ b/bsps/arm/raspberrypi/start/linkcmds
@@ -41,8 +41,6 @@ MEMORY {
         RAM            (AIW) : ORIGIN = 0x00008000, LENGTH = 128M - 32k
 }
 
-bsp_processor_count = DEFINED (bsp_processor_count) ? bsp_processor_count : @RASPBERRYPI_CPUS@;
-
 REGION_ALIAS ("REGION_START", RAM);
 REGION_ALIAS ("REGION_VECTOR", VECTOR_RAM);
 REGION_ALIAS ("REGION_TEXT", RAM);
@@ -61,7 +59,6 @@ REGION_ALIAS ("REGION_STACK", RAM);
 REGION_ALIAS ("REGION_NOCACHE", RAM);
 REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM);
 
-bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 3008;
 bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024;
 
 bsp_section_robarrier_align = DEFINED (bsp_section_robarrier_align) ? bsp_section_robarrier_align : 1M;
diff --git a/bsps/arm/realview-pbx-a9/config/realview_pbx_a9_qemu_smp.cfg b/bsps/arm/realview-pbx-a9/config/realview_pbx_a9_qemu_smp.cfg
deleted file mode 100644
index fd51a18004..0000000000
--- a/bsps/arm/realview-pbx-a9/config/realview_pbx_a9_qemu_smp.cfg
+++ /dev/null
@@ -1 +0,0 @@
-include $(RTEMS_ROOT)/make/custom/realview_pbx_a9_qemu.cfg
diff --git a/bsps/arm/realview-pbx-a9/start/linkcmds.realview_pbx_a9_qemu_smp b/bsps/arm/realview-pbx-a9/start/linkcmds.realview_pbx_a9_qemu_smp
deleted file mode 100644
index d31c4f08ae..0000000000
--- a/bsps/arm/realview-pbx-a9/start/linkcmds.realview_pbx_a9_qemu_smp
+++ /dev/null
@@ -1,3 +0,0 @@
-bsp_processor_count = DEFINED (bsp_processor_count) ? bsp_processor_count : 8;
-
-INCLUDE linkcmds.realview_pbx_a9_qemu
diff --git a/bsps/arm/rtl22xx/start/start.S b/bsps/arm/rtl22xx/start/start.S
index c038198aff..0fc265493d 100644
--- a/bsps/arm/rtl22xx/start/start.S
+++ b/bsps/arm/rtl22xx/start/start.S
@@ -8,20 +8,8 @@
  *  http://www.rtems.org/license/LICENSE.
 */
 
-#include <bsp/linker-symbols.h>
-
-/* Some standard definitions...*/
-.equ PSR_MODE_USR,       0x10
-.equ PSR_MODE_FIQ,       0x11
-.equ PSR_MODE_IRQ,       0x12
-.equ PSR_MODE_SVC,       0x13
-.equ PSR_MODE_ABT,       0x17
-.equ PSR_MODE_UNDEF,     0x1B
-.equ PSR_MODE_SYS,       0x1F
-
-.equ PSR_I,              0x80
-.equ PSR_F,              0x40
-.equ PSR_T,              0x20
+#include <rtems/asm.h>
+#include <rtems/score/cpu.h>
 
 .text
 .code	32
@@ -30,45 +18,46 @@ _start:
         /*
          * Since I don't plan to return to the bootloader,
          * I don't have to save the registers.
-         *
-         * I'll just set the CPSR for SVC mode, interrupts
-         * off, and ARM instructions.
          */
 
-        /* --- Initialize stack pointer registers */
-        /* Enter IRQ mode and set up the IRQ stack pointer */
-        mov     r0, #(PSR_MODE_IRQ | PSR_I | PSR_F)     /* No interrupts */
-        bic	r0, r0, #PSR_T
-        msr     cpsr, r0
-        ldr     r1, =bsp_stack_irq_size
-        ldr     sp, =bsp_stack_irq_begin
-        add     sp, sp, r1
+        /* Set end of interrupt stack area */
+        ldr     r7, =_Configuration_Interrupt_stack_area_end
 
         /* Enter FIQ mode and set up the FIQ stack pointer */
-        mov     r0, #(PSR_MODE_FIQ | PSR_I | PSR_F)     /* No interrupts */
-        bic	r0, r0, #PSR_T
+        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
         msr     cpsr, r0
         ldr     r1, =bsp_stack_fiq_size
-        ldr     sp, =bsp_stack_fiq_begin
-        add     sp, sp, r1
+        mov     sp, r7
+        sub     r7, r7, r1
 
         /* Enter ABT mode and set up the ABT stack pointer */
-        mov     r0, #(PSR_MODE_ABT | PSR_I | PSR_F)     /* No interrupts */
-        bic	r0, r0, #PSR_T
+        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
         msr     cpsr, r0
-        bic	r0, r0, #PSR_T
         ldr     r1, =bsp_stack_abt_size
-        ldr     sp, =bsp_stack_abt_begin
-        add     sp, sp, r1
+        mov     sp, r7
+        sub     r7, r7, r1
+
+        /* Enter UND mode and set up the UND stack pointer */
+        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
+        msr     cpsr, r0
+        ldr     r1, =bsp_stack_und_size
+        mov     sp, r7
+        sub     r7, r7, r1
 
-        /* Set up the SVC stack pointer last and stay in SVC mode */
-        mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)     /* No interrupts */
-        bic	r0, r0, #PSR_T
+        /* Enter IRQ mode and set up the IRQ stack pointer */
+        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
+        msr     cpsr, r0
+        mov     sp, r7
+
+        /*
+         * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
+         * (interrupts are disabled).
+         */
+        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
         msr     cpsr, r0
-        ldr     r1, =bsp_stack_svc_size
-        ldr     sp, =bsp_stack_svc_begin
-        add     sp, sp, r1
-        sub     sp, sp, #0x64
+        mov     sp, r7
+
+        /* Stay in SVC mode */
 
         /*
          * Initialize the exception vectors. This includes the
diff --git a/bsps/arm/shared/start/arm-a9mpcore-smp.c b/bsps/arm/shared/start/arm-a9mpcore-smp.c
index a3a95f4ea2..a8d3a541d4 100644
--- a/bsps/arm/shared/start/arm-a9mpcore-smp.c
+++ b/bsps/arm/shared/start/arm-a9mpcore-smp.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2015 embedded brains GmbH.  All rights reserved.
+ * Copyright (c) 2013, 2018 embedded brains GmbH.  All rights reserved.
  *
  *  embedded brains GmbH
  *  Dornierstr. 4
@@ -19,7 +19,6 @@
 #include <libcpu/arm-cp15.h>
 
 #include <bsp/irq.h>
-#include <bsp/linker-symbols.h>
 
 static void bsp_inter_processor_interrupt(void *arg)
 {
@@ -28,10 +27,7 @@ static void bsp_inter_processor_interrupt(void *arg)
 
 uint32_t _CPU_SMP_Initialize(void)
 {
-  uint32_t hardware_count = arm_gic_irq_processor_count();
-  uint32_t linker_count = (uint32_t) bsp_processor_count;
-
-  return hardware_count <= linker_count ? hardware_count : linker_count;
+  return arm_gic_irq_processor_count();
 }
 
 void _CPU_SMP_Finalize_initialization(uint32_t cpu_count)
diff --git a/bsps/arm/shared/start/linkcmds.base b/bsps/arm/shared/start/linkcmds.base
index 5a669d87a8..cab8e85674 100644
--- a/bsps/arm/shared/start/linkcmds.base
+++ b/bsps/arm/shared/start/linkcmds.base
@@ -45,25 +45,12 @@ bsp_stack_abt_size = ALIGN (bsp_stack_abt_size, bsp_stack_align);
 bsp_stack_fiq_size = DEFINED (bsp_stack_fiq_size) ? bsp_stack_fiq_size : 0;
 bsp_stack_fiq_size = ALIGN (bsp_stack_fiq_size, bsp_stack_align);
 
-bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 0;
-bsp_stack_irq_size = ALIGN (bsp_stack_irq_size, bsp_stack_align);
-
-bsp_stack_svc_size = DEFINED (bsp_stack_svc_size) ? bsp_stack_svc_size : 0;
-bsp_stack_svc_size = ALIGN (bsp_stack_svc_size, bsp_stack_align);
-
 bsp_stack_und_size = DEFINED (bsp_stack_und_size) ? bsp_stack_und_size : 0;
 bsp_stack_und_size = ALIGN (bsp_stack_und_size, bsp_stack_align);
 
 bsp_stack_hyp_size = DEFINED (bsp_stack_hyp_size) ? bsp_stack_hyp_size : 0;
 bsp_stack_hyp_size = ALIGN (bsp_stack_hyp_size, bsp_stack_align);
 
-bsp_stack_main_size = DEFINED (bsp_stack_main_size) ? bsp_stack_main_size : 0;
-bsp_stack_main_size = ALIGN (bsp_stack_main_size, bsp_stack_align);
-
-bsp_stack_all_size = bsp_stack_abt_size + bsp_stack_fiq_size + bsp_stack_irq_size + bsp_stack_svc_size + bsp_stack_und_size + bsp_stack_hyp_size + bsp_stack_main_size;
-
-bsp_processor_count = DEFINED (bsp_processor_count) ? bsp_processor_count : 1;
-
 MEMORY {
 	UNEXPECTED_SECTIONS : ORIGIN = 0xffffffff, LENGTH = 0
 }
@@ -297,44 +284,7 @@ SECTIONS {
 
 	.vector : ALIGN_WITH_INPUT {
 		bsp_section_vector_begin = .;
-
 		. = . + DEFINED (bsp_vector_table_in_start_section) ? 0 : bsp_vector_table_size;
-
-		. = ALIGN (bsp_stack_align);
-
-		bsp_stack_irq_begin = .;
-		. = . + bsp_stack_irq_size;
-		bsp_stack_irq_end = .;
-
-		bsp_stack_svc_begin = .;
-		. = . + bsp_stack_svc_size;
-		bsp_stack_svc_end = .;
-
-		bsp_stack_fiq_begin = .;
-		. = . + bsp_stack_fiq_size;
-		bsp_stack_fiq_end = .;
-
-		bsp_stack_und_begin = .;
-		. = . + bsp_stack_und_size;
-		bsp_stack_und_end = .;
-
-		bsp_stack_hyp_begin = .;
-		. = . + bsp_stack_hyp_size;
-		bsp_stack_hyp_end = .;
-
-		bsp_stack_abt_begin = .;
-		. = . + bsp_stack_abt_size;
-		bsp_stack_abt_end = .;
-
-		bsp_stack_main_begin = .;
-		. = . + bsp_stack_main_size;
-		bsp_stack_main_end = .;
-
-		bsp_stack_secondary_processors_begin = .;
-		. = . + (bsp_processor_count - 1) * bsp_stack_all_size;
-		bsp_stack_secondary_processors_end = .;
-
-		*(.bsp_vector)
 	} > REGION_VECTOR AT > REGION_VECTOR
 	.rtemsstack (NOLOAD) : {
 		*(SORT(.rtemsstack.*))
diff --git a/bsps/arm/shared/start/start.S b/bsps/arm/shared/start/start.S
index aa0f3782c9..148625ff97 100644
--- a/bsps/arm/shared/start/start.S
+++ b/bsps/arm/shared/start/start.S
@@ -5,7 +5,7 @@
  */
 
 /*
- * Copyright (c) 2008, 2016 embedded brains GmbH.  All rights reserved.
+ * Copyright (c) 2008, 2018 embedded brains GmbH.  All rights reserved.
  *
  *  embedded brains GmbH
  *  Dornierstr. 4
@@ -19,45 +19,10 @@
  */
 
 #include <rtems/asm.h>
-#include <rtems/system.h>	
 #include <rtems/score/percpu.h>
-	
+
 #include <bspopts.h>
 #include <bsp/irq.h>
-#include <bsp/linker-symbols.h>
-
-	/* External symbols */
-	.extern	bsp_reset
-	.extern	boot_card
-	.extern	bsp_start_hook_0
-	.extern	bsp_start_hook_1
-	.extern bsp_stack_irq_end
-	.extern bsp_stack_fiq_end
-	.extern bsp_stack_abt_end
-	.extern bsp_stack_und_end
-	.extern bsp_stack_svc_end
-#ifdef RTEMS_SMP
-	.extern bsp_stack_all_size
-#endif
-	.extern	_ARMV4_Exception_undef_default
-	.extern	_ARMV4_Exception_swi_default
-	.extern	_ARMV4_Exception_data_abort_default
-	.extern	_ARMV4_Exception_pref_abort_default
-	.extern	_ARMV4_Exception_reserved_default
-	.extern	_ARMV4_Exception_interrupt
-	.extern	_ARMV4_Exception_fiq_default
-	.extern	_ARMV7M_Exception_default
-
-#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
-	.extern bsp_start_init_registers_core
-	.extern bsp_start_init_registers_banked_fiq
-	.extern bsp_start_init_registers_vfp
-#endif
-
-#ifdef BSP_START_IN_HYP_SUPPORT
-	.extern	bsp_start_arm_drop_hyp_mode
-	.globl	bsp_start_hyp_vector_table_begin
-#endif
 
 	/* Global symbols */
 	.globl	_start
@@ -65,12 +30,17 @@
 	.globl	bsp_start_vector_table_end
 	.globl	bsp_start_vector_table_size
 	.globl	bsp_vector_table_size
-	.globl	bsp_start_hook_0_done
 
 	.section	".bsp_start_text", "ax"
 
 #if defined(ARM_MULTILIB_ARCH_V4)
 
+	.globl	bsp_start_hook_0_done
+
+#ifdef BSP_START_IN_HYP_SUPPORT
+	.globl	bsp_start_hyp_vector_table_begin
+#endif
+
 	.arm
 
 /*
@@ -208,12 +178,20 @@ _start:
 	add	r1, r1, r7, asl #PER_CPU_CONTROL_SIZE_LOG2
 	mcr	p15, 0, r1, c13, c0, 4
 
-	/* Calculate stack offset */
-	ldr	r1, =bsp_stack_all_size
-	mul	r1, r7
 #endif
 
-	mrs	r4, cpsr	/* save original procesor status value  */
+	/* Calculate interrupt stack area end for current processor */
+	ldr	r1, =_Configuration_Interrupt_stack_size
+#ifdef RTEMS_SMP
+	add	r7, #1
+	mul	r1, r1, r7
+#endif
+	ldr	r2, =_Configuration_Interrupt_stack_area_begin
+	add	r7, r1, r2
+
+	/* Save original CPSR value */
+	mrs	r4, cpsr
+
 #ifdef BSP_START_IN_HYP_SUPPORT
 	orr	r0, r4, #(ARM_PSR_I | ARM_PSR_F)
 	msr	cpsr, r4
@@ -222,38 +200,22 @@ _start:
 	cmp	r0, #ARM_PSR_M_HYP
 	bne	bsp_start_skip_hyp_svc_switch
 
-	/* Boot loader stats kernel in HYP mode, switch to SVC necessary */
-	ldr	sp, =bsp_stack_hyp_end
-#ifdef RTEMS_SMP
-	add	sp, r1
-#endif
+	/* Boot loader starts kernel in HYP mode, switch to SVC necessary */
+	ldr	r1, =bsp_stack_hyp_size
+	mov	sp, r7
+	sub	r7, r7, r1
 	bl	bsp_start_arm_drop_hyp_mode
 
 bsp_start_skip_hyp_svc_switch:
 #endif
-	/*
-	 * Set SVC mode, disable interrupts and enable ARM instructions.
-	 */
-	mov	r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
-	msr	cpsr, r0
-
 	/* Initialize stack pointer registers for the various modes */
 
-	/* Enter IRQ mode and set up the IRQ stack pointer */
-	mov	r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
-	msr	cpsr, r0
-	ldr	sp, =bsp_stack_irq_end
-#ifdef RTEMS_SMP
-	add	sp, r1
-#endif
-
 	/* Enter FIQ mode and set up the FIQ stack pointer */
 	mov	r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
 	msr	cpsr, r0
-	ldr	sp, =bsp_stack_fiq_end
-#ifdef RTEMS_SMP
-	add	sp, r1
-#endif
+	ldr	r1, =bsp_stack_fiq_size
+	mov	sp, r7
+	sub	r7, r7, r1
 
 #ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
 	bl bsp_start_init_registers_banked_fiq
@@ -262,26 +224,29 @@ bsp_start_skip_hyp_svc_switch:
 	/* Enter ABT mode and set up the ABT stack pointer */
 	mov	r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
 	msr	cpsr, r0
-	ldr	sp, =bsp_stack_abt_end
-#ifdef RTEMS_SMP
-	add	sp, r1
-#endif
+	ldr	r1, =bsp_stack_abt_size
+	mov	sp, r7
+	sub	r7, r7, r1
 
 	/* Enter UND mode and set up the UND stack pointer */
 	mov	r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
 	msr	cpsr, r0
-	ldr	sp, =bsp_stack_und_end
-#ifdef RTEMS_SMP
-	add	sp, r1
-#endif
+	ldr	r1, =bsp_stack_und_size
+	mov	sp, r7
+	sub	r7, r7, r1
+
+	/* Enter IRQ mode and set up the IRQ stack pointer */
+	mov	r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
+	msr	cpsr, r0
+	mov	sp, r7
 
-	/* Enter SVC mode and set up the SVC stack pointer */
+	/*
+	 * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
+	 * (interrupts are disabled).
+	 */
 	mov	r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
 	msr	cpsr, r0
-	ldr	sp, =bsp_stack_svc_end
-#ifdef RTEMS_SMP
-	add	sp, r1
-#endif
+	mov	sp, r7
 
 	/* Stay in SVC mode */
 
@@ -333,7 +298,7 @@ bsp_start_skip_hyp_svc_switch:
 
 	SWITCH_FROM_ARM_TO_THUMB	r0
 
-	mov	r0, r4		/* original cpsr value */
+	mov	r0, r4		/* original CPSR value */
 	mov	r1, r5		/* machine type number or ~0 for DT boot */
 	mov	r2, r6		/* physical address of ATAGs or DTB */
 
@@ -385,13 +350,11 @@ twiddle:
 
 	.syntax	unified
 
-	.extern	bsp_stack_main_end
-
 	.thumb
 
 bsp_start_vector_table_begin:
 
-	.word	bsp_stack_main_end
+	.word	_Configuration_Interrupt_stack_area_end
 	.word	_start /* Reset */
 	.word	_ARMV7M_Exception_default /* NMI */
 	.word	_ARMV7M_Exception_default /* Hard Fault */
@@ -441,7 +404,7 @@ _start:
 
 #endif /* ARM_MULTILIB_VFP */
 
-	ldr	sp, =bsp_stack_main_end
+	ldr	sp, =_Configuration_Interrupt_stack_area_end
 	ldr	lr, =bsp_start_hook_0_done + 1
 	b	bsp_start_hook_0
 
diff --git a/bsps/arm/smdk2410/start/start.S b/bsps/arm/smdk2410/start/start.S
index 95d781cb89..b8d1ddefa0 100644
--- a/bsps/arm/smdk2410/start/start.S
+++ b/bsps/arm/smdk2410/start/start.S
@@ -8,20 +8,8 @@
  *  http://www.rtems.org/license/LICENSE.
  */
 
-#include <bsp/linker-symbols.h>
-
-/* Some standard definitions...*/
-.equ PSR_MODE_USR,       0x10
-.equ PSR_MODE_FIQ,       0x11
-.equ PSR_MODE_IRQ,       0x12
-.equ PSR_MODE_SVC,       0x13
-.equ PSR_MODE_ABT,       0x17
-.equ PSR_MODE_UNDEF,     0x1B
-.equ PSR_MODE_SYS,       0x1F
-
-.equ PSR_I,              0x80
-.equ PSR_F,              0x40
-.equ PSR_T,              0x20
+#include <rtems/asm.h>
+#include <rtems/score/cpu.h>
 
 .text
 .globl  _start
@@ -65,43 +53,46 @@ _start2:
         /*
          * Since I don't plan to return to the bootloader,
          * I don't have to save the registers.
-         *
-         * I'll just set the CPSR for SVC mode, interrupts
-         * off, and ARM instructions.
          */
-        mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)
-        msr     cpsr, r0
 
-        /* --- Initialize stack pointer registers */
-        /* Enter IRQ mode and set up the IRQ stack pointer */
-        mov     r0, #(PSR_MODE_IRQ | PSR_I | PSR_F)     /* No interrupts */
-        msr     cpsr, r0
-        ldr     r1, =bsp_stack_irq_size
-        ldr     sp, =bsp_stack_irq_begin
-        add     sp, sp, r1
+        /* Set end of interrupt stack area */
+        ldr     r7, =_Configuration_Interrupt_stack_area_end
 
         /* Enter FIQ mode and set up the FIQ stack pointer */
-        mov     r0, #(PSR_MODE_FIQ | PSR_I | PSR_F)     /* No interrupts */
+        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
         msr     cpsr, r0
         ldr     r1, =bsp_stack_fiq_size
-        ldr     sp, =bsp_stack_fiq_begin
-        add     sp, sp, r1
+        mov     sp, r7
+        sub     r7, r7, r1
 
         /* Enter ABT mode and set up the ABT stack pointer */
-        mov     r0, #(PSR_MODE_ABT | PSR_I | PSR_F)     /* No interrupts */
+        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
         msr     cpsr, r0
         ldr     r1, =bsp_stack_abt_size
-        ldr     sp, =bsp_stack_abt_begin
-        add     sp, sp, r1
+        mov     sp, r7
+        sub     r7, r7, r1
+
+        /* Enter UND mode and set up the UND stack pointer */
+        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
+        msr     cpsr, r0
+        ldr     r1, =bsp_stack_und_size
+        mov     sp, r7
+        sub     r7, r7, r1
+
+        /* Enter IRQ mode and set up the IRQ stack pointer */
+        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
+        msr     cpsr, r0
+        mov     sp, r7
 
-        /* Set up the SVC stack pointer last and stay in SVC mode */
-        mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)     /* No interrupts */
+        /*
+         * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
+         * (interrupts are disabled).
+         */
+        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
         msr     cpsr, r0
-        ldr     r1, =bsp_stack_svc_size
-        ldr     sp, =bsp_stack_svc_begin
-        add     sp, sp, r1
-        sub     sp, sp, #0x64
+        mov     sp, r7
 
+        /* Stay in SVC mode */
 
 	/* disable mmu, I and D caches*/
 	nop
diff --git a/bsps/arm/xilinx-zynq/start/linkcmds.in b/bsps/arm/xilinx-zynq/start/linkcmds.in
index 7fd6e2772d..b56309bf37 100644
--- a/bsps/arm/xilinx-zynq/start/linkcmds.in
+++ b/bsps/arm/xilinx-zynq/start/linkcmds.in
@@ -6,8 +6,6 @@ MEMORY {
    NOCACHE   : ORIGIN = @ZYNQ_RAM_ORIGIN_AVAILABLE@ + @ZYNQ_RAM_LENGTH_AVAILABLE@ - @ZYNQ_RAM_NOCACHE_LENGTH@, LENGTH = @ZYNQ_RAM_NOCACHE_LENGTH@
 }
 
-bsp_processor_count = DEFINED (bsp_processor_count) ? bsp_processor_count : @ZYNQ_CPUS@;
-
 REGION_ALIAS ("REGION_START",          RAM);
 REGION_ALIAS ("REGION_VECTOR",         RAM);
 REGION_ALIAS ("REGION_TEXT",           RAM);
@@ -26,7 +24,6 @@ REGION_ALIAS ("REGION_STACK",          RAM);
 REGION_ALIAS ("REGION_NOCACHE",        NOCACHE);
 REGION_ALIAS ("REGION_NOCACHE_LOAD",   NOCACHE);
 
-bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 4096;
 bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024;
 
 bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M;