bsp/tms570: Board-specific tms570_map_clock_init()

Update #4982.

4 files changed, 187 insertions, 109 deletions

diff --git a/bsps/arm/tms570/include/bsp/tms570_hwinit.h b/bsps/arm/tms570/include/bsp/tms570_hwinit.h
index 2a178ceb05..eca4a5e7cc 100644
--- a/bsps/arm/tms570/include/bsp/tms570_hwinit.h
+++ b/bsps/arm/tms570/include/bsp/tms570_hwinit.h
@@ -75,7 +75,6 @@ void tms570_pinmux_init( void );
 void tms570_trim_lpo_init( void );
 void tms570_flash_init( void );
 void tms570_periph_init( void );
-void tms570_map_clock_init( void );
 void tms570_system_hw_init( void );
 void tms570_esm_init( void );
 
@@ -90,4 +89,11 @@ void tms570_esm_init( void );
  */
 void tms570_pll_init(void);
 
+/**
+ * @brief Initialize the tms570 Global Clock Manager (GCM) registers which
+ *   sub-divide the input clock source (generally PLL) into the various
+ *   peripheral clocks (VCLK1-3, etc).
+ */
+void tms570_map_clock_init(void);
+
 #endif /* LIBBSP_ARM_TMS570_HWINIT_H */
diff --git a/bsps/arm/tms570/start/hwinit-lc4357-hdk.c b/bsps/arm/tms570/start/hwinit-lc4357-hdk.c
index 6a8a2f1a86..a57536be30 100644
--- a/bsps/arm/tms570/start/hwinit-lc4357-hdk.c
+++ b/bsps/arm/tms570/start/hwinit-lc4357-hdk.c
@@ -137,3 +137,75 @@ void tms570_pll_init( void )
     // Enable all clock sources except the following
     TMS570_SYS1.CSDIS = (TMS570_CLKDIS_SRC_EXT_CLK2 | TMS570_CLKDIS_SRC_EXT_CLK1 | TMS570_CLKDIS_SRC_RESERVED);
 }
+
+void tms570_map_clock_init(void)
+{
+    // based on HalCoGen mapClocks method
+    uint32_t sys_csvstat, sys_csdis;
+
+    TMS570_SYS2.HCLKCNTL = 1U;
+
+    /** @b Initialize @b Clock @b Tree: */
+    /** - Disable / Enable clock domain */
+    TMS570_SYS1.CDDIS = ( 0U << 4U ) |  /* AVCLK 1 ON */
+                        ( 1U << 5U ) |  /* AVCLK 2 OFF */
+                        ( 0U << 8U ) |  /* VCLK3 ON */
+                        ( 0U << 9U ) |  /* VCLK4 ON */
+                        ( 0U << 10U ) | /* AVCLK 3 ON */
+                        ( 0U << 11U );  /* AVCLK 4 ON */
+
+    /* Work Around for Errata SYS#46:
+    * Despite this being a LS3137 errata, hardware testing on the LC4357 indicates this wait is still necessary
+    */
+    sys_csvstat = TMS570_SYS1.CSVSTAT;
+    sys_csdis = TMS570_SYS1.CSDIS;
+
+    while ( ( sys_csvstat & ( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) !=
+            ( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) {
+        sys_csvstat = TMS570_SYS1.CSVSTAT;
+        sys_csdis = TMS570_SYS1.CSDIS;
+    }
+
+    TMS570_SYS1.GHVSRC =  TMS570_SYS1_GHVSRC_GHVWAKE(TMS570_SYS_CLK_SRC_PLL1)
+                        | TMS570_SYS1_GHVSRC_HVLPM(TMS570_SYS_CLK_SRC_PLL1)
+                        | TMS570_SYS1_GHVSRC_GHVSRC(TMS570_SYS_CLK_SRC_PLL1);
+
+    /** - Setup RTICLK1 and RTICLK2 clocks */
+    TMS570_SYS1.RCLKSRC = ((uint32_t)1U << 24U)        /* RTI2 divider (Not applicable for lock-step device)  */
+                        | ((uint32_t)TMS570_SYS_CLK_SRC_VCLK << 16U) /* RTI2 clock source (Not applicable for lock-step device) Field not in TRM? */
+                        | ((uint32_t)1U << 8U)         /* RTI1 divider */
+                        | ((uint32_t)TMS570_SYS_CLK_SRC_VCLK << 0U); /* RTI1 clock source */
+
+    /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */
+    TMS570_SYS1.VCLKASRC =  TMS570_SYS1_VCLKASRC_VCLKA2S(TMS570_SYS_CLK_SRC_VCLK)
+                        | TMS570_SYS1_VCLKASRC_VCLKA1S(TMS570_SYS_CLK_SRC_VCLK);
+
+    /** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */
+
+    // VCLK2 = PLL1 / HCLK_DIV / 2 = 75MHz
+    TMS570_SYS1.CLKCNTL  = (TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLK2R(0xF))
+                        | TMS570_SYS1_CLKCNTL_VCLK2R(0x1);
+    // VLCK1 = PLL1 / HCLK_DIV / 2 = 75MHz
+    TMS570_SYS1.CLKCNTL  = (TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLKR(0xF))
+                        | TMS570_SYS1_CLKCNTL_VCLKR(0x1);
+
+    // VCLK3 = PLL1 / HCLK_DIV / 3 = 50MHz
+    TMS570_SYS2.CLK2CNTRL = (TMS570_SYS2.CLK2CNTRL & ~TMS570_SYS2_CLK2CNTRL_VCLK3R(0xF))
+                        | TMS570_SYS2_CLK2CNTRL_VCLK3R(0x2);
+
+    TMS570_SYS2.VCLKACON1 =   TMS570_SYS2_VCLKACON1_VCLKA4R(1U - 1U)
+                            | (TMS570_SYS2_VCLKACON1_VCLKA4_DIV_CDDIS * 0)
+                            | TMS570_SYS2_VCLKACON1_VCLKA4S(TMS570_SYS_CLK_SRC_VCLK)
+                            | TMS570_SYS2_VCLKACON1_VCLKA3R(1U - 1U)
+                            | (TMS570_SYS2_VCLKACON1_VCLKA3_DIV_CDDIS * 0)
+                            | TMS570_SYS2_VCLKACON1_VCLKA3S(TMS570_SYS_CLK_SRC_VCLK);
+
+    /* Now the PLLs are locked and the PLL outputs can be sped up */
+    /* The R-divider was programmed to be 0xF. Now this divider is changed to programmed value */
+    TMS570_SYS1.PLLCTL1 = (TMS570_SYS1.PLLCTL1 & 0xE0FFFFFFU) | (uint32_t)((uint32_t)(1U - 1U) << 24U);
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> " Clear and write to the volatile register " */
+    TMS570_SYS2.PLLCTL3 = (TMS570_SYS2.PLLCTL3 & 0xE0FFFFFFU) | (uint32_t)((uint32_t)(1U - 1U) << 24U);
+
+    /* Enable/Disable Frequency modulation */
+    TMS570_SYS1.PLLCTL2 |= 0x00000000U;
+}
diff --git a/bsps/arm/tms570/start/hwinit-ls3137-hdk.c b/bsps/arm/tms570/start/hwinit-ls3137-hdk.c
index 772352470f..e4b7cef336 100644
--- a/bsps/arm/tms570/start/hwinit-ls3137-hdk.c
+++ b/bsps/arm/tms570/start/hwinit-ls3137-hdk.c
@@ -45,6 +45,17 @@
 #include <bsp/tms570.h>
 #include <bsp/tms570_hwinit.h>
 
+enum tms570_system_clock_source {
+  TMS570_SYS_CLK_SRC_OSC = 0U,          /**< Alias for oscillator clock Source                */
+  TMS570_SYS_CLK_SRC_PLL1 = 1U,         /**< Alias for Pll1 clock Source                      */
+  TMS570_SYS_CLK_SRC_EXTERNAL1 = 3U,    /**< Alias for external clock Source                  */
+  TMS570_SYS_CLK_SRC_LPO_LOW = 4U,      /**< Alias for low power oscillator low clock Source  */
+  TMS570_SYS_CLK_SRC_LPO_HIGH = 5U,     /**< Alias for low power oscillator high clock Source */
+  TMS570_SYS_CLK_SRC_PLL2 = 6U,         /**< Alias for Pll2 clock Source                      */
+  TMS570_SYS_CLK_SRC_EXTERNAL2 = 7U,    /**< Alias for external 2 clock Source                */
+  TMS570_SYS_CLK_SRC_VCLK = 9U          /**< Alias for synchronous VCLK1 clock Source         */
+};
+
 /**
  * @brief Setup all system PLLs (HCG:setupPLL)
  *
@@ -100,3 +111,100 @@ void tms570_pll_init( void )
                       0x00000000 | /* CLKSR6 on */
                       0x00000080;  /* CLKSR7 off */
 }
+
+/**
+ * @brief Setup chip clocks including to wait for PLLs locks (HCG:mapClocks)
+ *
+ */
+/* SourceId : SYSTEM_SourceId_005 */
+/* DesignId : SYSTEM_DesignId_005 */
+/* Requirements : HL_SR469 */
+void tms570_map_clock_init( void )
+{
+  uint32_t sys_csvstat, sys_csdis;
+
+  /** @b Initialize @b Clock @b Tree: */
+  /** - Disable / Enable clock domain */
+  TMS570_SYS1.CDDIS = ( 0U << 4U ) |  /* AVCLK 1 OFF */
+                      ( 0U << 5U ) |  /* AVCLK 2 OFF */
+                      ( 0U << 8U ) |  /* VCLK3 OFF */
+                      ( 0U << 9U ) |  /* VCLK4 OFF */
+                      ( 1U << 10U ) | /* AVCLK 3 OFF */
+                      ( 0U << 11U );  /* AVCLK 4 OFF */
+
+  /* Work Around for Errata SYS#46:
+   *
+   * Errata Description:
+   *            Clock Source Switching Not Qualified with Clock Source Enable And Clock Source Valid
+   * Workaround:
+   *            Always check the CSDIS register to make sure the clock source is turned on and check
+   * the CSVSTAT register to make sure the clock source is valid. Then write to GHVSRC to switch the clock.
+   */
+  /** - Wait for until clocks are locked */
+  sys_csvstat = TMS570_SYS1.CSVSTAT;
+  sys_csdis = TMS570_SYS1.CSDIS;
+
+  while ( ( sys_csvstat & ( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) !=
+          ( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) {
+    sys_csvstat = TMS570_SYS1.CSVSTAT;
+    sys_csdis = TMS570_SYS1.CSDIS;
+  } /* Wait */
+
+  /* Now the PLLs are locked and the PLL outputs can be sped up */
+  /* The R-divider was programmed to be 0xF. Now this divider is changed to programmed value */
+  TMS570_SYS1.PLLCTL1 =
+    ( TMS570_SYS1.PLLCTL1 & ~TMS570_SYS1_PLLCTL1_PLLDIV( 0x1F ) ) |
+    TMS570_SYS1_PLLCTL1_PLLDIV( 1 - 1 );
+  /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+  TMS570_SYS2.PLLCTL3 =
+    ( TMS570_SYS2.PLLCTL3 & ~TMS570_SYS2_PLLCTL3_PLLDIV2( 0x1F ) ) |
+    TMS570_SYS2_PLLCTL3_PLLDIV2( 1 - 1 );
+
+  /* Enable/Disable Frequency modulation */
+  TMS570_SYS1.PLLCTL2 &= ~TMS570_SYS1_PLLCTL2_FMENA;
+
+  /** - Map device clock domains to desired sources and configure top-level dividers */
+  /** - All clock domains are working off the default clock sources until now */
+  /** - The below assignments can be easily modified using the HALCoGen GUI */
+
+  /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */
+  TMS570_SYS1.GHVSRC = TMS570_SYS1_GHVSRC_GHVWAKE( TMS570_SYS_CLK_SRC_OSC ) |
+                       TMS570_SYS1_GHVSRC_HVLPM( TMS570_SYS_CLK_SRC_OSC ) |
+                       TMS570_SYS1_GHVSRC_GHVSRC( TMS570_SYS_CLK_SRC_PLL1 );
+
+  /** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */
+  TMS570_SYS1.CLKCNTL =
+    ( TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLK2R( 0xF ) ) |
+    TMS570_SYS1_CLKCNTL_VCLK2R( 1 );
+
+  TMS570_SYS1.CLKCNTL =
+    ( TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLKR( 0xF ) ) |
+    TMS570_SYS1_CLKCNTL_VCLKR( 1 );
+
+  TMS570_SYS2.CLK2CNTRL =
+    ( TMS570_SYS2.CLK2CNTRL & ~TMS570_SYS2_CLK2CNTRL_VCLK3R( 0xF ) ) |
+    TMS570_SYS2_CLK2CNTRL_VCLK3R( 1 );
+
+  TMS570_SYS2.CLK2CNTRL = ( TMS570_SYS2.CLK2CNTRL & 0xFFFFF0FFU ) |
+                          ( 1U << 8U ); /* FIXME: unknown in manual*/
+
+  /** - Setup RTICLK1 and RTICLK2 clocks */
+  TMS570_SYS1.RCLKSRC = ( 1U << 24U ) |
+                        ( TMS570_SYS_CLK_SRC_VCLK << 16U ) | /* FIXME: not in manual */
+                        TMS570_SYS1_RCLKSRC_RTI1DIV( 1 ) |
+                        TMS570_SYS1_RCLKSRC_RTI1SRC( TMS570_SYS_CLK_SRC_VCLK );
+
+  /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */
+  TMS570_SYS1.VCLKASRC =
+    TMS570_SYS1_VCLKASRC_VCLKA2S( TMS570_SYS_CLK_SRC_VCLK ) |
+    TMS570_SYS1_VCLKASRC_VCLKA1S( TMS570_SYS_CLK_SRC_VCLK );
+
+  TMS570_SYS2.VCLKACON1 = TMS570_SYS2_VCLKACON1_VCLKA4R( 1 - 1 ) |
+                          TMS570_SYS2_VCLKACON1_VCLKA4_DIV_CDDIS * 0 |
+                          TMS570_SYS2_VCLKACON1_VCLKA4S(
+    TMS570_SYS_CLK_SRC_VCLK ) |
+                          TMS570_SYS2_VCLKACON1_VCLKA3R( 1 - 1 ) |
+                          TMS570_SYS2_VCLKACON1_VCLKA3_DIV_CDDIS * 0 |
+                          TMS570_SYS2_VCLKACON1_VCLKA3S(
+    TMS570_SYS_CLK_SRC_VCLK );
+}
diff --git a/bsps/arm/tms570/start/init_system.c b/bsps/arm/tms570/start/init_system.c
index b5387bfbc2..4d2c2ef29f 100644
--- a/bsps/arm/tms570/start/init_system.c
+++ b/bsps/arm/tms570/start/init_system.c
@@ -75,17 +75,6 @@ enum tms570_flash_power_modes {
   TMS570_FLASH_SYS_ACTIVE = 3U     /**< Alias for flash bank power mode active  */
 };
 
-enum tms570_system_clock_source {
-  TMS570_SYS_CLK_SRC_OSC = 0U,          /**< Alias for oscillator clock Source                */
-  TMS570_SYS_CLK_SRC_PLL1 = 1U,         /**< Alias for Pll1 clock Source                      */
-  TMS570_SYS_CLK_SRC_EXTERNAL1 = 3U,    /**< Alias for external clock Source                  */
-  TMS570_SYS_CLK_SRC_LPO_LOW = 4U,      /**< Alias for low power oscillator low clock Source  */
-  TMS570_SYS_CLK_SRC_LPO_HIGH = 5U,     /**< Alias for low power oscillator high clock Source */
-  TMS570_SYS_CLK_SRC_PLL2 = 6U,         /**< Alias for Pll2 clock Source                      */
-  TMS570_SYS_CLK_SRC_EXTERNAL2 = 7U,    /**< Alias for external 2 clock Source                */
-  TMS570_SYS_CLK_SRC_VCLK = 9U          /**< Alias for synchronous VCLK1 clock Source         */
-};
-
 /**
  * @brief Setup Flash memory parameters and timing (HCG:setupFlash)
  *
@@ -154,103 +143,6 @@ void tms570_periph_init( void )
 }
 
 /**
- * @brief Setup chip clocks including to wait for PLLs locks (HCG:mapClocks)
- *
- */
-/* SourceId : SYSTEM_SourceId_005 */
-/* DesignId : SYSTEM_DesignId_005 */
-/* Requirements : HL_SR469 */
-void tms570_map_clock_init( void )
-{
-  uint32_t sys_csvstat, sys_csdis;
-
-  /** @b Initialize @b Clock @b Tree: */
-  /** - Disable / Enable clock domain */
-  TMS570_SYS1.CDDIS = ( 0U << 4U ) |  /* AVCLK 1 OFF */
-                      ( 0U << 5U ) |  /* AVCLK 2 OFF */
-                      ( 0U << 8U ) |  /* VCLK3 OFF */
-                      ( 0U << 9U ) |  /* VCLK4 OFF */
-                      ( 1U << 10U ) | /* AVCLK 3 OFF */
-                      ( 0U << 11U );  /* AVCLK 4 OFF */
-
-  /* Work Around for Errata SYS#46:
-   *
-   * Errata Description:
-   *            Clock Source Switching Not Qualified with Clock Source Enable And Clock Source Valid
-   * Workaround:
-   *            Always check the CSDIS register to make sure the clock source is turned on and check
-   * the CSVSTAT register to make sure the clock source is valid. Then write to GHVSRC to switch the clock.
-   */
-  /** - Wait for until clocks are locked */
-  sys_csvstat = TMS570_SYS1.CSVSTAT;
-  sys_csdis = TMS570_SYS1.CSDIS;
-
-  while ( ( sys_csvstat & ( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) !=
-          ( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) {
-    sys_csvstat = TMS570_SYS1.CSVSTAT;
-    sys_csdis = TMS570_SYS1.CSDIS;
-  } /* Wait */
-
-  /* Now the PLLs are locked and the PLL outputs can be sped up */
-  /* The R-divider was programmed to be 0xF. Now this divider is changed to programmed value */
-  TMS570_SYS1.PLLCTL1 =
-    ( TMS570_SYS1.PLLCTL1 & ~TMS570_SYS1_PLLCTL1_PLLDIV( 0x1F ) ) |
-    TMS570_SYS1_PLLCTL1_PLLDIV( 1 - 1 );
-  /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
-  TMS570_SYS2.PLLCTL3 =
-    ( TMS570_SYS2.PLLCTL3 & ~TMS570_SYS2_PLLCTL3_PLLDIV2( 0x1F ) ) |
-    TMS570_SYS2_PLLCTL3_PLLDIV2( 1 - 1 );
-
-  /* Enable/Disable Frequency modulation */
-  TMS570_SYS1.PLLCTL2 &= ~TMS570_SYS1_PLLCTL2_FMENA;
-
-  /** - Map device clock domains to desired sources and configure top-level dividers */
-  /** - All clock domains are working off the default clock sources until now */
-  /** - The below assignments can be easily modified using the HALCoGen GUI */
-
-  /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */
-  TMS570_SYS1.GHVSRC = TMS570_SYS1_GHVSRC_GHVWAKE( TMS570_SYS_CLK_SRC_OSC ) |
-                       TMS570_SYS1_GHVSRC_HVLPM( TMS570_SYS_CLK_SRC_OSC ) |
-                       TMS570_SYS1_GHVSRC_GHVSRC( TMS570_SYS_CLK_SRC_PLL1 );
-
-  /** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */
-  TMS570_SYS1.CLKCNTL =
-    ( TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLK2R( 0xF ) ) |
-    TMS570_SYS1_CLKCNTL_VCLK2R( 1 );
-
-  TMS570_SYS1.CLKCNTL =
-    ( TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLKR( 0xF ) ) |
-    TMS570_SYS1_CLKCNTL_VCLKR( 1 );
-
-  TMS570_SYS2.CLK2CNTRL =
-    ( TMS570_SYS2.CLK2CNTRL & ~TMS570_SYS2_CLK2CNTRL_VCLK3R( 0xF ) ) |
-    TMS570_SYS2_CLK2CNTRL_VCLK3R( 1 );
-
-  TMS570_SYS2.CLK2CNTRL = ( TMS570_SYS2.CLK2CNTRL & 0xFFFFF0FFU ) |
-                          ( 1U << 8U ); /* FIXME: unknown in manual*/
-
-  /** - Setup RTICLK1 and RTICLK2 clocks */
-  TMS570_SYS1.RCLKSRC = ( 1U << 24U ) |
-                        ( TMS570_SYS_CLK_SRC_VCLK << 16U ) | /* FIXME: not in manual */
-                        TMS570_SYS1_RCLKSRC_RTI1DIV( 1 ) |
-                        TMS570_SYS1_RCLKSRC_RTI1SRC( TMS570_SYS_CLK_SRC_VCLK );
-
-  /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */
-  TMS570_SYS1.VCLKASRC =
-    TMS570_SYS1_VCLKASRC_VCLKA2S( TMS570_SYS_CLK_SRC_VCLK ) |
-    TMS570_SYS1_VCLKASRC_VCLKA1S( TMS570_SYS_CLK_SRC_VCLK );
-
-  TMS570_SYS2.VCLKACON1 = TMS570_SYS2_VCLKACON1_VCLKA4R( 1 - 1 ) |
-                          TMS570_SYS2_VCLKACON1_VCLKA4_DIV_CDDIS * 0 |
-                          TMS570_SYS2_VCLKACON1_VCLKA4S(
-    TMS570_SYS_CLK_SRC_VCLK ) |
-                          TMS570_SYS2_VCLKACON1_VCLKA3R( 1 - 1 ) |
-                          TMS570_SYS2_VCLKACON1_VCLKA3_DIV_CDDIS * 0 |
-                          TMS570_SYS2_VCLKACON1_VCLKA3S(
-    TMS570_SYS_CLK_SRC_VCLK );
-}
-
-/**
  * @brief TMS570 system hardware initialization (HCG:systemInit)
  *
  */