bsps/arm: Clear SCTLR[M, I, A, C] in start.S

Initialize the data and unified cache levels.  Invalidate the
instruction cache levels.

Update #4202.

1 files changed, 3 insertions, 34 deletions

diff --git a/bsps/arm/xilinx-zynq/start/bspstarthooks.c b/bsps/arm/xilinx-zynq/start/bspstarthooks.c
index 0fc2a2590d..25cf96abdb 100644
--- a/bsps/arm/xilinx-zynq/start/bspstarthooks.c
+++ b/bsps/arm/xilinx-zynq/start/bspstarthooks.c
@@ -29,45 +29,14 @@
 
 #include <bsp.h>
 #include <bsp/start.h>
-#include <bsp/arm-cp15-start.h>
 #include <bsp/arm-a9mpcore-start.h>
 
+#include <libcpu/arm-cp15.h>
+
 BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
 {
-  uint32_t sctlr_val;
-
-  sctlr_val = arm_cp15_get_control();
-
-  /*
-   * Current U-boot loader seems to start kernel image
-   * with I and D caches on and MMU enabled.
-   * If RTEMS application image finds that cache is on
-   * during startup then disable caches.
-   */
-  if ( sctlr_val & (ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M ) ) {
-    if ( sctlr_val & (ARM_CP15_CTRL_C | ARM_CP15_CTRL_M ) ) {
-      /*
-       * If the data cache is on then ensure that it is clean
-       * before switching off to be extra carefull.
-       */
-      arm_cp15_data_cache_clean_all_levels();
-    }
-    arm_cp15_flush_prefetch_buffer();
-    sctlr_val &= ~ ( ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M | ARM_CP15_CTRL_A );
-    arm_cp15_set_control( sctlr_val );
-  }
-  arm_cp15_instruction_cache_invalidate();
-  /*
-   * The care should be taken there that no shared levels
-   * are invalidated by secondary CPUs in SMP case.
-   * It is not problem on Zynq because level of coherency
-   * is L1 only and higher level is not maintained and seen
-   * by CP15. So no special care to limit levels on the secondary
-   * are required there.
-   */
-  arm_cp15_data_cache_invalidate_all_levels();
   arm_cp15_tlb_invalidate();
-  arm_cp15_flush_prefetch_buffer();
+  _ARM_Instruction_synchronization_barrier()
   arm_a9mpcore_start_hook_0();
 }