bsps/stm32h7: update STM32 H7 HAL

This patch updates STM32 H7 HAL source files. The files are taken from two
STM projects from their github.com repositories:

(i)
https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git

The project files are still available under BSD-3 license
and the version/commit used is:

d5fc8d05fc16fa2a2a2f948cf6c6ab39e78358e1

which represents post Release v1.11.1 development tree.

(ii)
https://github.com/STMicroelectronics/cmsis_device_h7.git

The project files were re-licensed from previous BSD-3 to Apache 2.0
license. Fortunately the project does not contain NOTICE file so no need
to do anything special when used in RTEMS.

The project version/commit imported is:

6d5ef249bec5177e0e2a0880ed62df2132874d99

which is code-wise Release v1.10.3 exactly.

1 files changed, 90 insertions, 60 deletions

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_pwr.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_pwr.h
index 5da346f890..be137a46fc 100644
--- a/bsps/arm/stm32h7/include/stm32h7xx_ll_pwr.h
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_pwr.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -35,7 +34,6 @@ extern "C" {
 #if defined (PWR)
 
 /** @defgroup PWR_LL PWR
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 
@@ -43,12 +41,10 @@ extern "C" {
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
 /** @defgroup PWR_LL_Private_Constants PWR Private Constants
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 
 /** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @brief    Flags defines which can be used with LL_PWR_WriteReg function
   * @{
   */
@@ -65,12 +61,10 @@ extern "C" {
 /* Exported types ------------------------------------------------------------*/
 /* Exported constants --------------------------------------------------------*/
 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 
 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @brief    Flags defines which can be used with LL_PWR_WriteReg function
   * @{
   */
@@ -79,9 +73,13 @@ extern "C" {
 #define LL_PWR_FLAG_CPU2_CSSF         PWR_CPU2CR_CSSF     /*!< Clear flags for CPU2 */
 #endif /* DUAL_CORE */
 #define LL_PWR_FLAG_WKUPCR_WKUPC6     PWR_WKUPCR_WKUPC6   /*!< Clear PC1 WKUP flag  */
+#if defined (PWR_WKUPCR_WKUPC5)
 #define LL_PWR_FLAG_WKUPCR_WKUPC5     PWR_WKUPCR_WKUPC5   /*!< Clear PI11 WKUP flag */
+#endif /* defined (PWR_WKUPCR_WKUPC5) */
 #define LL_PWR_FLAG_WKUPCR_WKUPC4     PWR_WKUPCR_WKUPC4   /*!< Clear PC13 WKUP flag */
+#if defined (PWR_WKUPCR_WKUPC3)
 #define LL_PWR_FLAG_WKUPCR_WKUPC3     PWR_WKUPCR_WKUPC3   /*!< Clear PI8 WKUP flag  */
+#endif /* defined (PWR_WKUPCR_WKUPC3) */
 #define LL_PWR_FLAG_WKUPCR_WKUPC2     PWR_WKUPCR_WKUPC2   /*!< Clear PA2 WKUP flag  */
 #define LL_PWR_FLAG_WKUPCR_WKUPC1     PWR_WKUPCR_WKUPC1   /*!< Clear PA0 WKUP flag  */
 /**
@@ -89,7 +87,6 @@ extern "C" {
   */
 
 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @brief    Flags defines which can be used with LL_PWR_ReadReg function
   * @{
   */
@@ -137,9 +134,13 @@ extern "C" {
 #endif /* PWR_CPUCR_PDDS_D2 */
 
 #define LL_PWR_WKUPFR_WKUPF6          PWR_WKUPFR_WKUPF6   /*!< Wakeup flag on PC1  */
+#if defined (PWR_WKUPFR_WKUPF5)
 #define LL_PWR_WKUPFR_WKUPF5          PWR_WKUPFR_WKUPF5   /*!< Wakeup flag on PI11 */
+#endif /* defined (PWR_WKUPFR_WKUPF5) */
 #define LL_PWR_WKUPFR_WKUPF4          PWR_WKUPFR_WKUPF4   /*!< Wakeup flag on PC13 */
+#if defined (PWR_WKUPFR_WKUPF3)
 #define LL_PWR_WKUPFR_WKUPF3          PWR_WKUPFR_WKUPF3   /*!< Wakeup flag on PI8  */
+#endif /* defined (PWR_WKUPFR_WKUPF3) */
 #define LL_PWR_WKUPFR_WKUPF2          PWR_WKUPFR_WKUPF2   /*!< Wakeup flag on PA2  */
 #define LL_PWR_WKUPFR_WKUPF1          PWR_WKUPFR_WKUPF1   /*!< Wakeup flag on PA0  */
 /**
@@ -147,7 +148,6 @@ extern "C" {
   */
 
 /** @defgroup PWR_LL_EC_MODE_PWR Power mode
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 #if defined (PWR_CPUCR_PDDS_D2)
@@ -187,15 +187,18 @@ extern "C" {
   */
 
 /** @defgroup PWR_LL_EC_REGU_VOLTAGE Run mode Regulator Voltage Scaling
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 #if defined (PWR_CPUCR_PDDS_D2)
 #define LL_PWR_REGU_VOLTAGE_SCALE3      PWR_D3CR_VOS_0                    /*!< Select voltage scale 3 */
 #define LL_PWR_REGU_VOLTAGE_SCALE2      PWR_D3CR_VOS_1                    /*!< Select voltage scale 2 */
 #define LL_PWR_REGU_VOLTAGE_SCALE1      (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 1 */
+#if defined (SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */
 #define LL_PWR_REGU_VOLTAGE_SCALE0      (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */
 #else
+#define LL_PWR_REGU_VOLTAGE_SCALE0      0x00000000U                       /*!< Select voltage scale 0 */
+#endif /* defined (SYSCFG_PWRCR_ODEN) */
+#else
 #define LL_PWR_REGU_VOLTAGE_SCALE3      0x00000000U                       /*!< Select voltage scale 3 */
 #define LL_PWR_REGU_VOLTAGE_SCALE2      PWR_D3CR_VOS_0                    /*!< Select voltage scale 2 */
 #define LL_PWR_REGU_VOLTAGE_SCALE1      PWR_D3CR_VOS_1                    /*!< Select voltage scale 1 */
@@ -206,7 +209,6 @@ extern "C" {
   */
 
 /** @defgroup PWR_LL_EC_STOP_MODE_REGU_VOLTAGE Stop mode Regulator Voltage Scaling
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 #define LL_PWR_REGU_VOLTAGE_SVOS_SCALE5   PWR_CR1_SVOS_0                    /*!< Select voltage scale 5 when system enters STOP mode */
@@ -217,7 +219,6 @@ extern "C" {
   */
 
 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 #define LL_PWR_REGU_DSMODE_MAIN           0x00000000U   /*!< Voltage Regulator in main mode during deepsleep mode      */
@@ -227,7 +228,6 @@ extern "C" {
   */
 
 /** @defgroup PWR_LL_EC_PVDLEVEL Power Digital Voltage Level Detector
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 #define LL_PWR_PVDLEVEL_0   PWR_CR1_PLS_LEV0  /*!< Voltage threshold detected by PVD 1.95 V */
@@ -243,7 +243,6 @@ extern "C" {
   */
 
 /** @defgroup PWR_LL_EC_AVDLEVEL Power Analog Voltage Level Detector
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 #define LL_PWR_AVDLEVEL_0   PWR_CR1_ALS_LEV0  /*!< Analog Voltage threshold detected by AVD 1.7 V */
@@ -256,7 +255,6 @@ extern "C" {
   */
 
 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR Battery Charge Resistor
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 #define LL_PWR_BATT_CHARG_RESISTOR_5K     0x00000000U   /*!< Charge the Battery through a 5 kO resistor    */
@@ -266,21 +264,23 @@ extern "C" {
   */
 
 /** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 #define LL_PWR_WAKEUP_PIN1    PWR_WKUPEPR_WKUPEN1  /*!< Wake-Up pin 1 : PA0  */
 #define LL_PWR_WAKEUP_PIN2    PWR_WKUPEPR_WKUPEN2  /*!< Wake-Up pin 2 : PA2  */
+#if defined (PWR_WKUPEPR_WKUPEN3)
 #define LL_PWR_WAKEUP_PIN3    PWR_WKUPEPR_WKUPEN3  /*!< Wake-Up pin 3 : PI8  */
+#endif /* defined (PWR_WKUPEPR_WKUPEN3) */
 #define LL_PWR_WAKEUP_PIN4    PWR_WKUPEPR_WKUPEN4  /*!< Wake-Up pin 4 : PC13 */
+#if defined (PWR_WKUPEPR_WKUPEN5)
 #define LL_PWR_WAKEUP_PIN5    PWR_WKUPEPR_WKUPEN5  /*!< Wake-Up pin 5 : PI11 */
+#endif /* defined (PWR_WKUPEPR_WKUPEN5) */
 #define LL_PWR_WAKEUP_PIN6    PWR_WKUPEPR_WKUPEN6  /*!< Wake-Up pin 6 : PC1  */
 /**
   * @}
   */
 
 /** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL  Wakeup Pins pull configuration
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 #define LL_PWR_WAKEUP_PIN_NOPULL      0x00000000UL   /*!< Configure Wake-Up pin in no pull   */
@@ -291,16 +291,15 @@ extern "C" {
   */
 
 /** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
-#define LL_PWR_LDO_SUPPLY                     PWR_CR3_LDOEN                                                               /*!< Core domains are suppplied from the LDO                                                                     */
-#if defined (SMPS)                                                                                                                                                                                                                       
-#define LL_PWR_DIRECT_SMPS_SUPPLY             PWR_CR3_SMPSEN                                                              /*!< Core domains are suppplied from the SMPS                                                                    */
+#define LL_PWR_LDO_SUPPLY                     PWR_CR3_LDOEN                                                               /*!< Core domains are supplied from the LDO                                                                     */
+#if defined (SMPS)
+#define LL_PWR_DIRECT_SMPS_SUPPLY             PWR_CR3_SMPSEN                                                              /*!< Core domains are supplied from the SMPS                                                                    */
 #define LL_PWR_SMPS_1V8_SUPPLIES_LDO          (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)                      /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains                                       */
 #define LL_PWR_SMPS_2V5_SUPPLIES_LDO          (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)                      /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains                                       */
-#define LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO  (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
-#define LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO  (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
+#define LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO  (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */
+#define LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO  (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */
 #define LL_PWR_SMPS_1V8_SUPPLIES_EXT          (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains                            */
 #define LL_PWR_SMPS_2V5_SUPPLIES_EXT          (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains                            */
 #endif /* SMPS */
@@ -314,12 +313,10 @@ extern "C" {
   */
 /* Exported macro ------------------------------------------------------------*/
 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 
 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 
@@ -346,12 +343,10 @@ extern "C" {
   */
 /* Exported functions --------------------------------------------------------*/
 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 
 /** @defgroup PWR_LL_EF_Configuration Configuration
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 
@@ -541,7 +536,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogBooster(void)
 
 #if defined (PWR_CR1_AVD_READY)
 /**
-  * @brief  Enable the Analog Voltage Ready to isolate the BOOST IP untill VDDA will be ready
+  * @brief  Enable the Analog Voltage Ready to isolate the BOOST IP until VDDA will be ready
   * @rmtoll CR1    AVD_READY  LL_PWR_EnableAnalogVoltageReady
   * @retval None
   */
@@ -1361,7 +1356,7 @@ __STATIC_INLINE void LL_PWR_CPU2_SetD3PowerMode(uint32_t PDMode)
 }
 #endif /* DUAL_CORE */
 
-#if defined (PWR_CPUCR_PDDS_D3)
+#if defined (PWR_CPUCR_PDDS_D2)
 /**
   * @brief  Get the D3 Domain Power Down mode when the CPU enters deepsleep
   * @rmtoll CPUCR     PDDS_D3       LL_PWR_CPU_GetD3PowerMode
@@ -1385,7 +1380,7 @@ __STATIC_INLINE uint32_t LL_PWR_CPU_GetSRDPowerMode(void)
 {
   return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_SRD));
 }
-#endif /* PWR_CPUCR_PDDS_D3 */
+#endif /* PWR_CPUCR_PDDS_D2 */
 
 #if defined (DUAL_CORE)
 /**
@@ -1573,7 +1568,7 @@ __STATIC_INLINE uint32_t LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode(void)
   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
-  * @note   For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, VOS0 
+  * @note   For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, VOS0
   *         is applied when PWR_D3CR_VOS[1:0] = 0b11 and  SYSCFG_PWRCR_ODEN = 0b1.
   * @retval None
   */
@@ -1589,7 +1584,7 @@ __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
 /**
   * @brief  Get the main internal Regulator output voltage
   * @rmtoll D3CR    VOS       LL_PWR_GetRegulVoltageScaling
-  * @note   For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, checking 
+  * @note   For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, checking
   *         VOS0 need the check of PWR_D3CR_VOS[1:0] field and SYSCFG_PWRCR_ODEN bit.
   * @retval Returned value can be one of the following values:
   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
@@ -1617,10 +1612,13 @@ __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
   * @param  WakeUpPin This parameter can be one of the following values:
   *         @arg @ref LL_PWR_WAKEUP_PIN1
   *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
   *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
   *         @arg @ref LL_PWR_WAKEUP_PIN6
+  *
+  *         (*) value not defined in all devices.
+  *
   * @retval None
   */
 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
@@ -1639,10 +1637,13 @@ __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
   * @param  WakeUpPin This parameter can be one of the following values:
   *         @arg @ref LL_PWR_WAKEUP_PIN1
   *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
   *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
   *         @arg @ref LL_PWR_WAKEUP_PIN6
+  *
+  *         (*) value not defined in all devices.
+  *
   * @retval None
   */
 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
@@ -1661,10 +1662,13 @@ __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
   * @param  WakeUpPin This parameter can be one of the following values:
   *         @arg @ref LL_PWR_WAKEUP_PIN1
   *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
   *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
   *         @arg @ref LL_PWR_WAKEUP_PIN6
+  *
+  *         (*) value not defined in all devices.
+  *
   * @retval State of bit (1 or 0).
   */
 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
@@ -1683,10 +1687,13 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
   * @param  WakeUpPin This parameter can be one of the following values:
   *         @arg @ref LL_PWR_WAKEUP_PIN1
   *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
   *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
   *         @arg @ref LL_PWR_WAKEUP_PIN6
+  *
+  *         (*) value not defined in all devices.
+  *
   * @retval None
   */
 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
@@ -1705,10 +1712,13 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
   * @param  WakeUpPin This parameter can be one of the following values:
   *         @arg @ref LL_PWR_WAKEUP_PIN1
   *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
   *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
   *         @arg @ref LL_PWR_WAKEUP_PIN6
+  *
+  *         (*) value not defined in all devices.
+  *
   * @retval None
   */
 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
@@ -1727,10 +1737,13 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
   * @param  WakeUpPin This parameter can be one of the following values:
   *         @arg @ref LL_PWR_WAKEUP_PIN1
   *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
   *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
   *         @arg @ref LL_PWR_WAKEUP_PIN6
+  *
+  *         (*) value not defined in all devices.
+  *
   * @retval State of bit (1 or 0).
   */
 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
@@ -1749,10 +1762,13 @@ __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
   * @param  WakeUpPin This parameter can be one of the following values:
   *         @arg @ref LL_PWR_WAKEUP_PIN1
   *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
   *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
   *         @arg @ref LL_PWR_WAKEUP_PIN6
+  *
+  *         (*) value not defined in all devices.
+  *
   * @retval None
   */
 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)
@@ -1773,10 +1789,13 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)
   * @param  WakeUpPin This parameter can be one of the following values:
   *         @arg @ref LL_PWR_WAKEUP_PIN1
   *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
   *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
   *         @arg @ref LL_PWR_WAKEUP_PIN6
+  *
+  *         (*) value not defined in all devices.
+  *
   * @retval None
   */
 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)
@@ -1797,10 +1816,13 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)
   * @param  WakeUpPin This parameter can be one of the following values:
   *         @arg @ref LL_PWR_WAKEUP_PIN1
   *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
   *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
   *         @arg @ref LL_PWR_WAKEUP_PIN6
+  *
+  *         (*) value not defined in all devices.
+  *
   * @retval None
   */
 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)
@@ -1821,10 +1843,13 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)
   * @param  WakeUpPin This parameter can be one of the following values:
   *         @arg @ref LL_PWR_WAKEUP_PIN1
   *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
   *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
   *         @arg @ref LL_PWR_WAKEUP_PIN6
+  *
+  *         (*) value not defined in all devices.
+  *
   * @retval Returned value can be one of the following values:
   *         @arg @ref LL_PWR_WAKEUP_PIN_NOPULL
   *         @arg @ref LL_PWR_WAKEUP_PIN_PULLUP
@@ -1832,7 +1857,7 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)
   */
 __STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)
 {
-  register uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
+  uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
 
   return (uint32_t)(regValue >> ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK));
 }
@@ -1842,7 +1867,6 @@ __STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)
   */
 
 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 
@@ -2100,6 +2124,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
   return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF6) == (PWR_WKUPFR_WKUPF6)) ? 1UL : 0UL);
 }
 
+#if defined (PWR_WKUPFR_WKUPF5)
 /**
   * @brief  Get Wake-up Flag 5
   * @rmtoll WKUPFR          WKUPF5          LL_PWR_IsActiveFlag_WU5
@@ -2109,6 +2134,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
 {
   return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) == (PWR_WKUPFR_WKUPF5)) ? 1UL : 0UL);
 }
+#endif /* defined (PWR_WKUPFR_WKUPF5) */
 
 /**
   * @brief  Get Wake-up Flag 4
@@ -2120,6 +2146,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
   return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) == (PWR_WKUPFR_WKUPF4)) ? 1UL : 0UL);
 }
 
+#if defined (PWR_WKUPFR_WKUPF3)
 /**
   * @brief  Get Wake-up Flag 3
   * @rmtoll WKUPFR          WKUPF3          LL_PWR_IsActiveFlag_WU3
@@ -2129,6 +2156,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
 {
   return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) == (PWR_WKUPFR_WKUPF3)) ? 1UL : 0UL);
 }
+#endif /* defined (PWR_WKUPFR_WKUPF3) */
 
 /**
   * @brief  Get Wake-up Flag 2
@@ -2182,6 +2210,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
   WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC6);
 }
 
+#if defined (PWR_WKUPCR_WKUPC5)
 /**
   * @brief  Clear Wake-up Flag 5
   * @rmtoll WKUPCR          WKUPC5         LL_PWR_ClearFlag_WU5
@@ -2191,6 +2220,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
 {
   WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC5);
 }
+#endif /* defined (PWR_WKUPCR_WKUPC5) */
 
 /**
   * @brief  Clear Wake-up Flag 4
@@ -2202,6 +2232,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
   WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4);
 }
 
+#if defined (PWR_WKUPCR_WKUPC3)
 /**
   * @brief  Clear Wake-up Flag 3
   * @rmtoll WKUPCR          WKUPC3         LL_PWR_ClearFlag_WU3
@@ -2211,6 +2242,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
 {
   WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3);
 }
+#endif /* defined (PWR_WKUPCR_WKUPC3) */
 
 /**
   * @brief  Clear Wake-up Flag 2
@@ -2234,7 +2266,6 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
 
 #if defined (USE_FULL_LL_DRIVER)
 /** @defgroup PWR_LL_EF_Init De-initialization function
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 ErrorStatus LL_PWR_DeInit(void);
@@ -2268,4 +2299,3 @@ ErrorStatus LL_PWR_DeInit(void);
 
 #endif /* STM32H7xx_LL_PWR_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/