bsps/stm32h7: update STM32 H7 HAL

This patch updates STM32 H7 HAL source files. The files are taken from two
STM projects from their github.com repositories:

(i)
https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git

The project files are still available under BSD-3 license
and the version/commit used is:

d5fc8d05fc16fa2a2a2f948cf6c6ab39e78358e1

which represents post Release v1.11.1 development tree.

(ii)
https://github.com/STMicroelectronics/cmsis_device_h7.git

The project files were re-licensed from previous BSD-3 to Apache 2.0
license. Fortunately the project does not contain NOTICE file so no need
to do anything special when used in RTEMS.

The project version/commit imported is:

6d5ef249bec5177e0e2a0880ed62df2132874d99

which is code-wise Release v1.10.3 exactly.

1 files changed, 9 insertions, 28 deletions

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_cortex.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_cortex.h
index c6e0d04ad4..2b63e8f33d 100644
--- a/bsps/arm/stm32h7/include/stm32h7xx_ll_cortex.h
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_cortex.h
@@ -10,7 +10,7 @@
     [..]
     The LL CORTEX driver contains a set of generic APIs that can be
     used by user:
-      (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
+      (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
           functions
       (+) Low power mode configuration (SCB register of Cortex-MCU)
       (+) MPU API to configure and enable regions
@@ -21,13 +21,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -48,7 +47,6 @@ extern "C" {
   */
 
 /** @defgroup CORTEX_LL CORTEX
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 
@@ -62,12 +60,10 @@ extern "C" {
 /* Exported types ------------------------------------------------------------*/
 /* Exported constants --------------------------------------------------------*/
 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 
 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000UL                /*!< AHB clock divided by 8 selected as SysTick clock source.*/
@@ -77,7 +73,6 @@ extern "C" {
   */
 
 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 #define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */
@@ -90,7 +85,6 @@ extern "C" {
 #if __MPU_PRESENT
 
 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000UL                                      /*!< Disable NMI and privileged SW access */
@@ -102,7 +96,6 @@ extern "C" {
   */
 
 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 #define LL_MPU_REGION_NUMBER0              0x00UL /*!< REGION Number 0  */
@@ -128,7 +121,6 @@ extern "C" {
   */
 
 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 #define LL_MPU_REGION_SIZE_32B             (0x04UL << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
@@ -164,7 +156,6 @@ extern "C" {
   */
 
 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 #define LL_MPU_REGION_NO_ACCESS            (0x00UL << MPU_RASR_AP_Pos) /*!< No access*/
@@ -178,19 +169,19 @@ extern "C" {
   */
 
 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 #define LL_MPU_TEX_LEVEL0                  (0x00UL << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
 #define LL_MPU_TEX_LEVEL1                  (0x01UL << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
 #define LL_MPU_TEX_LEVEL2                  (0x02UL << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
+
+/* Legacy Define */
 #define LL_MPU_TEX_LEVEL4                  (0x04UL << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
 /**
   * @}
   */
 
 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00UL            /*!< Instruction fetches enabled */
@@ -200,7 +191,6 @@ extern "C" {
   */
 
 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 #define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
@@ -210,7 +200,6 @@ extern "C" {
   */
 
 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 #define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
@@ -220,7 +209,6 @@ extern "C" {
   */
 
 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 #define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
@@ -237,12 +225,10 @@ extern "C" {
 
 /* Exported functions --------------------------------------------------------*/
 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 
 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 
@@ -317,7 +303,6 @@ __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
   */
 
 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 
@@ -396,7 +381,6 @@ __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
   */
 
 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 
@@ -435,7 +419,6 @@ __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
   */
 
 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 
@@ -495,7 +478,6 @@ __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
 
 #if __MPU_PRESENT
 /** @defgroup CORTEX_LL_EF_MPU MPU
-  * @ingroup RTEMSBSPsARMSTM32H7
   * @{
   */
 
@@ -612,7 +594,7 @@ __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
   *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
   *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
   *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
-  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
+  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2
   *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
   *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
   *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
@@ -685,4 +667,3 @@ __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
 
 #endif /* STM32H7xx_LL_CORTEX_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/