diff options
author | Karel Gardas <karel@functional.vision> | 2023-07-19 18:04:28 +0200 |
---|---|---|
committer | Karel Gardas <karel@functional.vision> | 2023-07-31 15:15:09 +0200 |
commit | f728eb4dc4e19fce942f4762882f9a2aa06087b9 (patch) | |
tree | d3d85d6d98c286580ffc2795543ffc2848eeff41 /bsps/arm/stm32h7/include/stm32h7xx_hal_spi.h | |
parent | bsps/arm: fix nested extern decl. warnings brought by CMSIS files update (diff) | |
download | rtems-f728eb4dc4e19fce942f4762882f9a2aa06087b9.tar.bz2 |
bsps/stm32h7: update STM32 H7 HAL
This patch updates STM32 H7 HAL source files. The files are taken from two
STM projects from their github.com repositories:
(i)
https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git
The project files are still available under BSD-3 license
and the version/commit used is:
d5fc8d05fc16fa2a2a2f948cf6c6ab39e78358e1
which represents post Release v1.11.1 development tree.
(ii)
https://github.com/STMicroelectronics/cmsis_device_h7.git
The project files were re-licensed from previous BSD-3 to Apache 2.0
license. Fortunately the project does not contain NOTICE file so no need
to do anything special when used in RTEMS.
The project version/commit imported is:
6d5ef249bec5177e0e2a0880ed62df2132874d99
which is code-wise Release v1.10.3 exactly.
Diffstat (limited to 'bsps/arm/stm32h7/include/stm32h7xx_hal_spi.h')
-rw-r--r-- | bsps/arm/stm32h7/include/stm32h7xx_hal_spi.h | 234 |
1 files changed, 119 insertions, 115 deletions
diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_spi.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_spi.h index d43b0ada99..77578d191c 100644 --- a/bsps/arm/stm32h7/include/stm32h7xx_hal_spi.h +++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_spi.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - * <h2><center>© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.</center></h2> + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -38,7 +37,6 @@ extern "C" { /* Exported types ------------------------------------------------------------*/ /** @defgroup SPI_Exported_Types SPI Exported Types - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -64,7 +62,8 @@ typedef struct uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_Management */ + This parameter can be a value of + @ref SPI_Slave_Select_Management */ uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be used to configure the transmit and receive SCK clock. @@ -82,40 +81,45 @@ typedef struct This parameter can be a value of @ref SPI_CRC_Calculation */ uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. - This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */ + This parameter must be an odd number between + Min_Data = 0 and Max_Data = 65535 */ uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. This parameter can be a value of @ref SPI_CRC_length */ uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . This parameter can be a value of @ref SPI_NSSP_Mode - This mode is activated by the SSOM bit in the SPIx_CR2 register and - it takes effect only if the SPI interface is configured as Motorola SPI - master (FRF=0). */ + This mode is activated by the SSOM bit in the SPIx_CR2 register + and it takes effect only if the SPI interface is configured + as Motorola SPI master (FRF=0). */ - uint32_t NSSPolarity; /*!< Specifies which level of SS input/output external signal (present on SS pin) is - considered as active one. + uint32_t NSSPolarity; /*!< Specifies which level of SS input/output external signal + (present on SS pin) is considered as active one. This parameter can be a value of @ref SPI_NSS_Polarity */ uint32_t FifoThreshold; /*!< Specifies the FIFO threshold level. This parameter can be a value of @ref SPI_Fifo_Threshold */ - uint32_t TxCRCInitializationPattern; /*!< Specifies the transmitter CRC initialization Pattern used for the CRC calculation. - This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */ + uint32_t TxCRCInitializationPattern; /*!< Specifies the transmitter CRC initialization Pattern used for + the CRC calculation. This parameter can be a value of + @ref SPI_CRC_Calculation_Initialization_Pattern */ - uint32_t RxCRCInitializationPattern; /*!< Specifies the receiver CRC initialization Pattern used for the CRC calculation. - This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */ + uint32_t RxCRCInitializationPattern; /*!< Specifies the receiver CRC initialization Pattern used for + the CRC calculation. This parameter can be a value of + @ref SPI_CRC_Calculation_Initialization_Pattern */ - uint32_t MasterSSIdleness; /*!< Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted - additionally between active edge of SS and first data transaction start in master mode. + uint32_t MasterSSIdleness; /*!< Specifies an extra delay, expressed in number of SPI clock cycle + periods, inserted additionally between active edge of SS + and first data transaction start in master mode. This parameter can be a value of @ref SPI_Master_SS_Idleness */ - uint32_t MasterInterDataIdleness; /*!< Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between - two consecutive data frames in master mode - This parameter can be a value of @ref SPI_Master_InterData_Idleness */ + uint32_t MasterInterDataIdleness; /*!< Specifies minimum time delay (expressed in SPI clock cycles periods) + inserted between two consecutive data frames in master mode. + This parameter can be a value of + @ref SPI_Master_InterData_Idleness */ - uint32_t MasterReceiverAutoSusp; /*!< Control continuous SPI transfer in master receiver mode and automatic management - in order to avoid overrun condition. + uint32_t MasterReceiverAutoSusp; /*!< Control continuous SPI transfer in master receiver mode + and automatic management in order to avoid overrun condition. This parameter can be a value of @ref SPI_Master_RX_AutoSuspend*/ uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state @@ -123,7 +127,6 @@ typedef struct uint32_t IOSwap; /*!< Invert MISO/MOSI alternate functions This parameter can be a value of @ref SPI_IO_Swap */ - } SPI_InitTypeDef; /** @@ -147,7 +150,7 @@ typedef enum */ typedef struct { - uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ uint16_t TxXferSize; /*!< SPI Tx Transfer size to reload */ @@ -158,7 +161,7 @@ typedef struct uint32_t Requested; /*!< SPI reload request */ } SPI_ReloadTypeDef; -#endif /* USE_HSPI_RELOAD_TRANSFER */ +#endif /* USE_SPI_RELOAD_TRANSFER */ /** * @brief SPI handle Structure definition @@ -169,7 +172,7 @@ typedef struct __SPI_HandleTypeDef SPI_InitTypeDef Init; /*!< SPI communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ uint16_t TxXferSize; /*!< SPI Tx Transfer size */ @@ -196,12 +199,12 @@ typedef struct __SPI_HandleTypeDef __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ __IO uint32_t ErrorCode; /*!< SPI Error code */ - + #if defined(USE_SPI_RELOAD_TRANSFER) SPI_ReloadTypeDef Reload; /*!< SPI reload parameters */ - -#endif /* USE_HSPI_RELOAD_TRANSFER */ + +#endif /* USE_SPI_RELOAD_TRANSFER */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ @@ -212,6 +215,7 @@ typedef struct __SPI_HandleTypeDef void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ + void (* SuspendCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Suspend callback */ void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ @@ -232,8 +236,9 @@ typedef enum HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, /*!< SPI TxRx Half Completed callback ID */ HAL_SPI_ERROR_CB_ID = 0x06UL, /*!< SPI Error callback ID */ HAL_SPI_ABORT_CB_ID = 0x07UL, /*!< SPI Abort callback ID */ - HAL_SPI_MSPINIT_CB_ID = 0x08UL, /*!< SPI Msp Init callback ID */ - HAL_SPI_MSPDEINIT_CB_ID = 0x09UL /*!< SPI Msp DeInit callback ID */ + HAL_SPI_SUSPEND_CB_ID = 0x08UL, /*!< SPI Suspend callback ID */ + HAL_SPI_MSPINIT_CB_ID = 0x09UL, /*!< SPI Msp Init callback ID */ + HAL_SPI_MSPDEINIT_CB_ID = 0x0AUL /*!< SPI Msp DeInit callback ID */ } HAL_SPI_CallbackIDTypeDef; @@ -250,12 +255,10 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to /* Exported constants --------------------------------------------------------*/ /** @defgroup SPI_Exported_Constants SPI Exported Constants - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ /** @defgroup SPI_FIFO_Type SPI FIFO Type - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define SPI_LOWEND_FIFO_SIZE 8UL @@ -265,7 +268,6 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ /** @defgroup SPI_Error_Code SPI Error Codes - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define HAL_SPI_ERROR_NONE (0x00000000UL) /*!< No error */ @@ -274,21 +276,21 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to #define HAL_SPI_ERROR_OVR (0x00000004UL) /*!< OVR error */ #define HAL_SPI_ERROR_FRE (0x00000008UL) /*!< FRE error */ #define HAL_SPI_ERROR_DMA (0x00000010UL) /*!< DMA transfer error */ -#define HAL_SPI_ERROR_FLAG (0x00000020UL) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */ +#define HAL_SPI_ERROR_FLAG (0x00000020UL) /*!< Error on RXP/TXP/DXP/FTLVL/FRLVL Flag */ #define HAL_SPI_ERROR_ABORT (0x00000040UL) /*!< Error during SPI Abort procedure */ #define HAL_SPI_ERROR_UDR (0x00000080UL) /*!< Underrun error */ #define HAL_SPI_ERROR_TIMEOUT (0x00000100UL) /*!< Timeout error */ -#define HAL_SPI_ERROR_UNKNOW (0x00000200UL) /*!< Unknow error */ +#define HAL_SPI_ERROR_UNKNOW (0x00000200UL) /*!< Unknown error */ #define HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400UL) /*!< Requested operation not supported */ +#define HAL_SPI_ERROR_RELOAD (0x00000800UL) /*!< Reload error */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) -#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000800UL) /*!< Invalid Callback error */ +#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00001000UL) /*!< Invalid Callback error */ #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup SPI_Mode SPI Mode - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define SPI_MODE_SLAVE (0x00000000UL) @@ -298,7 +300,6 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ /** @defgroup SPI_Direction SPI Direction Mode - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define SPI_DIRECTION_2LINES (0x00000000UL) @@ -310,7 +311,6 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ /** @defgroup SPI_Data_Size SPI Data Size - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define SPI_DATASIZE_4BIT (0x00000003UL) @@ -347,7 +347,6 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ /** @defgroup SPI_Clock_Polarity SPI Clock Polarity - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define SPI_POLARITY_LOW (0x00000000UL) @@ -357,7 +356,6 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ /** @defgroup SPI_Clock_Phase SPI Clock Phase - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define SPI_PHASE_1EDGE (0x00000000UL) @@ -367,7 +365,6 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ /** @defgroup SPI_Slave_Select_Management SPI Slave Select Management - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define SPI_NSS_SOFT SPI_CFG2_SSM @@ -378,7 +375,6 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define SPI_NSS_PULSE_DISABLE (0x00000000UL) @@ -388,7 +384,6 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define SPI_BAUDRATEPRESCALER_2 (0x00000000UL) @@ -404,7 +399,6 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ /** @defgroup SPI_MSB_LSB_Transmission SPI MSB LSB Transmission - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define SPI_FIRSTBIT_MSB (0x00000000UL) @@ -414,7 +408,6 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ /** @defgroup SPI_TI_Mode SPI TI Mode - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define SPI_TIMODE_DISABLE (0x00000000UL) @@ -424,7 +417,6 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ /** @defgroup SPI_CRC_Calculation SPI CRC Calculation - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define SPI_CRCCALCULATION_DISABLE (0x00000000UL) @@ -434,7 +426,6 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ /** @defgroup SPI_CRC_length SPI CRC Length - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define SPI_CRC_LENGTH_DATASIZE (0x00000000UL) @@ -472,7 +463,6 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ /** @defgroup SPI_Fifo_Threshold SPI Fifo Threshold - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define SPI_FIFO_THRESHOLD_01DATA (0x00000000UL) @@ -496,7 +486,6 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ /** @defgroup SPI_CRC_Calculation_Initialization_Pattern SPI CRC Calculation Initialization Pattern - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN (0x00000000UL) @@ -506,7 +495,6 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ /** @defgroup SPI_NSS_Polarity SPI NSS Polarity - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define SPI_NSS_POLARITY_LOW (0x00000000UL) @@ -516,7 +504,6 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ /** @defgroup SPI_Master_Keep_IO_State Keep IO State - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define SPI_MASTER_KEEP_IO_STATE_DISABLE (0x00000000UL) @@ -526,7 +513,6 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ /** @defgroup SPI_IO_Swap Control SPI IO Swap - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define SPI_IO_SWAP_DISABLE (0x00000000UL) @@ -536,7 +522,6 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ /** @defgroup SPI_Master_SS_Idleness SPI Master SS Idleness - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define SPI_MASTER_SS_IDLENESS_00CYCLE (0x00000000UL) @@ -560,7 +545,6 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ /** @defgroup SPI_Master_InterData_Idleness SPI Master Inter-Data Idleness - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE (0x00000000UL) @@ -584,7 +568,6 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ /** @defgroup SPI_Master_RX_AutoSuspend SPI Master Receiver AutoSuspend - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define SPI_MASTER_RX_AUTOSUSP_DISABLE (0x00000000UL) @@ -593,30 +576,27 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @} */ -/** @defgroup SPI_Underrun_Detection SPI Underrun Detection - * @ingroup RTEMSBSPsARMSTM32H7 +/** @defgroup SPI_Underrun_Behaviour SPI Underrun Behavior * @{ */ -#define SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME (0x00000000UL) -#define SPI_UNDERRUN_DETECT_END_DATA_FRAME SPI_CFG1_UDRDET_0 -#define SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS SPI_CFG1_UDRDET_1 +#define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000UL) +#define SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG_0 +#define SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED SPI_CFG1_UDRCFG_1 /** * @} */ -/** @defgroup SPI_Underrun_Behaviour SPI Underrun Behavior - * @ingroup RTEMSBSPsARMSTM32H7 +/** @defgroup SPI_Underrun_Detection SPI Underrun Detection * @{ */ -#define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000UL) -#define SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG_0 -#define SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED SPI_CFG1_UDRCFG_1 +#define SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME (0x00000000UL) +#define SPI_UNDERRUN_DETECT_END_DATA_FRAME SPI_CFG1_UDRDET_0 +#define SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS SPI_CFG1_UDRDET_1 /** * @} */ /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define SPI_IT_RXP SPI_IER_RXPIE @@ -636,7 +616,6 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ /** @defgroup SPI_Flags_definition SPI Flags Definition - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ #define SPI_FLAG_RXP SPI_SR_RXP /* SPI status flag : Rx-Packet available flag */ @@ -659,13 +638,12 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ -#define SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */ -#define SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0) -#define SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1) -#define SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0) +#define SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */ +#define SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0) +#define SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1) +#define SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0) /** * @} */ @@ -676,7 +654,6 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to /* Exported macros -----------------------------------------------------------*/ /** @defgroup SPI_Exported_Macros SPI Exported Macros - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ @@ -693,7 +670,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to } while(0) #else #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) -#endif +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ /** @brief Enable the specified SPI interrupts. * @param __HANDLE__: specifies the SPI Handle. @@ -756,7 +733,8 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @arg SPI_IT_ERR : Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & \ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SPI flag is set or not. * @param __HANDLE__: specifies the SPI Handle. @@ -872,7 +850,8 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) -HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ /** @@ -883,23 +862,26 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @{ */ /* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); #if defined(USE_SPI_RELOAD_TRANSFER) -HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -#endif /* USE_HSPI_RELOAD_TRANSFER */ +HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, + uint8_t *pRxData, uint16_t Size); +#endif /* USE_SPI_RELOAD_TRANSFER */ HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); @@ -918,6 +900,7 @@ void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi); /** * @} */ @@ -927,8 +910,8 @@ void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); */ /* Peripheral State and Error functions ***************************************/ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); /** * @} */ @@ -939,23 +922,43 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); /* Private macros ------------------------------------------------------------*/ /** @defgroup SPI_Private_Macros SPI Private Macros - * @ingroup RTEMSBSPsARMSTM32H7 * @{ */ -/** @brief Set the SPI transmit-only mode. +/** @brief Set the SPI transmit-only mode in 1Line configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR) + +/** @brief Set the SPI receive-only mode in 1Line configuration. * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_HDDIR) +#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR) -/** @brief Set the SPI receive-only mode. +/** @brief Set the SPI transmit-only mode in 2Lines configuration. * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 ,SPI_CR1_HDDIR) +#define SPI_2LINES_TX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_0) + +/** @brief Set the SPI receive-only mode in 2Lines configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_2LINES_RX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_1) + +/** @brief Set the SPI Transmit-Receive mode in 2Lines configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_2LINES(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, 0x00000000UL) #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ ((MODE) == SPI_MODE_MASTER)) @@ -967,15 +970,13 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) -#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) ( \ - ((MODE) == SPI_DIRECTION_2LINES)|| \ - ((MODE) == SPI_DIRECTION_1LINE) || \ - ((MODE) == SPI_DIRECTION_2LINES_TXONLY)) +#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ + ((MODE) == SPI_DIRECTION_1LINE) || \ + ((MODE) == SPI_DIRECTION_2LINES_TXONLY)) -#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) ( \ - ((MODE) == SPI_DIRECTION_2LINES)|| \ - ((MODE) == SPI_DIRECTION_1LINE) || \ - ((MODE) == SPI_DIRECTION_2LINES_RXONLY)) +#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ + ((MODE) == SPI_DIRECTION_1LINE) || \ + ((MODE) == SPI_DIRECTION_2LINES_RXONLY)) #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_32BIT) || \ ((DATASIZE) == SPI_DATASIZE_31BIT) || \ @@ -1038,13 +1039,13 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \ ((NSSP) == SPI_NSS_PULSE_DISABLE)) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ @@ -1090,7 +1091,8 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); ((LENGTH) == SPI_CRC_LENGTH_5BIT) || \ ((LENGTH) == SPI_CRC_LENGTH_4BIT)) -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1UL) +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) > 0x0UL) + #define IS_SPI_UNDERRUN_DETECTION(MODE) (((MODE) == SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME) || \ ((MODE) == SPI_UNDERRUN_DETECT_END_DATA_FRAME) || \ @@ -1099,6 +1101,9 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); #define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \ ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED) || \ ((MODE) == SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED)) + +#define IS_SPI_MASTER_RX_AUTOSUSP(MODE) (((MODE) == SPI_MASTER_RX_AUTOSUSP_DISABLE) || \ + ((MODE) == SPI_MASTER_RX_AUTOSUSP_ENABLE)) /** * @} */ @@ -1120,4 +1125,3 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |