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authorSebastian Huber <sebastian.huber@embedded-brains.de>2018-04-24 07:49:12 +0200
committerSebastian Huber <sebastian.huber@embedded-brains.de>2018-04-24 10:24:29 +0200
commitaa705fe3473d64208d796d7ac7404a255ac4078a (patch)
tree92e0a5497c5b93744475d18b45658afa4308c4cf /bsps/arm/shared
parentbsps: Move arm-a9mpcore-smp.c to bsps (diff)
downloadrtems-aa705fe3473d64208d796d7ac7404a255ac4078a.tar.bz2
bsps: Move arm-cp15-set-exception-handler.c to bsps
This patch is a part of the BSP source reorganization. Update #3285.
Diffstat (limited to 'bsps/arm/shared')
-rw-r--r--bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c56
1 files changed, 56 insertions, 0 deletions
diff --git a/bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c b/bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c
new file mode 100644
index 0000000000..b24b7c4eb0
--- /dev/null
+++ b/bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2013 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Dornierstr. 4
+ * 82178 Puchheim
+ * Germany
+ * <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <libcpu/arm-cp15.h>
+
+#include <bsp/linker-symbols.h>
+
+void arm_cp15_set_exception_handler(
+ Arm_symbolic_exception_name exception,
+ void (*handler)(void)
+)
+{
+ if ((unsigned) exception < MAX_EXCEPTIONS) {
+ uint32_t *cpu_table = (uint32_t *) 0 + MAX_EXCEPTIONS;
+ uint32_t *mirror_table = (uint32_t *) bsp_vector_table_begin + MAX_EXCEPTIONS;
+ uint32_t current_handler = mirror_table[exception];
+
+ if (current_handler != (uint32_t) handler) {
+ size_t table_size = MAX_EXCEPTIONS * sizeof(uint32_t);
+ uint32_t cls = arm_cp15_get_min_cache_line_size();
+ uint32_t ctrl;
+ rtems_interrupt_level level;
+
+ rtems_interrupt_local_disable(level);
+
+ ctrl = arm_cp15_mmu_disable(cls);
+
+ mirror_table[exception] = (uint32_t) handler;
+
+ rtems_cache_flush_multiple_data_lines(mirror_table, table_size);
+
+ /*
+ * On ARMv7 processors with the Security Extension the mirror table might
+ * be the actual table used by the processor.
+ */
+ rtems_cache_invalidate_multiple_instruction_lines(mirror_table, table_size);
+
+ rtems_cache_invalidate_multiple_instruction_lines(cpu_table, table_size);
+
+ arm_cp15_set_control(ctrl);
+
+ rtems_interrupt_local_enable(level);
+ }
+ }
+}