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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2019-01-08 09:50:50 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2019-01-09 10:36:02 +0100 |
| commit | b9ffc41c9678fb3c5386c1a6ab394656ec85dbc6 (patch) | |
| tree | 135cb3a1136be3695caff41a931ebe997a8337c8 /bsps/arm/shared/cache/cache-v7ar-disable-data.S | |
| parent | Adjust interrupt mode tests for some CPU ports (diff) | |
| download | rtems-b9ffc41c9678fb3c5386c1a6ab394656ec85dbc6.tar.bz2 | |
riscv: Enable robust thread dispatch
It must be enabled, since the context switch code does not save/restore
the interrupt status.
Update #3433.
Diffstat (limited to 'bsps/arm/shared/cache/cache-v7ar-disable-data.S')
0 files changed, 0 insertions, 0 deletions