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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-12-21 10:16:02 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-12-21 10:32:25 +0100 |
| commit | ba856559a4120a7f454aad30445508f0acc2a040 (patch) | |
| tree | 91cac6d25aa4bd733035b322196f00991011ce58 /bsps/arm/shared/cache/cache-l2c-310.c | |
| parent | bsps/i386: Enable instruction cache support (diff) | |
| download | rtems-ba856559a4120a7f454aad30445508f0acc2a040.tar.bz2 | |
ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
Remove this superfluous define.
Update #3667.
Diffstat (limited to '')
| -rw-r--r-- | bsps/arm/shared/cache/cache-l2c-310.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/bsps/arm/shared/cache/cache-l2c-310.c b/bsps/arm/shared/cache/cache-l2c-310.c index 6869d205a8..e447aa0a63 100644 --- a/bsps/arm/shared/cache/cache-l2c-310.c +++ b/bsps/arm/shared/cache/cache-l2c-310.c @@ -68,8 +68,7 @@ /* Some/many ARM Cortex-A cores have L1 data line length 64 bytes */ #define CPU_MAXIMAL_CACHE_ALIGNMENT 64 #endif -#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS \ - ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS +#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS #define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS #define L2C_310_DATA_LINE_MASK ( CPU_DATA_CACHE_ALIGNMENT - 1 ) |