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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-12-21 10:16:02 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-12-21 10:32:25 +0100 |
| commit | ba856559a4120a7f454aad30445508f0acc2a040 (patch) | |
| tree | 91cac6d25aa4bd733035b322196f00991011ce58 /bsps/arm/shared/cache/cache-cp15.h | |
| parent | bsps/i386: Enable instruction cache support (diff) | |
| download | rtems-ba856559a4120a7f454aad30445508f0acc2a040.tar.bz2 | |
ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
Remove this superfluous define.
Update #3667.
Diffstat (limited to '')
| -rw-r--r-- | bsps/arm/shared/cache/cache-cp15.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/bsps/arm/shared/cache/cache-cp15.h b/bsps/arm/shared/cache/cache-cp15.h index ff01384f4b..1470c52e56 100644 --- a/bsps/arm/shared/cache/cache-cp15.h +++ b/bsps/arm/shared/cache/cache-cp15.h @@ -33,7 +33,6 @@ extern "C" { /* These two defines also ensure that the rtems_cache_* functions have bodies */ #define ARM_CACHE_L1_CPU_DATA_ALIGNMENT 32 #define ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT 32 -#define ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS #define ARM_CACHE_L1_CSS_ID_DATA \ (ARM_CP15_CACHE_CSS_ID_DATA | ARM_CP15_CACHE_CSS_LEVEL(0)) |