bsps: Move startup files to bsps

Adjust build support files to new directory layout.

This patch is a part of the BSP source reorganization.

Update #3285.

9 files changed, 624 insertions, 0 deletions

diff --git a/bsps/arm/lpc32xx/start/bsp_specs b/bsps/arm/lpc32xx/start/bsp_specs
new file mode 100644
index 0000000000..47dd31d46b
--- /dev/null
+++ b/bsps/arm/lpc32xx/start/bsp_specs
@@ -0,0 +1,9 @@
+%rename endfile old_endfile
+%rename startfile old_startfile
+
+*startfile:
+%{!qrtems: %(old_startfile)} \
+%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}}
+
+*endfile:
+%{!qrtems: %(old_endfiles)} %{qrtems: crtend.o%s crtn.o%s}
diff --git a/bsps/arm/lpc32xx/start/bspreset.c b/bsps/arm/lpc32xx/start/bspreset.c
new file mode 100644
index 0000000000..e3c4cfbbd2
--- /dev/null
+++ b/bsps/arm/lpc32xx/start/bspreset.c
@@ -0,0 +1,48 @@
+/**
+ * @file
+ *
+ * @ingroup arm_lpc32xx
+ *
+ * @brief Reset code.
+ */
+
+/*
+ * Copyright (c) 2009-2010 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <stdbool.h>
+
+#include <bspopts.h>
+#include <bsp/bootcard.h>
+#include <bsp/lpc32xx.h>
+
+static void watchdog_reset(void)
+{
+  #ifdef LPC32XX_ENABLE_WATCHDOG_RESET
+    LPC32XX_TIMCLK_CTRL |= TIMCLK_CTRL_WDT;
+    lpc32xx.wdt.mctrl |= WDTTIM_MCTRL_M_RES1 | WDTTIM_MCTRL_M_RES2;
+    lpc32xx.wdt.emr = WDTTIM_EMR_MATCH_CTRL_SET(lpc32xx.wdt.emr, 0x2);
+    lpc32xx.wdt.ctrl |= WDTTIM_CTRL_COUNT_ENAB;
+    lpc32xx.wdt.match0 = 1;
+    lpc32xx.wdt.counter = 0;
+  #endif
+}
+
+void bsp_reset( void)
+{
+  watchdog_reset();
+
+  while (true) {
+    /* Do nothing */
+  }
+}
diff --git a/bsps/arm/lpc32xx/start/bspstart.c b/bsps/arm/lpc32xx/start/bspstart.c
new file mode 100644
index 0000000000..7ade16bbb8
--- /dev/null
+++ b/bsps/arm/lpc32xx/start/bspstart.c
@@ -0,0 +1,38 @@
+/**
+ * @file
+ *
+ * @ingroup arm_lpc32xx
+ *
+ * @brief Startup code.
+ */
+
+/*
+ * Copyright (c) 2009-2014 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems/counter.h>
+
+#include <bsp.h>
+#include <bsp/bootcard.h>
+#include <bsp/irq-generic.h>
+
+CPU_Counter_ticks _CPU_Counter_read(void)
+{
+  return lpc32xx_timer();
+}
+
+void bsp_start(void)
+{
+  rtems_counter_initialize_converter(LPC32XX_PERIPH_CLK);
+  bsp_interrupt_initialize();
+}
diff --git a/bsps/arm/lpc32xx/start/bspstarthooks.c b/bsps/arm/lpc32xx/start/bspstarthooks.c
new file mode 100644
index 0000000000..1df21b4343
--- /dev/null
+++ b/bsps/arm/lpc32xx/start/bspstarthooks.c
@@ -0,0 +1,240 @@
+/**
+ * @file
+ *
+ * @ingroup arm_lpc32xx
+ *
+ * @brief Startup code.
+ */
+
+/*
+ * Copyright (c) 2009-2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#define ARM_CP15_TEXT_SECTION BSP_START_TEXT_SECTION
+
+#include <bsp.h>
+#include <bsp/start.h>
+#include <bsp/lpc32xx.h>
+#include <bsp/mmu.h>
+#include <bsp/arm-cp15-start.h>
+#include <bsp/linker-symbols.h>
+#include <bsp/uart-output-char.h>
+
+#ifdef LPC32XX_DISABLE_READ_WRITE_DATA_CACHE
+  #define LPC32XX_MMU_READ_WRITE_DATA LPC32XX_MMU_READ_WRITE
+#else
+  #define LPC32XX_MMU_READ_WRITE_DATA LPC32XX_MMU_READ_WRITE_CACHED
+#endif
+
+#ifdef LPC32XX_DISABLE_READ_ONLY_PROTECTION
+  #define LPC32XX_MMU_READ_ONLY_DATA LPC32XX_MMU_READ_WRITE_CACHED
+  #define LPC32XX_MMU_CODE LPC32XX_MMU_READ_WRITE_CACHED
+#else
+  #define LPC32XX_MMU_READ_ONLY_DATA LPC32XX_MMU_READ_ONLY_CACHED
+  #define LPC32XX_MMU_CODE LPC32XX_MMU_READ_ONLY_CACHED
+#endif
+
+#ifndef LPC32XX_DISABLE_MMU
+  static const BSP_START_DATA_SECTION arm_cp15_start_section_config
+    lpc32xx_mmu_config_table [] = {
+    {
+      .begin = (uint32_t) bsp_section_fast_text_begin,
+      .end = (uint32_t) bsp_section_fast_text_end,
+      .flags = LPC32XX_MMU_CODE
+    }, {
+      .begin = (uint32_t) bsp_section_fast_data_begin,
+      .end = (uint32_t) bsp_section_fast_data_end,
+      .flags = LPC32XX_MMU_READ_WRITE_DATA
+#ifdef LPC32XX_SCRATCH_AREA_SIZE
+    }, {
+      .begin = (uint32_t) &lpc32xx_scratch_area [0],
+      .end = (uint32_t) &lpc32xx_scratch_area [LPC32XX_SCRATCH_AREA_SIZE],
+      .flags = LPC32XX_MMU_READ_ONLY_DATA
+#endif
+    }, {
+      .begin = (uint32_t) bsp_section_start_begin,
+      .end = (uint32_t) bsp_section_start_end,
+      .flags = LPC32XX_MMU_CODE
+    }, {
+      .begin = (uint32_t) bsp_section_vector_begin,
+      .end = (uint32_t) bsp_section_vector_end,
+      .flags = LPC32XX_MMU_READ_WRITE_CACHED
+    }, {
+      .begin = (uint32_t) bsp_section_text_begin,
+      .end = (uint32_t) bsp_section_text_end,
+      .flags = LPC32XX_MMU_CODE
+    }, {
+      .begin = (uint32_t) bsp_section_rodata_begin,
+      .end = (uint32_t) bsp_section_rodata_end,
+      .flags = LPC32XX_MMU_READ_ONLY_DATA
+    }, {
+      .begin = (uint32_t) bsp_section_data_begin,
+      .end = (uint32_t) bsp_section_data_end,
+      .flags = LPC32XX_MMU_READ_WRITE_DATA
+    }, {
+      .begin = (uint32_t) bsp_section_bss_begin,
+      .end = (uint32_t) bsp_section_bss_end,
+      .flags = LPC32XX_MMU_READ_WRITE_DATA
+    }, {
+      .begin = (uint32_t) bsp_section_work_begin,
+      .end = (uint32_t) bsp_section_work_end,
+      .flags = LPC32XX_MMU_READ_WRITE_DATA
+    }, {
+      .begin = (uint32_t) bsp_section_stack_begin,
+      .end = (uint32_t) bsp_section_stack_end,
+      .flags = LPC32XX_MMU_READ_WRITE_DATA
+    }, {
+      .begin = 0x0U,
+      .end = 0x100000U,
+      .flags = LPC32XX_MMU_READ_ONLY_CACHED
+    }, {
+      .begin = 0x20000000U,
+      .end = 0x200c0000U,
+      .flags = LPC32XX_MMU_READ_WRITE
+    }, {
+      .begin = 0x30000000U,
+      .end = 0x32000000U,
+      .flags = LPC32XX_MMU_READ_WRITE
+    }, {
+      .begin = 0x40000000U,
+      .end = 0x40100000U,
+      .flags = LPC32XX_MMU_READ_WRITE
+    }, {
+      .begin = (uint32_t) lpc32xx_magic_zero_begin,
+      .end = (uint32_t) lpc32xx_magic_zero_end,
+      .flags = LPC32XX_MMU_READ_WRITE_DATA
+    }
+  };
+#endif
+
+static BSP_START_TEXT_SECTION void setup_mmu_and_cache(void)
+{
+  uint32_t ctrl = arm_cp15_start_setup_mmu_and_cache(
+    ARM_CP15_CTRL_I | ARM_CP15_CTRL_R | ARM_CP15_CTRL_C
+      | ARM_CP15_CTRL_V | ARM_CP15_CTRL_M,
+    ARM_CP15_CTRL_S | ARM_CP15_CTRL_A
+  );
+
+  arm_cp15_cache_invalidate();
+
+  #ifndef LPC32XX_DISABLE_MMU
+    arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache(
+      ctrl,
+      (uint32_t *) bsp_translation_table_base,
+      LPC32XX_MMU_CLIENT_DOMAIN,
+      &lpc32xx_mmu_config_table [0],
+      RTEMS_ARRAY_SIZE(lpc32xx_mmu_config_table)
+    );
+  #endif
+}
+
+BSP_START_TEXT_SECTION bool lpc32xx_start_pll_setup(
+  uint32_t hclkpll_ctrl,
+  uint32_t hclkdiv_ctrl,
+  bool force
+)
+{
+  uint32_t pwr_ctrl = LPC32XX_PWR_CTRL;
+  bool settings_ok =
+    ((LPC32XX_HCLKPLL_CTRL ^ hclkpll_ctrl) & BSP_MSK32(1, 16)) == 0
+      && ((LPC32XX_HCLKDIV_CTRL ^ hclkdiv_ctrl) & BSP_MSK32(0, 8)) == 0;
+
+  if ((pwr_ctrl & PWR_NORMAL_RUN_MODE) == 0 || (!settings_ok && force)) {
+    /* Disable HCLK PLL output */
+    LPC32XX_PWR_CTRL = pwr_ctrl & ~PWR_NORMAL_RUN_MODE;
+
+    /* Configure HCLK PLL */
+    LPC32XX_HCLKPLL_CTRL = hclkpll_ctrl;
+    while ((LPC32XX_HCLKPLL_CTRL & HCLK_PLL_LOCK) == 0) {
+      /* Wait */
+    }
+
+    /* Setup HCLK divider */
+    LPC32XX_HCLKDIV_CTRL = hclkdiv_ctrl;
+
+    /* Enable HCLK PLL output */
+    LPC32XX_PWR_CTRL = pwr_ctrl | PWR_NORMAL_RUN_MODE;
+  }
+
+  return settings_ok;
+}
+
+#if LPC32XX_OSCILLATOR_MAIN != 13000000U
+  #error "unexpected main oscillator frequency"
+#endif
+
+static BSP_START_TEXT_SECTION void setup_pll(void)
+{
+  uint32_t hclkpll_ctrl = LPC32XX_HCLKPLL_CTRL_INIT_VALUE;
+  uint32_t hclkdiv_ctrl = LPC32XX_HCLKDIV_CTRL_INIT_VALUE;
+
+  lpc32xx_start_pll_setup(hclkpll_ctrl, hclkdiv_ctrl, false);
+}
+
+BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
+{
+  setup_pll();
+}
+
+static BSP_START_TEXT_SECTION void stop_dma_activities(void)
+{
+  #ifdef LPC32XX_STOP_GPDMA
+    LPC32XX_DO_STOP_GPDMA;
+  #endif
+
+  #ifdef LPC32XX_STOP_ETHERNET
+    LPC32XX_DO_STOP_ETHERNET;
+  #endif
+
+  #ifdef LPC32XX_STOP_USB
+    LPC32XX_DO_STOP_USB;
+  #endif
+}
+
+static BSP_START_TEXT_SECTION void setup_uarts(void)
+{
+  LPC32XX_UART_CTRL = 0x0;
+  LPC32XX_UART_LOOP = 0x0;
+
+  #ifdef LPC32XX_UART_5_BAUD
+    LPC32XX_UARTCLK_CTRL |= 1U << 2;
+    LPC32XX_U5CLK = LPC32XX_CONFIG_U5CLK;
+    LPC32XX_UART_CLKMODE = BSP_FLD32SET(LPC32XX_UART_CLKMODE, 0x2, 8, 9);
+    BSP_CONSOLE_UART_INIT(0x01);
+  #endif
+}
+
+static BSP_START_TEXT_SECTION void setup_timer(void)
+{
+  volatile lpc_timer *timer = LPC32XX_STANDARD_TIMER;
+
+  LPC32XX_TIMCLK_CTRL1 = (1U << 2) | (1U << 3);
+
+  timer->tcr = LPC_TIMER_TCR_RST;
+  timer->ctcr = 0x0;
+  timer->pr = 0x0;
+  timer->ir = 0xff;
+  timer->mcr = 0x0;
+  timer->ccr = 0x0;
+  timer->tcr = LPC_TIMER_TCR_EN;
+}
+
+BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
+{
+  stop_dma_activities();
+  bsp_start_copy_sections();
+  setup_mmu_and_cache();
+  setup_uarts();
+  setup_timer();
+  bsp_start_clear_bss();
+}
diff --git a/bsps/arm/lpc32xx/start/linkcmds.lpc32xx b/bsps/arm/lpc32xx/start/linkcmds.lpc32xx
new file mode 100644
index 0000000000..200e7f3e04
--- /dev/null
+++ b/bsps/arm/lpc32xx/start/linkcmds.lpc32xx
@@ -0,0 +1,17 @@
+/**
+ * @file
+ *
+ * @ingroup lpc32xx_linker
+ *
+ * @brief Linker support.
+ */
+
+bsp_translation_table_base = ORIGIN (RAM_MMU);
+
+lpc32xx = 0x20020000;
+
+lpc32xx_magic_zero_begin = 0x05000000;
+lpc32xx_magic_zero_end = 0x07000000;
+lpc32xx_magic_zero_size = lpc32xx_magic_zero_end - lpc32xx_magic_zero_end;
+
+INCLUDE linkcmds.armv4
diff --git a/bsps/arm/lpc32xx/start/linkcmds.lpc32xx_mzx b/bsps/arm/lpc32xx/start/linkcmds.lpc32xx_mzx
new file mode 100644
index 0000000000..127a82f79a
--- /dev/null
+++ b/bsps/arm/lpc32xx/start/linkcmds.lpc32xx_mzx
@@ -0,0 +1,69 @@
+/**
+ * @file
+ *
+ * @ingroup lpc32xx_linker_mzx
+ *
+ * @brief Memory map.
+ */
+
+/**
+ * @defgroup lpc32xx_linker_mzx MZX Application Memory Map
+ *
+ * @ingroup bsp_linker
+ *
+ * @brief MZX application memory map.
+ *
+ * <table>
+ *   <tr><th>Region Name</th><th>Region Begin</th><th>Region Size</th></tr>
+ *   <tr><td>RAM_INT</td><td>0x08000000</td><td>256k</td></tr>
+ *   <tr><td>RAM_MMU</td><td>0x80000000</td><td>16k</td></tr>
+ *   <tr><td>RAM_EXT</td><td>0x80004000</td><td>32M - 16k</td></tr>
+ * </table>
+ *
+ * <table>
+ *   <tr><th>Section Name</th><th>Section Runtime Region</th><th>Section Load Region</th></tr>
+ *   <tr><td>.start</td><td>RAM_EXT</td><td></td></tr>
+ *   <tr><td>.vector</td><td>RAM_INT</td><td></td></tr>
+ *   <tr><td>.text</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.rodata</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.data</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.fast</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.bss</td><td>RAM_EXT</td><td></td></tr>
+ *   <tr><td>.work</td><td>RAM_EXT</td><td></td></tr>
+ *   <tr><td>.stack</td><td>RAM_INT</td><td></td></tr>
+ * </table>
+ */
+
+MEMORY {
+	RAM_INT : ORIGIN = 0x08000000, LENGTH = 256k
+	RAM_MMU : ORIGIN = 0x80000000, LENGTH = 16k /* SDRAM on DYCS0 */
+	RAM_SCRATCH : ORIGIN = 0x80004000, LENGTH = 4k /* SDRAM on DYCS0 */
+	RAM_EXT : ORIGIN = 0x80005000, LENGTH = 32M - 20k /* SDRAM on DYCS0 */
+}
+
+REGION_ALIAS ("REGION_START", RAM_EXT);
+REGION_ALIAS ("REGION_VECTOR", RAM_INT);
+REGION_ALIAS ("REGION_TEXT", RAM_EXT);
+REGION_ALIAS ("REGION_TEXT_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_RODATA", RAM_EXT);
+REGION_ALIAS ("REGION_RODATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_DATA", RAM_EXT);
+REGION_ALIAS ("REGION_DATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_FAST_TEXT", RAM_EXT);
+REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_FAST_DATA", RAM_EXT);
+REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_BSS", RAM_EXT);
+REGION_ALIAS ("REGION_WORK", RAM_EXT);
+REGION_ALIAS ("REGION_STACK", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_INT);
+
+lpc32xx_scratch_area = ORIGIN (RAM_SCRATCH);
+
+bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 4096;
+bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024;
+
+bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M;
+
+INCLUDE linkcmds.lpc32xx
diff --git a/bsps/arm/lpc32xx/start/linkcmds.lpc32xx_mzx_stage_1 b/bsps/arm/lpc32xx/start/linkcmds.lpc32xx_mzx_stage_1
new file mode 100644
index 0000000000..eae076e235
--- /dev/null
+++ b/bsps/arm/lpc32xx/start/linkcmds.lpc32xx_mzx_stage_1
@@ -0,0 +1,68 @@
+/**
+ * @file
+ *
+ * @ingroup lpc32xx_linker_mzx_stage_1
+ *
+ * @brief Memory map.
+ */
+
+/**
+ * @defgroup lpc32xx_linker_mzx_stage_1 MZX Stage-1 Program Memory Map
+ *
+ * @ingroup bsp_linker
+ *
+ * @brief MZX stage-1 program memory map.
+ *
+ * <table>
+ *   <tr><th>Region Name</th><th>Region Begin</th><th>Region Size</th></tr>
+ *   <tr><td>RAM_INT</td><td>0x08000000</td><td>232k</td></tr>
+ *   <tr><td>RAM_MMU</td><td>0x0803a000</td><td>16k</td></tr>
+ *   <tr><td>RAM_VEC</td><td>0x0803d000</td><td>8k</td></tr>
+ * </table>
+ *
+ * <table>
+ *   <tr><th>Section Name</th><th>Section Runtime Region</th><th>Section Load Region</th></tr>
+ *   <tr><td>.start</td><td>RAM_INT</td><td></td></tr>
+ *   <tr><td>.vector</td><td>RAM_INT</td><td></td></tr>
+ *   <tr><td>.text</td><td>RAM_INT</td><td>RAM_INT</td></tr>
+ *   <tr><td>.rodata</td><td>RAM_INT</td><td>RAM_INT</td></tr>
+ *   <tr><td>.data</td><td>RAM_INT</td><td>RAM_INT</td></tr>
+ *   <tr><td>.fast</td><td>RAM_INT</td><td>RAM_INT</td></tr>
+ *   <tr><td>.bss</td><td>RAM_INT</td><td></td></tr>
+ *   <tr><td>.work</td><td>RAM_INT</td><td></td></tr>
+ *   <tr><td>.stack</td><td>RAM_INT</td><td></td></tr>
+ * </table>
+ */
+
+MEMORY {
+	RAM_INT : ORIGIN = 0x08000000, LENGTH = 232k
+	RAM_VEC : ORIGIN = 0x0803a000, LENGTH = 8k
+	RAM_MMU : ORIGIN = 0x0803c000, LENGTH = 16k
+	RAM_SCRATCH : ORIGIN = 0x80004000, LENGTH = 4k /* SDRAM on DYCS0 */
+}
+
+REGION_ALIAS ("REGION_START", RAM_INT);
+REGION_ALIAS ("REGION_VECTOR", RAM_VEC);
+REGION_ALIAS ("REGION_TEXT", RAM_INT);
+REGION_ALIAS ("REGION_TEXT_LOAD", RAM_INT);
+REGION_ALIAS ("REGION_RODATA", RAM_INT);
+REGION_ALIAS ("REGION_RODATA_LOAD", RAM_INT);
+REGION_ALIAS ("REGION_DATA", RAM_INT);
+REGION_ALIAS ("REGION_DATA_LOAD", RAM_INT);
+REGION_ALIAS ("REGION_FAST_TEXT", RAM_INT);
+REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM_INT);
+REGION_ALIAS ("REGION_FAST_DATA", RAM_INT);
+REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM_INT);
+REGION_ALIAS ("REGION_BSS", RAM_INT);
+REGION_ALIAS ("REGION_WORK", RAM_INT);
+REGION_ALIAS ("REGION_STACK", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_INT);
+
+lpc32xx_scratch_area = ORIGIN (RAM_SCRATCH);
+
+bsp_stack_svc_size = DEFINED (bsp_stack_svc_size) ? bsp_stack_svc_size : 7168;
+
+bsp_vector_table_in_start_section = 1;
+
+INCLUDE linkcmds.lpc32xx
diff --git a/bsps/arm/lpc32xx/start/linkcmds.lpc32xx_mzx_stage_2 b/bsps/arm/lpc32xx/start/linkcmds.lpc32xx_mzx_stage_2
new file mode 100644
index 0000000000..2aa8c34091
--- /dev/null
+++ b/bsps/arm/lpc32xx/start/linkcmds.lpc32xx_mzx_stage_2
@@ -0,0 +1,67 @@
+/**
+ * @file
+ *
+ * @ingroup lpc32xx_linker_mzx_stage_2
+ *
+ * @brief Memory map.
+ */
+
+/**
+ * @defgroup lpc32xx_linker_mzx_stage_2 MZX Stage-2 Program Memory Map
+ *
+ * @ingroup bsp_linker
+ *
+ * @brief MZX stage-2 program memory map.
+ *
+ * <table>
+ *   <tr><th>Region Name</th><th>Region Begin</th><th>Region Size</th></tr>
+ *   <tr><td>RAM_INT</td><td>0x08000000</td><td>256k</td></tr>
+ *   <tr><td>RAM_MMU</td><td>0x81c00000</td><td>16k</td></tr>
+ *   <tr><td>RAM_EXT</td><td>0x81c04000</td><td>4M - 16k</td></tr>
+ * </table>
+ *
+ * <table>
+ *   <tr><th>Section Name</th><th>Section Runtime Region</th><th>Section Load Region</th></tr>
+ *   <tr><td>.start</td><td>RAM_EXT</td><td></td></tr>
+ *   <tr><td>.vector</td><td>RAM_INT</td><td></td></tr>
+ *   <tr><td>.text</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.rodata</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.data</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.fast</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.bss</td><td>RAM_EXT</td><td></td></tr>
+ *   <tr><td>.work</td><td>RAM_EXT</td><td></td></tr>
+ *   <tr><td>.stack</td><td>RAM_INT</td><td></td></tr>
+ * </table>
+ */
+
+MEMORY {
+	RAM_INT : ORIGIN = 0x08000000, LENGTH = 240k
+	RAM_FAST : ORIGIN = 0x0803c000, LENGTH = 16k
+	RAM_MMU : ORIGIN = 0x80000000, LENGTH = 16k /* SDRAM on DYCS0 */
+	RAM_SCRATCH : ORIGIN = 0x80004000, LENGTH = 4k /* SDRAM on DYCS0 */
+	RAM_EXT : ORIGIN = 0x81c00000, LENGTH = 4M /* SDRAM on DYCS0 */
+}
+
+REGION_ALIAS ("REGION_START", RAM_EXT);
+REGION_ALIAS ("REGION_VECTOR", RAM_INT);
+REGION_ALIAS ("REGION_TEXT", RAM_EXT);
+REGION_ALIAS ("REGION_TEXT_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_RODATA", RAM_EXT);
+REGION_ALIAS ("REGION_RODATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_DATA", RAM_EXT);
+REGION_ALIAS ("REGION_DATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_FAST_TEXT", RAM_FAST);
+REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_FAST_DATA", RAM_FAST);
+REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_BSS", RAM_EXT);
+REGION_ALIAS ("REGION_WORK", RAM_EXT);
+REGION_ALIAS ("REGION_STACK", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_INT);
+
+lpc32xx_scratch_area = ORIGIN (RAM_SCRATCH);
+
+bsp_stack_svc_size = DEFINED (bsp_stack_svc_size) ? bsp_stack_svc_size : 8192;
+
+INCLUDE linkcmds.lpc32xx
diff --git a/bsps/arm/lpc32xx/start/linkcmds.lpc32xx_phycore b/bsps/arm/lpc32xx/start/linkcmds.lpc32xx_phycore
new file mode 100644
index 0000000000..d874c46152
--- /dev/null
+++ b/bsps/arm/lpc32xx/start/linkcmds.lpc32xx_phycore
@@ -0,0 +1,68 @@
+/**
+ * @file
+ *
+ * @ingroup lpc32xx_linker_phycore
+ *
+ * @brief Memory map.
+ */
+
+/**
+ * @defgroup lpc32xx_linker_phycore phyCORE-LPC3250 Memory Map
+ *
+ * @ingroup bsp_linker
+ *
+ * @brief phyCORE-LPC3250 memory map.
+ *
+ * <table>
+ *   <tr><th>Region Name</th><th>Region Begin</th><th>Region Size</th></tr>
+ *   <tr><td>RAM_INT</td><td>0x08000000</td><td>256k</td></tr>
+ *   <tr><td>RAM_MMU</td><td>0x80000000</td><td>16k</td></tr>
+ *   <tr><td>RAM_EXT</td><td>0x80004000</td><td>64M - 16k</td></tr>
+ *   <tr><td>ROM_EXT</td><td>0xe0000000</td><td>2M</td></tr>
+ * </table>
+ *
+ * <table>
+ *   <tr><th>Section Name</th><th>Section Runtime Region</th><th>Section Load Region</th></tr>
+ *   <tr><td>.start</td><td>RAM_EXT</td><td></td></tr>
+ *   <tr><td>.vector</td><td>RAM_INT</td><td></td></tr>
+ *   <tr><td>.text</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.rodata</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.data</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.fast</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.bss</td><td>RAM_EXT</td><td></td></tr>
+ *   <tr><td>.work</td><td>RAM_EXT</td><td></td></tr>
+ *   <tr><td>.stack</td><td>RAM_INT</td><td></td></tr>
+ * </table>
+ */
+
+MEMORY {
+	RAM_INT : ORIGIN = 0x08000000, LENGTH = 256k
+	RAM_MMU : ORIGIN = 0x80000000, LENGTH = 16k /* SDRAM on DYCS0 */
+	RAM_EXT : ORIGIN = 0x80004000, LENGTH = 64M - 16k /* SDRAM on DYCS0 */
+	ROM_EXT : ORIGIN = 0xe0000000, LENGTH = 2M /* NOR flash on CS0 */
+}
+
+REGION_ALIAS ("REGION_START", RAM_EXT);
+REGION_ALIAS ("REGION_VECTOR", RAM_INT);
+REGION_ALIAS ("REGION_TEXT", RAM_EXT);
+REGION_ALIAS ("REGION_TEXT_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_RODATA", RAM_EXT);
+REGION_ALIAS ("REGION_RODATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_DATA", RAM_EXT);
+REGION_ALIAS ("REGION_DATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_FAST_TEXT", RAM_EXT);
+REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_FAST_DATA", RAM_EXT);
+REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_BSS", RAM_EXT);
+REGION_ALIAS ("REGION_WORK", RAM_EXT);
+REGION_ALIAS ("REGION_STACK", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_INT);
+
+bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 4096;
+bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024;
+
+bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M;
+
+INCLUDE linkcmds.lpc32xx