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authorSebastian Huber <sebastian.huber@embedded-brains.de>2022-06-07 15:42:41 +0200
committerSebastian Huber <sebastian.huber@embedded-brains.de>2022-06-08 10:25:41 +0200
commit4d0d7d5413226733589b3647258a43570fbfb983 (patch)
treef92e23490d8dd6a2de29e015689ebaad74d36f8e /bsps/arm/lpc32xx
parentbsp/lpc32xx: Use standard timer 2 for tm27.h (diff)
downloadrtems-4d0d7d5413226733589b3647258a43570fbfb983.tar.bz2
bsp/lpc32xx: bsp_interrupt_is_valid_vector()
Provide custom bsp_interrupt_is_valid_vector() implementation since several interrupt vectors are reserved.
Diffstat (limited to 'bsps/arm/lpc32xx')
-rw-r--r--bsps/arm/lpc32xx/include/bsp/irq.h4
-rw-r--r--bsps/arm/lpc32xx/irq/irq.c27
2 files changed, 31 insertions, 0 deletions
diff --git a/bsps/arm/lpc32xx/include/bsp/irq.h b/bsps/arm/lpc32xx/include/bsp/irq.h
index d8ad65b3d2..255c556a96 100644
--- a/bsps/arm/lpc32xx/include/bsp/irq.h
+++ b/bsps/arm/lpc32xx/include/bsp/irq.h
@@ -136,8 +136,12 @@ extern "C" {
#define BSP_INTERRUPT_VECTOR_COUNT (LPC32XX_IRQ_SYSCLK + 1)
+#define BSP_INTERRUPT_CUSTOM_VALID_VECTOR
+
#define LPC32XX_IRQ_COUNT BSP_INTERRUPT_VECTOR_COUNT
+bool bsp_interrupt_is_valid_vector(rtems_vector_number vector);
+
void lpc32xx_irq_set_priority(rtems_vector_number vector, unsigned priority);
unsigned lpc32xx_irq_get_priority(rtems_vector_number vector);
diff --git a/bsps/arm/lpc32xx/irq/irq.c b/bsps/arm/lpc32xx/irq/irq.c
index 947faca52c..a62eee6dd5 100644
--- a/bsps/arm/lpc32xx/irq/irq.c
+++ b/bsps/arm/lpc32xx/irq/irq.c
@@ -41,6 +41,14 @@ static lpc32xx_irq_fields lpc32xx_irq_priority_masks [LPC32XX_IRQ_PRIORITY_COUNT
static lpc32xx_irq_fields lpc32xx_irq_enable;
+static const lpc32xx_irq_fields lpc32xx_irq_is_valid = {
+ .field = {
+ .mic = 0x3fffeff8U,
+ .sic_1 = 0xffde71d6U,
+ .sic_2 = 0x9fdc9fffU
+ }
+};
+
static inline bool lpc32xx_irq_priority_is_valid(unsigned priority)
{
return priority <= LPC32XX_IRQ_PRIORITY_LOWEST;
@@ -84,6 +92,16 @@ static inline void lpc32xx_irq_clear_bit_in_register(unsigned index, unsigned re
*reg &= ~(1U << bit);
}
+static inline bool lpc32xx_irq_is_bit_set_in_field(
+ unsigned index,
+ const lpc32xx_irq_fields *fields
+)
+{
+ LPC32XX_IRQ_BIT_OPS_DEFINE;
+
+ return fields->fields_table [module] & (1U << bit);
+}
+
static inline void lpc32xx_irq_set_bit_in_field(unsigned index, lpc32xx_irq_fields *fields)
{
LPC32XX_IRQ_BIT_OPS_DEFINE;
@@ -98,6 +116,15 @@ static inline void lpc32xx_irq_clear_bit_in_field(unsigned index, lpc32xx_irq_fi
fields->fields_table [module] &= ~(1U << bit);
}
+bool bsp_interrupt_is_valid_vector(rtems_vector_number vector)
+{
+ if (vector >= BSP_INTERRUPT_VECTOR_COUNT) {
+ return false;
+ }
+
+ return lpc32xx_irq_is_bit_set_in_field(vector, &lpc32xx_irq_is_valid);
+}
+
static inline unsigned lpc32xx_irq_get_index(uint32_t val)
{
ARM_SWITCH_REGISTERS;