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author | Christian Mauderer <christian.mauderer@embedded-brains.de> | 2020-10-12 13:40:30 +0200 |
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committer | Christian Mauderer <christian.mauderer@embedded-brains.de> | 2020-11-20 08:53:18 +0100 |
commit | 48f6a6c302a3e1a3f8915e2503d0fe618d1af285 (patch) | |
tree | b5d570ddd5e432519c5a9d42b4cf6725d8161551 /bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_gpc.c | |
parent | cpu/armv7m: Add table based init for ARMV7M_MPU (diff) | |
download | rtems-48f6a6c302a3e1a3f8915e2503d0fe618d1af285.tar.bz2 |
bsp/imxrt: Import files from MCUXpresso SDK V2.8.5
The following files have been imported:
cp ${SDK}/boards/evkbimxrt1050/project_template/clock_config.c nxp/boards/evkbimxrt1050
cp ${SDK}/boards/evkbimxrt1050/project_template/clock_config.h include/fsl_clock_config.h
cp ${SDK}/boards/evkbimxrt1050/project_template/dcd.c start/flash-dcd.c
cp ${SDK}/boards/evkbimxrt1050/project_template/pin_mux.c nxp/boards/evkbimxrt1050
cp ${SDK}/boards/evkbimxrt1050/project_template/pin_mux.h include/fsl_pin_mux.h
cp ${SDK}/boards/evkbimxrt1050/xip/evkbimxrt1050_flexspi_nor_config.h include/fsl_flexspi_nor_config.h
cp ${SDK}/devices/MIMXRT1052/MIMXRT1052.h include
cp ${SDK}/devices/MIMXRT1052/MIMXRT1052_features.h include
cp ${SDK}/devices/MIMXRT1052/drivers/fsl_*.c nxp/devices/MIMXRT1052/drivers
cp ${SDK}/devices/MIMXRT1052/drivers/fsl_*.h include
cp ${SDK}/devices/MIMXRT1052/fsl_device_registers.h include
cp ${SDK}/devices/MIMXRT1052/system_MIMXRT1052.h include/
cp ${SDK}/devices/MIMXRT1052/xip/fsl_flexspi_nor_boot.c nxp/devices/MIMXRT1052/xip/fsl_flexspi_nor_boot.c
cp ${SDK}/devices/MIMXRT1052/xip/fsl_flexspi_nor_boot.h include
Update #4180
Diffstat (limited to 'bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_gpc.c')
-rw-r--r-- | bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_gpc.c | 103 |
1 files changed, 103 insertions, 0 deletions
diff --git a/bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_gpc.c b/bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_gpc.c new file mode 100644 index 0000000000..e5cef48d1b --- /dev/null +++ b/bsps/arm/imxrt/nxp/devices/MIMXRT1052/drivers/fsl_gpc.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_gpc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.gpc_1" +#endif + +/*! + * brief Enable the IRQ. + * + * param base GPC peripheral base address. + * param irqId ID number of IRQ to be enabled, available range is 32-159. 0-31 is available in some platforms. + */ +void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId) +{ + uint32_t irqRegNum = irqId / 32U; + uint32_t irqRegShiftNum = irqId % 32U; + + assert(irqRegNum <= GPC_IMR_COUNT); + +#if ((defined FSL_FEATURE_GPC_HAS_IRQ_0_31) && FSL_FEATURE_GPC_HAS_IRQ_0_31) + if (irqRegNum == GPC_IMR_COUNT) + { + base->IMR5 &= ~(1UL << irqRegShiftNum); + } + else + { + base->IMR[irqRegNum] &= ~(1UL << irqRegShiftNum); + } +#else + assert(irqRegNum > 0U); + base->IMR[irqRegNum - 1UL] &= ~(1UL << irqRegShiftNum); +#endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */ +} + +/*! + * brief Disable the IRQ. + * + * param base GPC peripheral base address. + * param irqId ID number of IRQ to be disabled, available range is 32-159. 0-31 is available in some platforms. + */ +void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId) +{ + uint32_t irqRegNum = irqId / 32U; + uint32_t irqRegShiftNum = irqId % 32U; + + assert(irqRegNum <= GPC_IMR_COUNT); + +#if ((defined FSL_FEATURE_GPC_HAS_IRQ_0_31) && FSL_FEATURE_GPC_HAS_IRQ_0_31) + if (irqRegNum == GPC_IMR_COUNT) + { + base->IMR5 |= (1UL << irqRegShiftNum); + } + else + { + base->IMR[irqRegNum] |= (1UL << irqRegShiftNum); + } +#else + assert(irqRegNum > 0U); + base->IMR[irqRegNum - 1UL] |= (1UL << irqRegShiftNum); +#endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */ +} + +/*! + * brief Get the IRQ/Event flag. + * + * param base GPC peripheral base address. + * param irqId ID number of IRQ to be enabled, available range is 32-159. 0-31 is available in some platforms. + * return Indicated IRQ/Event is asserted or not. + */ +bool GPC_GetIRQStatusFlag(GPC_Type *base, uint32_t irqId) +{ + uint32_t irqRegNum = irqId / 32U; + uint32_t irqRegShiftNum = irqId % 32U; + uint32_t ret; + + assert(irqRegNum <= GPC_IMR_COUNT); + +#if ((defined FSL_FEATURE_GPC_HAS_IRQ_0_31) && FSL_FEATURE_GPC_HAS_IRQ_0_31) + if (irqRegNum == GPC_IMR_COUNT) + { + ret = base->ISR5 & (1UL << irqRegShiftNum); + } + else + { + ret = base->ISR[irqRegNum] & (1UL << irqRegShiftNum); + } +#else + assert(irqRegNum > 0U); + ret = base->ISR[irqRegNum - 1UL] & (1UL << irqRegShiftNum); +#endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */ + + return (1UL << irqRegShiftNum) == ret; +} |